2 * srmmu.c: SRMMU specific routines for memory management.
4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1995,2002 Pete Zaitcev (zaitcev@yahoo.com)
6 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
7 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 * Copyright (C) 1999,2000 Anton Blanchard (anton@samba.org)
11 #include <linux/kernel.h>
13 #include <linux/vmalloc.h>
14 #include <linux/pagemap.h>
15 #include <linux/init.h>
16 #include <linux/spinlock.h>
17 #include <linux/bootmem.h>
19 #include <linux/seq_file.h>
20 #include <linux/kdebug.h>
21 #include <linux/log2.h>
22 #include <linux/gfp.h>
24 #include <asm/bitext.h>
26 #include <asm/pgalloc.h>
27 #include <asm/pgtable.h>
29 #include <asm/vaddrs.h>
30 #include <asm/traps.h>
33 #include <asm/cache.h>
34 #include <asm/oplib.h>
37 #include <asm/mmu_context.h>
38 #include <asm/io-unit.h>
39 #include <asm/cacheflush.h>
40 #include <asm/tlbflush.h>
42 /* Now the cpu specific definitions. */
43 #include <asm/viking.h>
46 #include <asm/tsunami.h>
47 #include <asm/swift.h>
48 #include <asm/turbosparc.h>
51 #include <asm/btfixup.h>
53 enum mbus_module srmmu_modtype;
54 static unsigned int hwbug_bitmask;
58 struct ctx_list *ctx_list_pool;
59 struct ctx_list ctx_free;
60 struct ctx_list ctx_used;
62 extern struct resource sparc_iomap;
64 extern unsigned long last_valid_pfn;
66 static pgd_t *srmmu_swapper_pg_dir;
69 #define FLUSH_BEGIN(mm)
72 #define FLUSH_BEGIN(mm) if((mm)->context != NO_CONTEXT) {
76 BTFIXUPDEF_CALL(void, flush_page_for_dma, unsigned long)
77 #define flush_page_for_dma(page) BTFIXUP_CALL(flush_page_for_dma)(page)
79 int flush_page_for_dma_global = 1;
82 BTFIXUPDEF_CALL(void, local_flush_page_for_dma, unsigned long)
83 #define local_flush_page_for_dma(page) BTFIXUP_CALL(local_flush_page_for_dma)(page)
88 ctxd_t *srmmu_ctx_table_phys;
89 static ctxd_t *srmmu_context_table;
91 int viking_mxcc_present;
92 static DEFINE_SPINLOCK(srmmu_context_spinlock);
94 static int is_hypersparc;
96 static int srmmu_cache_pagetables;
98 /* these will be initialized in srmmu_nocache_calcsize() */
99 static unsigned long srmmu_nocache_size;
100 static unsigned long srmmu_nocache_end;
102 /* 1 bit <=> 256 bytes of nocache <=> 64 PTEs */
103 #define SRMMU_NOCACHE_BITMAP_SHIFT (PAGE_SHIFT - 4)
105 /* The context table is a nocache user with the biggest alignment needs. */
106 #define SRMMU_NOCACHE_ALIGN_MAX (sizeof(ctxd_t)*SRMMU_MAX_CONTEXTS)
108 void *srmmu_nocache_pool;
109 void *srmmu_nocache_bitmap;
110 static struct bit_map srmmu_nocache_map;
112 static inline int srmmu_pte_none(pte_t pte)
113 { return !(pte_val(pte) & 0xFFFFFFF); }
115 static inline int srmmu_pmd_none(pmd_t pmd)
116 { return !(pmd_val(pmd) & 0xFFFFFFF); }
118 static inline pte_t srmmu_pte_wrprotect(pte_t pte)
119 { return __pte(pte_val(pte) & ~SRMMU_WRITE);}
121 static inline pte_t srmmu_pte_mkclean(pte_t pte)
122 { return __pte(pte_val(pte) & ~SRMMU_DIRTY);}
124 static inline pte_t srmmu_pte_mkold(pte_t pte)
125 { return __pte(pte_val(pte) & ~SRMMU_REF);}
127 /* XXX should we hyper_flush_whole_icache here - Anton */
128 static inline void srmmu_ctxd_set(ctxd_t *ctxp, pgd_t *pgdp)
129 { set_pte((pte_t *)ctxp, (SRMMU_ET_PTD | (__nocache_pa((unsigned long) pgdp) >> 4))); }
131 void pmd_set(pmd_t *pmdp, pte_t *ptep)
133 unsigned long ptp; /* Physical address, shifted right by 4 */
136 ptp = __nocache_pa((unsigned long) ptep) >> 4;
137 for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) {
138 set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp);
139 ptp += (SRMMU_REAL_PTRS_PER_PTE*sizeof(pte_t) >> 4);
143 void pmd_populate(struct mm_struct *mm, pmd_t *pmdp, struct page *ptep)
145 unsigned long ptp; /* Physical address, shifted right by 4 */
148 ptp = page_to_pfn(ptep) << (PAGE_SHIFT-4); /* watch for overflow */
149 for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) {
150 set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp);
151 ptp += (SRMMU_REAL_PTRS_PER_PTE*sizeof(pte_t) >> 4);
155 static inline pte_t srmmu_pte_modify(pte_t pte, pgprot_t newprot)
156 { return __pte((pte_val(pte) & SRMMU_CHG_MASK) | pgprot_val(newprot)); }
158 /* to find an entry in a top-level page table... */
159 static inline pgd_t *srmmu_pgd_offset(struct mm_struct * mm, unsigned long address)
160 { return mm->pgd + (address >> SRMMU_PGDIR_SHIFT); }
162 /* Find an entry in the third-level page table.. */
163 pte_t *pte_offset_kernel(pmd_t * dir, unsigned long address)
167 pte = __nocache_va((dir->pmdv[0] & SRMMU_PTD_PMASK) << 4);
168 return (pte_t *) pte +
169 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1));
173 * size: bytes to allocate in the nocache area.
174 * align: bytes, number to align at.
175 * Returns the virtual address of the allocated area.
177 static unsigned long __srmmu_get_nocache(int size, int align)
181 if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {
182 printk("Size 0x%x too small for nocache request\n", size);
183 size = SRMMU_NOCACHE_BITMAP_SHIFT;
185 if (size & (SRMMU_NOCACHE_BITMAP_SHIFT-1)) {
186 printk("Size 0x%x unaligned int nocache request\n", size);
187 size += SRMMU_NOCACHE_BITMAP_SHIFT-1;
189 BUG_ON(align > SRMMU_NOCACHE_ALIGN_MAX);
191 offset = bit_map_string_get(&srmmu_nocache_map,
192 size >> SRMMU_NOCACHE_BITMAP_SHIFT,
193 align >> SRMMU_NOCACHE_BITMAP_SHIFT);
195 printk("srmmu: out of nocache %d: %d/%d\n",
196 size, (int) srmmu_nocache_size,
197 srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
201 return (SRMMU_NOCACHE_VADDR + (offset << SRMMU_NOCACHE_BITMAP_SHIFT));
204 unsigned long srmmu_get_nocache(int size, int align)
208 tmp = __srmmu_get_nocache(size, align);
211 memset((void *)tmp, 0, size);
216 void srmmu_free_nocache(unsigned long vaddr, int size)
220 if (vaddr < SRMMU_NOCACHE_VADDR) {
221 printk("Vaddr %lx is smaller than nocache base 0x%lx\n",
222 vaddr, (unsigned long)SRMMU_NOCACHE_VADDR);
225 if (vaddr+size > srmmu_nocache_end) {
226 printk("Vaddr %lx is bigger than nocache end 0x%lx\n",
227 vaddr, srmmu_nocache_end);
230 if (!is_power_of_2(size)) {
231 printk("Size 0x%x is not a power of 2\n", size);
234 if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {
235 printk("Size 0x%x is too small\n", size);
238 if (vaddr & (size-1)) {
239 printk("Vaddr %lx is not aligned to size 0x%x\n", vaddr, size);
243 offset = (vaddr - SRMMU_NOCACHE_VADDR) >> SRMMU_NOCACHE_BITMAP_SHIFT;
244 size = size >> SRMMU_NOCACHE_BITMAP_SHIFT;
246 bit_map_clear(&srmmu_nocache_map, offset, size);
249 static void srmmu_early_allocate_ptable_skeleton(unsigned long start,
252 extern unsigned long probe_memory(void); /* in fault.c */
255 * Reserve nocache dynamically proportionally to the amount of
256 * system RAM. -- Tomas Szepe <szepe@pinerecords.com>, June 2002
258 static void srmmu_nocache_calcsize(void)
260 unsigned long sysmemavail = probe_memory() / 1024;
261 int srmmu_nocache_npages;
263 srmmu_nocache_npages =
264 sysmemavail / SRMMU_NOCACHE_ALCRATIO / 1024 * 256;
266 /* P3 XXX The 4x overuse: corroborated by /proc/meminfo. */
267 // if (srmmu_nocache_npages < 256) srmmu_nocache_npages = 256;
268 if (srmmu_nocache_npages < SRMMU_MIN_NOCACHE_PAGES)
269 srmmu_nocache_npages = SRMMU_MIN_NOCACHE_PAGES;
271 /* anything above 1280 blows up */
272 if (srmmu_nocache_npages > SRMMU_MAX_NOCACHE_PAGES)
273 srmmu_nocache_npages = SRMMU_MAX_NOCACHE_PAGES;
275 srmmu_nocache_size = srmmu_nocache_npages * PAGE_SIZE;
276 srmmu_nocache_end = SRMMU_NOCACHE_VADDR + srmmu_nocache_size;
279 static void __init srmmu_nocache_init(void)
281 unsigned int bitmap_bits;
285 unsigned long paddr, vaddr;
286 unsigned long pteval;
288 bitmap_bits = srmmu_nocache_size >> SRMMU_NOCACHE_BITMAP_SHIFT;
290 srmmu_nocache_pool = __alloc_bootmem(srmmu_nocache_size,
291 SRMMU_NOCACHE_ALIGN_MAX, 0UL);
292 memset(srmmu_nocache_pool, 0, srmmu_nocache_size);
294 srmmu_nocache_bitmap = __alloc_bootmem(bitmap_bits >> 3, SMP_CACHE_BYTES, 0UL);
295 bit_map_init(&srmmu_nocache_map, srmmu_nocache_bitmap, bitmap_bits);
297 srmmu_swapper_pg_dir = (pgd_t *)__srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
298 memset(__nocache_fix(srmmu_swapper_pg_dir), 0, SRMMU_PGD_TABLE_SIZE);
299 init_mm.pgd = srmmu_swapper_pg_dir;
301 srmmu_early_allocate_ptable_skeleton(SRMMU_NOCACHE_VADDR, srmmu_nocache_end);
303 paddr = __pa((unsigned long)srmmu_nocache_pool);
304 vaddr = SRMMU_NOCACHE_VADDR;
306 while (vaddr < srmmu_nocache_end) {
307 pgd = pgd_offset_k(vaddr);
308 pmd = pmd_offset(__nocache_fix(pgd), vaddr);
309 pte = pte_offset_kernel(__nocache_fix(pmd), vaddr);
311 pteval = ((paddr >> 4) | SRMMU_ET_PTE | SRMMU_PRIV);
313 if (srmmu_cache_pagetables)
314 pteval |= SRMMU_CACHE;
316 set_pte(__nocache_fix(pte), __pte(pteval));
326 pgd_t *get_pgd_fast(void)
330 pgd = (pgd_t *)__srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
332 pgd_t *init = pgd_offset_k(0);
333 memset(pgd, 0, USER_PTRS_PER_PGD * sizeof(pgd_t));
334 memcpy(pgd + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD,
335 (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
342 * Hardware needs alignment to 256 only, but we align to whole page size
343 * to reduce fragmentation problems due to the buddy principle.
344 * XXX Provide actual fragmentation statistics in /proc.
346 * Alignments up to the page size are the same for physical and virtual
347 * addresses of the nocache area.
349 pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address)
354 if ((pte = (unsigned long)pte_alloc_one_kernel(mm, address)) == 0)
356 page = pfn_to_page( __nocache_pa(pte) >> PAGE_SHIFT );
357 pgtable_page_ctor(page);
361 void pte_free(struct mm_struct *mm, pgtable_t pte)
365 pgtable_page_dtor(pte);
366 p = (unsigned long)page_address(pte); /* Cached address (for test) */
369 p = page_to_pfn(pte) << PAGE_SHIFT; /* Physical address */
370 p = (unsigned long) __nocache_va(p); /* Nocached virtual */
371 srmmu_free_nocache(p, PTE_SIZE);
376 static inline void alloc_context(struct mm_struct *old_mm, struct mm_struct *mm)
378 struct ctx_list *ctxp;
380 ctxp = ctx_free.next;
381 if(ctxp != &ctx_free) {
382 remove_from_ctx_list(ctxp);
383 add_to_used_ctxlist(ctxp);
384 mm->context = ctxp->ctx_number;
388 ctxp = ctx_used.next;
389 if(ctxp->ctx_mm == old_mm)
391 if(ctxp == &ctx_used)
392 panic("out of mmu contexts");
393 flush_cache_mm(ctxp->ctx_mm);
394 flush_tlb_mm(ctxp->ctx_mm);
395 remove_from_ctx_list(ctxp);
396 add_to_used_ctxlist(ctxp);
397 ctxp->ctx_mm->context = NO_CONTEXT;
399 mm->context = ctxp->ctx_number;
402 static inline void free_context(int context)
404 struct ctx_list *ctx_old;
406 ctx_old = ctx_list_pool + context;
407 remove_from_ctx_list(ctx_old);
408 add_to_free_ctxlist(ctx_old);
412 void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm,
413 struct task_struct *tsk)
415 if(mm->context == NO_CONTEXT) {
416 spin_lock(&srmmu_context_spinlock);
417 alloc_context(old_mm, mm);
418 spin_unlock(&srmmu_context_spinlock);
419 srmmu_ctxd_set(&srmmu_context_table[mm->context], mm->pgd);
422 if (sparc_cpu_model == sparc_leon)
426 hyper_flush_whole_icache();
428 srmmu_set_context(mm->context);
431 /* Low level IO area allocation on the SRMMU. */
432 static inline void srmmu_mapioaddr(unsigned long physaddr,
433 unsigned long virt_addr, int bus_type)
440 physaddr &= PAGE_MASK;
441 pgdp = pgd_offset_k(virt_addr);
442 pmdp = pmd_offset(pgdp, virt_addr);
443 ptep = pte_offset_kernel(pmdp, virt_addr);
444 tmp = (physaddr >> 4) | SRMMU_ET_PTE;
447 * I need to test whether this is consistent over all
448 * sun4m's. The bus_type represents the upper 4 bits of
449 * 36-bit physical address on the I/O space lines...
451 tmp |= (bus_type << 28);
453 __flush_page_to_ram(virt_addr);
454 set_pte(ptep, __pte(tmp));
457 void srmmu_mapiorange(unsigned int bus, unsigned long xpa,
458 unsigned long xva, unsigned int len)
462 srmmu_mapioaddr(xpa, xva, bus);
469 static inline void srmmu_unmapioaddr(unsigned long virt_addr)
475 pgdp = pgd_offset_k(virt_addr);
476 pmdp = pmd_offset(pgdp, virt_addr);
477 ptep = pte_offset_kernel(pmdp, virt_addr);
479 /* No need to flush uncacheable page. */
483 void srmmu_unmapiorange(unsigned long virt_addr, unsigned int len)
487 srmmu_unmapioaddr(virt_addr);
488 virt_addr += PAGE_SIZE;
494 * On the SRMMU we do not have the problems with limited tlb entries
495 * for mapping kernel pages, so we just take things from the free page
496 * pool. As a side effect we are putting a little too much pressure
497 * on the gfp() subsystem. This setup also makes the logic of the
498 * iommu mapping code a lot easier as we can transparently handle
499 * mappings on the kernel stack without any special code.
501 struct thread_info *alloc_thread_info_node(struct task_struct *tsk, int node)
503 struct thread_info *ret;
505 ret = (struct thread_info *)__get_free_pages(GFP_KERNEL,
507 #ifdef CONFIG_DEBUG_STACK_USAGE
509 memset(ret, 0, PAGE_SIZE << THREAD_INFO_ORDER);
510 #endif /* DEBUG_STACK_USAGE */
515 void free_thread_info(struct thread_info *ti)
517 free_pages((unsigned long)ti, THREAD_INFO_ORDER);
521 extern void tsunami_flush_cache_all(void);
522 extern void tsunami_flush_cache_mm(struct mm_struct *mm);
523 extern void tsunami_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
524 extern void tsunami_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
525 extern void tsunami_flush_page_to_ram(unsigned long page);
526 extern void tsunami_flush_page_for_dma(unsigned long page);
527 extern void tsunami_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
528 extern void tsunami_flush_tlb_all(void);
529 extern void tsunami_flush_tlb_mm(struct mm_struct *mm);
530 extern void tsunami_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
531 extern void tsunami_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
532 extern void tsunami_setup_blockops(void);
535 * Workaround, until we find what's going on with Swift. When low on memory,
536 * it sometimes loops in fault/handle_mm_fault incl. flush_tlb_page to find
537 * out it is already in page tables/ fault again on the same instruction.
538 * I really don't understand it, have checked it and contexts
539 * are right, flush_tlb_all is done as well, and it faults again...
542 * The following code is a deadwood that may be necessary when
543 * we start to make precise page flushes again. --zaitcev
545 static void swift_update_mmu_cache(struct vm_area_struct * vma, unsigned long address, pte_t *ptep)
548 static unsigned long last;
550 /* unsigned int n; */
552 if (address == last) {
553 val = srmmu_hwprobe(address);
554 if (val != 0 && pte_val(*ptep) != val) {
555 printk("swift_update_mmu_cache: "
556 "addr %lx put %08x probed %08x from %pf\n",
557 address, pte_val(*ptep), val,
558 __builtin_return_address(0));
559 srmmu_flush_whole_tlb();
567 extern void swift_flush_cache_all(void);
568 extern void swift_flush_cache_mm(struct mm_struct *mm);
569 extern void swift_flush_cache_range(struct vm_area_struct *vma,
570 unsigned long start, unsigned long end);
571 extern void swift_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
572 extern void swift_flush_page_to_ram(unsigned long page);
573 extern void swift_flush_page_for_dma(unsigned long page);
574 extern void swift_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
575 extern void swift_flush_tlb_all(void);
576 extern void swift_flush_tlb_mm(struct mm_struct *mm);
577 extern void swift_flush_tlb_range(struct vm_area_struct *vma,
578 unsigned long start, unsigned long end);
579 extern void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
581 #if 0 /* P3: deadwood to debug precise flushes on Swift. */
582 void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
587 if ((ctx1 = vma->vm_mm->context) != -1) {
588 cctx = srmmu_get_context();
589 /* Is context # ever different from current context? P3 */
591 printk("flush ctx %02x curr %02x\n", ctx1, cctx);
592 srmmu_set_context(ctx1);
593 swift_flush_page(page);
594 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
595 "r" (page), "i" (ASI_M_FLUSH_PROBE));
596 srmmu_set_context(cctx);
598 /* Rm. prot. bits from virt. c. */
599 /* swift_flush_cache_all(); */
600 /* swift_flush_cache_page(vma, page); */
601 swift_flush_page(page);
603 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
604 "r" (page), "i" (ASI_M_FLUSH_PROBE));
605 /* same as above: srmmu_flush_tlb_page() */
612 * The following are all MBUS based SRMMU modules, and therefore could
613 * be found in a multiprocessor configuration. On the whole, these
614 * chips seems to be much more touchy about DVMA and page tables
615 * with respect to cache coherency.
618 /* Cypress flushes. */
619 static void cypress_flush_cache_all(void)
621 volatile unsigned long cypress_sucks;
622 unsigned long faddr, tagval;
624 flush_user_windows();
625 for(faddr = 0; faddr < 0x10000; faddr += 0x20) {
626 __asm__ __volatile__("lda [%1 + %2] %3, %0\n\t" :
628 "r" (faddr), "r" (0x40000),
629 "i" (ASI_M_DATAC_TAG));
631 /* If modified and valid, kick it. */
632 if((tagval & 0x60) == 0x60)
633 cypress_sucks = *(unsigned long *)(0xf0020000 + faddr);
637 static void cypress_flush_cache_mm(struct mm_struct *mm)
639 register unsigned long a, b, c, d, e, f, g;
640 unsigned long flags, faddr;
644 flush_user_windows();
645 local_irq_save(flags);
646 octx = srmmu_get_context();
647 srmmu_set_context(mm->context);
648 a = 0x20; b = 0x40; c = 0x60;
649 d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
651 faddr = (0x10000 - 0x100);
656 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
657 "sta %%g0, [%0 + %2] %1\n\t"
658 "sta %%g0, [%0 + %3] %1\n\t"
659 "sta %%g0, [%0 + %4] %1\n\t"
660 "sta %%g0, [%0 + %5] %1\n\t"
661 "sta %%g0, [%0 + %6] %1\n\t"
662 "sta %%g0, [%0 + %7] %1\n\t"
663 "sta %%g0, [%0 + %8] %1\n\t" : :
664 "r" (faddr), "i" (ASI_M_FLUSH_CTX),
665 "r" (a), "r" (b), "r" (c), "r" (d),
666 "r" (e), "r" (f), "r" (g));
668 srmmu_set_context(octx);
669 local_irq_restore(flags);
673 static void cypress_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
675 struct mm_struct *mm = vma->vm_mm;
676 register unsigned long a, b, c, d, e, f, g;
677 unsigned long flags, faddr;
681 flush_user_windows();
682 local_irq_save(flags);
683 octx = srmmu_get_context();
684 srmmu_set_context(mm->context);
685 a = 0x20; b = 0x40; c = 0x60;
686 d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
688 start &= SRMMU_REAL_PMD_MASK;
690 faddr = (start + (0x10000 - 0x100));
695 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
696 "sta %%g0, [%0 + %2] %1\n\t"
697 "sta %%g0, [%0 + %3] %1\n\t"
698 "sta %%g0, [%0 + %4] %1\n\t"
699 "sta %%g0, [%0 + %5] %1\n\t"
700 "sta %%g0, [%0 + %6] %1\n\t"
701 "sta %%g0, [%0 + %7] %1\n\t"
702 "sta %%g0, [%0 + %8] %1\n\t" : :
704 "i" (ASI_M_FLUSH_SEG),
705 "r" (a), "r" (b), "r" (c), "r" (d),
706 "r" (e), "r" (f), "r" (g));
707 } while (faddr != start);
708 start += SRMMU_REAL_PMD_SIZE;
710 srmmu_set_context(octx);
711 local_irq_restore(flags);
715 static void cypress_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
717 register unsigned long a, b, c, d, e, f, g;
718 struct mm_struct *mm = vma->vm_mm;
719 unsigned long flags, line;
723 flush_user_windows();
724 local_irq_save(flags);
725 octx = srmmu_get_context();
726 srmmu_set_context(mm->context);
727 a = 0x20; b = 0x40; c = 0x60;
728 d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
731 line = (page + PAGE_SIZE) - 0x100;
736 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
737 "sta %%g0, [%0 + %2] %1\n\t"
738 "sta %%g0, [%0 + %3] %1\n\t"
739 "sta %%g0, [%0 + %4] %1\n\t"
740 "sta %%g0, [%0 + %5] %1\n\t"
741 "sta %%g0, [%0 + %6] %1\n\t"
742 "sta %%g0, [%0 + %7] %1\n\t"
743 "sta %%g0, [%0 + %8] %1\n\t" : :
745 "i" (ASI_M_FLUSH_PAGE),
746 "r" (a), "r" (b), "r" (c), "r" (d),
747 "r" (e), "r" (f), "r" (g));
748 } while(line != page);
749 srmmu_set_context(octx);
750 local_irq_restore(flags);
754 /* Cypress is copy-back, at least that is how we configure it. */
755 static void cypress_flush_page_to_ram(unsigned long page)
757 register unsigned long a, b, c, d, e, f, g;
760 a = 0x20; b = 0x40; c = 0x60; d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
762 line = (page + PAGE_SIZE) - 0x100;
767 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
768 "sta %%g0, [%0 + %2] %1\n\t"
769 "sta %%g0, [%0 + %3] %1\n\t"
770 "sta %%g0, [%0 + %4] %1\n\t"
771 "sta %%g0, [%0 + %5] %1\n\t"
772 "sta %%g0, [%0 + %6] %1\n\t"
773 "sta %%g0, [%0 + %7] %1\n\t"
774 "sta %%g0, [%0 + %8] %1\n\t" : :
776 "i" (ASI_M_FLUSH_PAGE),
777 "r" (a), "r" (b), "r" (c), "r" (d),
778 "r" (e), "r" (f), "r" (g));
779 } while(line != page);
782 /* Cypress is also IO cache coherent. */
783 static void cypress_flush_page_for_dma(unsigned long page)
787 /* Cypress has unified L2 VIPT, from which both instructions and data
788 * are stored. It does not have an onboard icache of any sort, therefore
789 * no flush is necessary.
791 static void cypress_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
795 static void cypress_flush_tlb_all(void)
797 srmmu_flush_whole_tlb();
800 static void cypress_flush_tlb_mm(struct mm_struct *mm)
803 __asm__ __volatile__(
804 "lda [%0] %3, %%g5\n\t"
805 "sta %2, [%0] %3\n\t"
806 "sta %%g0, [%1] %4\n\t"
807 "sta %%g5, [%0] %3\n"
809 : "r" (SRMMU_CTX_REG), "r" (0x300), "r" (mm->context),
810 "i" (ASI_M_MMUREGS), "i" (ASI_M_FLUSH_PROBE)
815 static void cypress_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
817 struct mm_struct *mm = vma->vm_mm;
821 start &= SRMMU_PGDIR_MASK;
822 size = SRMMU_PGDIR_ALIGN(end) - start;
823 __asm__ __volatile__(
824 "lda [%0] %5, %%g5\n\t"
827 "subcc %3, %4, %3\n\t"
829 " sta %%g0, [%2 + %3] %6\n\t"
830 "sta %%g5, [%0] %5\n"
832 : "r" (SRMMU_CTX_REG), "r" (mm->context), "r" (start | 0x200),
833 "r" (size), "r" (SRMMU_PGDIR_SIZE), "i" (ASI_M_MMUREGS),
834 "i" (ASI_M_FLUSH_PROBE)
839 static void cypress_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
841 struct mm_struct *mm = vma->vm_mm;
844 __asm__ __volatile__(
845 "lda [%0] %3, %%g5\n\t"
846 "sta %1, [%0] %3\n\t"
847 "sta %%g0, [%2] %4\n\t"
848 "sta %%g5, [%0] %3\n"
850 : "r" (SRMMU_CTX_REG), "r" (mm->context), "r" (page & PAGE_MASK),
851 "i" (ASI_M_MMUREGS), "i" (ASI_M_FLUSH_PROBE)
857 extern void viking_flush_cache_all(void);
858 extern void viking_flush_cache_mm(struct mm_struct *mm);
859 extern void viking_flush_cache_range(struct vm_area_struct *vma, unsigned long start,
861 extern void viking_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
862 extern void viking_flush_page_to_ram(unsigned long page);
863 extern void viking_flush_page_for_dma(unsigned long page);
864 extern void viking_flush_sig_insns(struct mm_struct *mm, unsigned long addr);
865 extern void viking_flush_page(unsigned long page);
866 extern void viking_mxcc_flush_page(unsigned long page);
867 extern void viking_flush_tlb_all(void);
868 extern void viking_flush_tlb_mm(struct mm_struct *mm);
869 extern void viking_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
871 extern void viking_flush_tlb_page(struct vm_area_struct *vma,
873 extern void sun4dsmp_flush_tlb_all(void);
874 extern void sun4dsmp_flush_tlb_mm(struct mm_struct *mm);
875 extern void sun4dsmp_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
877 extern void sun4dsmp_flush_tlb_page(struct vm_area_struct *vma,
881 extern void hypersparc_flush_cache_all(void);
882 extern void hypersparc_flush_cache_mm(struct mm_struct *mm);
883 extern void hypersparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
884 extern void hypersparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
885 extern void hypersparc_flush_page_to_ram(unsigned long page);
886 extern void hypersparc_flush_page_for_dma(unsigned long page);
887 extern void hypersparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
888 extern void hypersparc_flush_tlb_all(void);
889 extern void hypersparc_flush_tlb_mm(struct mm_struct *mm);
890 extern void hypersparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
891 extern void hypersparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
892 extern void hypersparc_setup_blockops(void);
895 * NOTE: All of this startup code assumes the low 16mb (approx.) of
896 * kernel mappings are done with one single contiguous chunk of
897 * ram. On small ram machines (classics mainly) we only get
898 * around 8mb mapped for us.
901 static void __init early_pgtable_allocfail(char *type)
903 prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type);
907 static void __init srmmu_early_allocate_ptable_skeleton(unsigned long start,
915 pgdp = pgd_offset_k(start);
916 if (pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
917 pmdp = (pmd_t *) __srmmu_get_nocache(
918 SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
920 early_pgtable_allocfail("pmd");
921 memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
922 pgd_set(__nocache_fix(pgdp), pmdp);
924 pmdp = pmd_offset(__nocache_fix(pgdp), start);
925 if(srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
926 ptep = (pte_t *)__srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
928 early_pgtable_allocfail("pte");
929 memset(__nocache_fix(ptep), 0, PTE_SIZE);
930 pmd_set(__nocache_fix(pmdp), ptep);
932 if (start > (0xffffffffUL - PMD_SIZE))
934 start = (start + PMD_SIZE) & PMD_MASK;
938 static void __init srmmu_allocate_ptable_skeleton(unsigned long start,
946 pgdp = pgd_offset_k(start);
947 if (pgd_none(*pgdp)) {
948 pmdp = (pmd_t *)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
950 early_pgtable_allocfail("pmd");
951 memset(pmdp, 0, SRMMU_PMD_TABLE_SIZE);
954 pmdp = pmd_offset(pgdp, start);
955 if(srmmu_pmd_none(*pmdp)) {
956 ptep = (pte_t *) __srmmu_get_nocache(PTE_SIZE,
959 early_pgtable_allocfail("pte");
960 memset(ptep, 0, PTE_SIZE);
963 if (start > (0xffffffffUL - PMD_SIZE))
965 start = (start + PMD_SIZE) & PMD_MASK;
970 * This is much cleaner than poking around physical address space
971 * looking at the prom's page table directly which is what most
972 * other OS's do. Yuck... this is much better.
974 static void __init srmmu_inherit_prom_mappings(unsigned long start,
980 int what = 0; /* 0 = normal-pte, 1 = pmd-level pte, 2 = pgd-level pte */
981 unsigned long prompte;
983 while(start <= end) {
985 break; /* probably wrap around */
986 if(start == 0xfef00000)
987 start = KADB_DEBUGGER_BEGVM;
988 if(!(prompte = srmmu_hwprobe(start))) {
993 /* A red snapper, see what it really is. */
996 if(!(start & ~(SRMMU_REAL_PMD_MASK))) {
997 if(srmmu_hwprobe((start-PAGE_SIZE) + SRMMU_REAL_PMD_SIZE) == prompte)
1001 if(!(start & ~(SRMMU_PGDIR_MASK))) {
1002 if(srmmu_hwprobe((start-PAGE_SIZE) + SRMMU_PGDIR_SIZE) ==
1007 pgdp = pgd_offset_k(start);
1009 *(pgd_t *)__nocache_fix(pgdp) = __pgd(prompte);
1010 start += SRMMU_PGDIR_SIZE;
1013 if (pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
1014 pmdp = (pmd_t *)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
1016 early_pgtable_allocfail("pmd");
1017 memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
1018 pgd_set(__nocache_fix(pgdp), pmdp);
1020 pmdp = pmd_offset(__nocache_fix(pgdp), start);
1021 if(srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
1022 ptep = (pte_t *) __srmmu_get_nocache(PTE_SIZE,
1025 early_pgtable_allocfail("pte");
1026 memset(__nocache_fix(ptep), 0, PTE_SIZE);
1027 pmd_set(__nocache_fix(pmdp), ptep);
1031 * We bend the rule where all 16 PTPs in a pmd_t point
1032 * inside the same PTE page, and we leak a perfectly
1033 * good hardware PTE piece. Alternatives seem worse.
1035 unsigned int x; /* Index of HW PMD in soft cluster */
1036 x = (start >> PMD_SHIFT) & 15;
1037 *(unsigned long *)__nocache_fix(&pmdp->pmdv[x]) = prompte;
1038 start += SRMMU_REAL_PMD_SIZE;
1041 ptep = pte_offset_kernel(__nocache_fix(pmdp), start);
1042 *(pte_t *)__nocache_fix(ptep) = __pte(prompte);
1047 #define KERNEL_PTE(page_shifted) ((page_shifted)|SRMMU_CACHE|SRMMU_PRIV|SRMMU_VALID)
1049 /* Create a third-level SRMMU 16MB page mapping. */
1050 static void __init do_large_mapping(unsigned long vaddr, unsigned long phys_base)
1052 pgd_t *pgdp = pgd_offset_k(vaddr);
1053 unsigned long big_pte;
1055 big_pte = KERNEL_PTE(phys_base >> 4);
1056 *(pgd_t *)__nocache_fix(pgdp) = __pgd(big_pte);
1059 /* Map sp_bank entry SP_ENTRY, starting at virtual address VBASE. */
1060 static unsigned long __init map_spbank(unsigned long vbase, int sp_entry)
1062 unsigned long pstart = (sp_banks[sp_entry].base_addr & SRMMU_PGDIR_MASK);
1063 unsigned long vstart = (vbase & SRMMU_PGDIR_MASK);
1064 unsigned long vend = SRMMU_PGDIR_ALIGN(vbase + sp_banks[sp_entry].num_bytes);
1065 /* Map "low" memory only */
1066 const unsigned long min_vaddr = PAGE_OFFSET;
1067 const unsigned long max_vaddr = PAGE_OFFSET + SRMMU_MAXMEM;
1069 if (vstart < min_vaddr || vstart >= max_vaddr)
1072 if (vend > max_vaddr || vend < min_vaddr)
1075 while(vstart < vend) {
1076 do_large_mapping(vstart, pstart);
1077 vstart += SRMMU_PGDIR_SIZE; pstart += SRMMU_PGDIR_SIZE;
1082 static inline void memprobe_error(char *msg)
1085 prom_printf("Halting now...\n");
1089 static inline void map_kernel(void)
1093 if (phys_base > 0) {
1094 do_large_mapping(PAGE_OFFSET, phys_base);
1097 for (i = 0; sp_banks[i].num_bytes != 0; i++) {
1098 map_spbank((unsigned long)__va(sp_banks[i].base_addr), i);
1102 /* Paging initialization on the Sparc Reference MMU. */
1103 extern void sparc_context_init(int);
1105 void (*poke_srmmu)(void) __cpuinitdata = NULL;
1107 extern unsigned long bootmem_init(unsigned long *pages_avail);
1109 void __init srmmu_paging_init(void)
1117 unsigned long pages_avail;
1119 sparc_iomap.start = SUN4M_IOBASE_VADDR; /* 16MB of IOSPACE on all sun4m's. */
1121 if (sparc_cpu_model == sun4d)
1122 num_contexts = 65536; /* We know it is Viking */
1124 /* Find the number of contexts on the srmmu. */
1125 cpunode = prom_getchild(prom_root_node);
1127 while(cpunode != 0) {
1128 prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
1129 if(!strcmp(node_str, "cpu")) {
1130 num_contexts = prom_getintdefault(cpunode, "mmu-nctx", 0x8);
1133 cpunode = prom_getsibling(cpunode);
1138 prom_printf("Something wrong, can't find cpu node in paging_init.\n");
1143 last_valid_pfn = bootmem_init(&pages_avail);
1145 srmmu_nocache_calcsize();
1146 srmmu_nocache_init();
1147 srmmu_inherit_prom_mappings(0xfe400000,(LINUX_OPPROM_ENDVM-PAGE_SIZE));
1150 /* ctx table has to be physically aligned to its size */
1151 srmmu_context_table = (ctxd_t *)__srmmu_get_nocache(num_contexts*sizeof(ctxd_t), num_contexts*sizeof(ctxd_t));
1152 srmmu_ctx_table_phys = (ctxd_t *)__nocache_pa((unsigned long)srmmu_context_table);
1154 for(i = 0; i < num_contexts; i++)
1155 srmmu_ctxd_set((ctxd_t *)__nocache_fix(&srmmu_context_table[i]), srmmu_swapper_pg_dir);
1158 srmmu_set_ctable_ptr((unsigned long)srmmu_ctx_table_phys);
1160 /* Stop from hanging here... */
1161 local_flush_tlb_all();
1167 srmmu_allocate_ptable_skeleton(sparc_iomap.start, IOBASE_END);
1168 srmmu_allocate_ptable_skeleton(DVMA_VADDR, DVMA_END);
1170 srmmu_allocate_ptable_skeleton(
1171 __fix_to_virt(__end_of_fixed_addresses - 1), FIXADDR_TOP);
1172 srmmu_allocate_ptable_skeleton(PKMAP_BASE, PKMAP_END);
1174 pgd = pgd_offset_k(PKMAP_BASE);
1175 pmd = pmd_offset(pgd, PKMAP_BASE);
1176 pte = pte_offset_kernel(pmd, PKMAP_BASE);
1177 pkmap_page_table = pte;
1182 sparc_context_init(num_contexts);
1187 unsigned long zones_size[MAX_NR_ZONES];
1188 unsigned long zholes_size[MAX_NR_ZONES];
1189 unsigned long npages;
1192 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1193 zones_size[znum] = zholes_size[znum] = 0;
1195 npages = max_low_pfn - pfn_base;
1197 zones_size[ZONE_DMA] = npages;
1198 zholes_size[ZONE_DMA] = npages - pages_avail;
1200 npages = highend_pfn - max_low_pfn;
1201 zones_size[ZONE_HIGHMEM] = npages;
1202 zholes_size[ZONE_HIGHMEM] = npages - calc_highpages();
1204 free_area_init_node(0, zones_size, pfn_base, zholes_size);
1208 void mmu_info(struct seq_file *m)
1213 "nocache total\t: %ld\n"
1214 "nocache used\t: %d\n",
1218 srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
1221 static void srmmu_update_mmu_cache(struct vm_area_struct * vma, unsigned long address, pte_t pte)
1225 void destroy_context(struct mm_struct *mm)
1228 if(mm->context != NO_CONTEXT) {
1230 srmmu_ctxd_set(&srmmu_context_table[mm->context], srmmu_swapper_pg_dir);
1232 spin_lock(&srmmu_context_spinlock);
1233 free_context(mm->context);
1234 spin_unlock(&srmmu_context_spinlock);
1235 mm->context = NO_CONTEXT;
1239 /* Init various srmmu chip types. */
1240 static void __init srmmu_is_bad(void)
1242 prom_printf("Could not determine SRMMU chip type.\n");
1246 static void __init init_vac_layout(void)
1253 unsigned long max_size = 0;
1254 unsigned long min_line_size = 0x10000000;
1257 nd = prom_getchild(prom_root_node);
1258 while((nd = prom_getsibling(nd)) != 0) {
1259 prom_getstring(nd, "device_type", node_str, sizeof(node_str));
1260 if(!strcmp(node_str, "cpu")) {
1261 vac_line_size = prom_getint(nd, "cache-line-size");
1262 if (vac_line_size == -1) {
1263 prom_printf("can't determine cache-line-size, "
1267 cache_lines = prom_getint(nd, "cache-nlines");
1268 if (cache_lines == -1) {
1269 prom_printf("can't determine cache-nlines, halting.\n");
1273 vac_cache_size = cache_lines * vac_line_size;
1275 if(vac_cache_size > max_size)
1276 max_size = vac_cache_size;
1277 if(vac_line_size < min_line_size)
1278 min_line_size = vac_line_size;
1279 //FIXME: cpus not contiguous!!
1281 if (cpu >= nr_cpu_ids || !cpu_online(cpu))
1289 prom_printf("No CPU nodes found, halting.\n");
1293 vac_cache_size = max_size;
1294 vac_line_size = min_line_size;
1296 printk("SRMMU: Using VAC size of %d bytes, line size %d bytes.\n",
1297 (int)vac_cache_size, (int)vac_line_size);
1300 static void __cpuinit poke_hypersparc(void)
1302 volatile unsigned long clear;
1303 unsigned long mreg = srmmu_get_mmureg();
1305 hyper_flush_unconditional_combined();
1307 mreg &= ~(HYPERSPARC_CWENABLE);
1308 mreg |= (HYPERSPARC_CENABLE | HYPERSPARC_WBENABLE);
1309 mreg |= (HYPERSPARC_CMODE);
1311 srmmu_set_mmureg(mreg);
1313 #if 0 /* XXX I think this is bad news... -DaveM */
1314 hyper_clear_all_tags();
1317 put_ross_icr(HYPERSPARC_ICCR_FTD | HYPERSPARC_ICCR_ICE);
1318 hyper_flush_whole_icache();
1319 clear = srmmu_get_faddr();
1320 clear = srmmu_get_fstatus();
1323 static void __init init_hypersparc(void)
1325 srmmu_name = "ROSS HyperSparc";
1326 srmmu_modtype = HyperSparc;
1332 BTFIXUPSET_CALL(flush_cache_all, hypersparc_flush_cache_all, BTFIXUPCALL_NORM);
1333 BTFIXUPSET_CALL(flush_cache_mm, hypersparc_flush_cache_mm, BTFIXUPCALL_NORM);
1334 BTFIXUPSET_CALL(flush_cache_range, hypersparc_flush_cache_range, BTFIXUPCALL_NORM);
1335 BTFIXUPSET_CALL(flush_cache_page, hypersparc_flush_cache_page, BTFIXUPCALL_NORM);
1337 BTFIXUPSET_CALL(flush_tlb_all, hypersparc_flush_tlb_all, BTFIXUPCALL_NORM);
1338 BTFIXUPSET_CALL(flush_tlb_mm, hypersparc_flush_tlb_mm, BTFIXUPCALL_NORM);
1339 BTFIXUPSET_CALL(flush_tlb_range, hypersparc_flush_tlb_range, BTFIXUPCALL_NORM);
1340 BTFIXUPSET_CALL(flush_tlb_page, hypersparc_flush_tlb_page, BTFIXUPCALL_NORM);
1342 BTFIXUPSET_CALL(__flush_page_to_ram, hypersparc_flush_page_to_ram, BTFIXUPCALL_NORM);
1343 BTFIXUPSET_CALL(flush_sig_insns, hypersparc_flush_sig_insns, BTFIXUPCALL_NORM);
1344 BTFIXUPSET_CALL(flush_page_for_dma, hypersparc_flush_page_for_dma, BTFIXUPCALL_NOP);
1347 poke_srmmu = poke_hypersparc;
1349 hypersparc_setup_blockops();
1352 static void __cpuinit poke_cypress(void)
1354 unsigned long mreg = srmmu_get_mmureg();
1355 unsigned long faddr, tagval;
1356 volatile unsigned long cypress_sucks;
1357 volatile unsigned long clear;
1359 clear = srmmu_get_faddr();
1360 clear = srmmu_get_fstatus();
1362 if (!(mreg & CYPRESS_CENABLE)) {
1363 for(faddr = 0x0; faddr < 0x10000; faddr += 20) {
1364 __asm__ __volatile__("sta %%g0, [%0 + %1] %2\n\t"
1365 "sta %%g0, [%0] %2\n\t" : :
1366 "r" (faddr), "r" (0x40000),
1367 "i" (ASI_M_DATAC_TAG));
1370 for(faddr = 0; faddr < 0x10000; faddr += 0x20) {
1371 __asm__ __volatile__("lda [%1 + %2] %3, %0\n\t" :
1373 "r" (faddr), "r" (0x40000),
1374 "i" (ASI_M_DATAC_TAG));
1376 /* If modified and valid, kick it. */
1377 if((tagval & 0x60) == 0x60)
1378 cypress_sucks = *(unsigned long *)
1379 (0xf0020000 + faddr);
1383 /* And one more, for our good neighbor, Mr. Broken Cypress. */
1384 clear = srmmu_get_faddr();
1385 clear = srmmu_get_fstatus();
1387 mreg |= (CYPRESS_CENABLE | CYPRESS_CMODE);
1388 srmmu_set_mmureg(mreg);
1391 static void __init init_cypress_common(void)
1395 BTFIXUPSET_CALL(flush_cache_all, cypress_flush_cache_all, BTFIXUPCALL_NORM);
1396 BTFIXUPSET_CALL(flush_cache_mm, cypress_flush_cache_mm, BTFIXUPCALL_NORM);
1397 BTFIXUPSET_CALL(flush_cache_range, cypress_flush_cache_range, BTFIXUPCALL_NORM);
1398 BTFIXUPSET_CALL(flush_cache_page, cypress_flush_cache_page, BTFIXUPCALL_NORM);
1400 BTFIXUPSET_CALL(flush_tlb_all, cypress_flush_tlb_all, BTFIXUPCALL_NORM);
1401 BTFIXUPSET_CALL(flush_tlb_mm, cypress_flush_tlb_mm, BTFIXUPCALL_NORM);
1402 BTFIXUPSET_CALL(flush_tlb_page, cypress_flush_tlb_page, BTFIXUPCALL_NORM);
1403 BTFIXUPSET_CALL(flush_tlb_range, cypress_flush_tlb_range, BTFIXUPCALL_NORM);
1406 BTFIXUPSET_CALL(__flush_page_to_ram, cypress_flush_page_to_ram, BTFIXUPCALL_NORM);
1407 BTFIXUPSET_CALL(flush_sig_insns, cypress_flush_sig_insns, BTFIXUPCALL_NOP);
1408 BTFIXUPSET_CALL(flush_page_for_dma, cypress_flush_page_for_dma, BTFIXUPCALL_NOP);
1410 poke_srmmu = poke_cypress;
1413 static void __init init_cypress_604(void)
1415 srmmu_name = "ROSS Cypress-604(UP)";
1416 srmmu_modtype = Cypress;
1417 init_cypress_common();
1420 static void __init init_cypress_605(unsigned long mrev)
1422 srmmu_name = "ROSS Cypress-605(MP)";
1424 srmmu_modtype = Cypress_vE;
1425 hwbug_bitmask |= HWBUG_COPYBACK_BROKEN;
1428 srmmu_modtype = Cypress_vD;
1429 hwbug_bitmask |= HWBUG_ASIFLUSH_BROKEN;
1431 srmmu_modtype = Cypress;
1434 init_cypress_common();
1437 static void __cpuinit poke_swift(void)
1441 /* Clear any crap from the cache or else... */
1442 swift_flush_cache_all();
1444 /* Enable I & D caches */
1445 mreg = srmmu_get_mmureg();
1446 mreg |= (SWIFT_IE | SWIFT_DE);
1448 * The Swift branch folding logic is completely broken. At
1449 * trap time, if things are just right, if can mistakenly
1450 * think that a trap is coming from kernel mode when in fact
1451 * it is coming from user mode (it mis-executes the branch in
1452 * the trap code). So you see things like crashme completely
1453 * hosing your machine which is completely unacceptable. Turn
1454 * this shit off... nice job Fujitsu.
1456 mreg &= ~(SWIFT_BF);
1457 srmmu_set_mmureg(mreg);
1460 #define SWIFT_MASKID_ADDR 0x10003018
1461 static void __init init_swift(void)
1463 unsigned long swift_rev;
1465 __asm__ __volatile__("lda [%1] %2, %0\n\t"
1466 "srl %0, 0x18, %0\n\t" :
1468 "r" (SWIFT_MASKID_ADDR), "i" (ASI_M_BYPASS));
1469 srmmu_name = "Fujitsu Swift";
1475 srmmu_modtype = Swift_lots_o_bugs;
1476 hwbug_bitmask |= (HWBUG_KERN_ACCBROKEN | HWBUG_KERN_CBITBROKEN);
1478 * Gee george, I wonder why Sun is so hush hush about
1479 * this hardware bug... really braindamage stuff going
1480 * on here. However I think we can find a way to avoid
1481 * all of the workaround overhead under Linux. Basically,
1482 * any page fault can cause kernel pages to become user
1483 * accessible (the mmu gets confused and clears some of
1484 * the ACC bits in kernel ptes). Aha, sounds pretty
1485 * horrible eh? But wait, after extensive testing it appears
1486 * that if you use pgd_t level large kernel pte's (like the
1487 * 4MB pages on the Pentium) the bug does not get tripped
1488 * at all. This avoids almost all of the major overhead.
1489 * Welcome to a world where your vendor tells you to,
1490 * "apply this kernel patch" instead of "sorry for the
1491 * broken hardware, send it back and we'll give you
1492 * properly functioning parts"
1497 srmmu_modtype = Swift_bad_c;
1498 hwbug_bitmask |= HWBUG_KERN_CBITBROKEN;
1500 * You see Sun allude to this hardware bug but never
1501 * admit things directly, they'll say things like,
1502 * "the Swift chip cache problems" or similar.
1506 srmmu_modtype = Swift_ok;
1510 BTFIXUPSET_CALL(flush_cache_all, swift_flush_cache_all, BTFIXUPCALL_NORM);
1511 BTFIXUPSET_CALL(flush_cache_mm, swift_flush_cache_mm, BTFIXUPCALL_NORM);
1512 BTFIXUPSET_CALL(flush_cache_page, swift_flush_cache_page, BTFIXUPCALL_NORM);
1513 BTFIXUPSET_CALL(flush_cache_range, swift_flush_cache_range, BTFIXUPCALL_NORM);
1516 BTFIXUPSET_CALL(flush_tlb_all, swift_flush_tlb_all, BTFIXUPCALL_NORM);
1517 BTFIXUPSET_CALL(flush_tlb_mm, swift_flush_tlb_mm, BTFIXUPCALL_NORM);
1518 BTFIXUPSET_CALL(flush_tlb_page, swift_flush_tlb_page, BTFIXUPCALL_NORM);
1519 BTFIXUPSET_CALL(flush_tlb_range, swift_flush_tlb_range, BTFIXUPCALL_NORM);
1521 BTFIXUPSET_CALL(__flush_page_to_ram, swift_flush_page_to_ram, BTFIXUPCALL_NORM);
1522 BTFIXUPSET_CALL(flush_sig_insns, swift_flush_sig_insns, BTFIXUPCALL_NORM);
1523 BTFIXUPSET_CALL(flush_page_for_dma, swift_flush_page_for_dma, BTFIXUPCALL_NORM);
1525 BTFIXUPSET_CALL(update_mmu_cache, swift_update_mmu_cache, BTFIXUPCALL_NORM);
1527 flush_page_for_dma_global = 0;
1530 * Are you now convinced that the Swift is one of the
1531 * biggest VLSI abortions of all time? Bravo Fujitsu!
1532 * Fujitsu, the !#?!%$'d up processor people. I bet if
1533 * you examined the microcode of the Swift you'd find
1534 * XXX's all over the place.
1536 poke_srmmu = poke_swift;
1539 static void turbosparc_flush_cache_all(void)
1541 flush_user_windows();
1542 turbosparc_idflash_clear();
1545 static void turbosparc_flush_cache_mm(struct mm_struct *mm)
1548 flush_user_windows();
1549 turbosparc_idflash_clear();
1553 static void turbosparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1555 FLUSH_BEGIN(vma->vm_mm)
1556 flush_user_windows();
1557 turbosparc_idflash_clear();
1561 static void turbosparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
1563 FLUSH_BEGIN(vma->vm_mm)
1564 flush_user_windows();
1565 if (vma->vm_flags & VM_EXEC)
1566 turbosparc_flush_icache();
1567 turbosparc_flush_dcache();
1571 /* TurboSparc is copy-back, if we turn it on, but this does not work. */
1572 static void turbosparc_flush_page_to_ram(unsigned long page)
1574 #ifdef TURBOSPARC_WRITEBACK
1575 volatile unsigned long clear;
1577 if (srmmu_hwprobe(page))
1578 turbosparc_flush_page_cache(page);
1579 clear = srmmu_get_fstatus();
1583 static void turbosparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
1587 static void turbosparc_flush_page_for_dma(unsigned long page)
1589 turbosparc_flush_dcache();
1592 static void turbosparc_flush_tlb_all(void)
1594 srmmu_flush_whole_tlb();
1597 static void turbosparc_flush_tlb_mm(struct mm_struct *mm)
1600 srmmu_flush_whole_tlb();
1604 static void turbosparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1606 FLUSH_BEGIN(vma->vm_mm)
1607 srmmu_flush_whole_tlb();
1611 static void turbosparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
1613 FLUSH_BEGIN(vma->vm_mm)
1614 srmmu_flush_whole_tlb();
1619 static void __cpuinit poke_turbosparc(void)
1621 unsigned long mreg = srmmu_get_mmureg();
1622 unsigned long ccreg;
1624 /* Clear any crap from the cache or else... */
1625 turbosparc_flush_cache_all();
1626 mreg &= ~(TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* Temporarily disable I & D caches */
1627 mreg &= ~(TURBOSPARC_PCENABLE); /* Don't check parity */
1628 srmmu_set_mmureg(mreg);
1630 ccreg = turbosparc_get_ccreg();
1632 #ifdef TURBOSPARC_WRITEBACK
1633 ccreg |= (TURBOSPARC_SNENABLE); /* Do DVMA snooping in Dcache */
1634 ccreg &= ~(TURBOSPARC_uS2 | TURBOSPARC_WTENABLE);
1635 /* Write-back D-cache, emulate VLSI
1636 * abortion number three, not number one */
1638 /* For now let's play safe, optimize later */
1639 ccreg |= (TURBOSPARC_SNENABLE | TURBOSPARC_WTENABLE);
1640 /* Do DVMA snooping in Dcache, Write-thru D-cache */
1641 ccreg &= ~(TURBOSPARC_uS2);
1642 /* Emulate VLSI abortion number three, not number one */
1645 switch (ccreg & 7) {
1646 case 0: /* No SE cache */
1647 case 7: /* Test mode */
1650 ccreg |= (TURBOSPARC_SCENABLE);
1652 turbosparc_set_ccreg (ccreg);
1654 mreg |= (TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* I & D caches on */
1655 mreg |= (TURBOSPARC_ICSNOOP); /* Icache snooping on */
1656 srmmu_set_mmureg(mreg);
1659 static void __init init_turbosparc(void)
1661 srmmu_name = "Fujitsu TurboSparc";
1662 srmmu_modtype = TurboSparc;
1664 BTFIXUPSET_CALL(flush_cache_all, turbosparc_flush_cache_all, BTFIXUPCALL_NORM);
1665 BTFIXUPSET_CALL(flush_cache_mm, turbosparc_flush_cache_mm, BTFIXUPCALL_NORM);
1666 BTFIXUPSET_CALL(flush_cache_page, turbosparc_flush_cache_page, BTFIXUPCALL_NORM);
1667 BTFIXUPSET_CALL(flush_cache_range, turbosparc_flush_cache_range, BTFIXUPCALL_NORM);
1669 BTFIXUPSET_CALL(flush_tlb_all, turbosparc_flush_tlb_all, BTFIXUPCALL_NORM);
1670 BTFIXUPSET_CALL(flush_tlb_mm, turbosparc_flush_tlb_mm, BTFIXUPCALL_NORM);
1671 BTFIXUPSET_CALL(flush_tlb_page, turbosparc_flush_tlb_page, BTFIXUPCALL_NORM);
1672 BTFIXUPSET_CALL(flush_tlb_range, turbosparc_flush_tlb_range, BTFIXUPCALL_NORM);
1674 BTFIXUPSET_CALL(__flush_page_to_ram, turbosparc_flush_page_to_ram, BTFIXUPCALL_NORM);
1676 BTFIXUPSET_CALL(flush_sig_insns, turbosparc_flush_sig_insns, BTFIXUPCALL_NOP);
1677 BTFIXUPSET_CALL(flush_page_for_dma, turbosparc_flush_page_for_dma, BTFIXUPCALL_NORM);
1679 poke_srmmu = poke_turbosparc;
1682 static void __cpuinit poke_tsunami(void)
1684 unsigned long mreg = srmmu_get_mmureg();
1686 tsunami_flush_icache();
1687 tsunami_flush_dcache();
1688 mreg &= ~TSUNAMI_ITD;
1689 mreg |= (TSUNAMI_IENAB | TSUNAMI_DENAB);
1690 srmmu_set_mmureg(mreg);
1693 static void __init init_tsunami(void)
1696 * Tsunami's pretty sane, Sun and TI actually got it
1697 * somewhat right this time. Fujitsu should have
1698 * taken some lessons from them.
1701 srmmu_name = "TI Tsunami";
1702 srmmu_modtype = Tsunami;
1704 BTFIXUPSET_CALL(flush_cache_all, tsunami_flush_cache_all, BTFIXUPCALL_NORM);
1705 BTFIXUPSET_CALL(flush_cache_mm, tsunami_flush_cache_mm, BTFIXUPCALL_NORM);
1706 BTFIXUPSET_CALL(flush_cache_page, tsunami_flush_cache_page, BTFIXUPCALL_NORM);
1707 BTFIXUPSET_CALL(flush_cache_range, tsunami_flush_cache_range, BTFIXUPCALL_NORM);
1710 BTFIXUPSET_CALL(flush_tlb_all, tsunami_flush_tlb_all, BTFIXUPCALL_NORM);
1711 BTFIXUPSET_CALL(flush_tlb_mm, tsunami_flush_tlb_mm, BTFIXUPCALL_NORM);
1712 BTFIXUPSET_CALL(flush_tlb_page, tsunami_flush_tlb_page, BTFIXUPCALL_NORM);
1713 BTFIXUPSET_CALL(flush_tlb_range, tsunami_flush_tlb_range, BTFIXUPCALL_NORM);
1715 BTFIXUPSET_CALL(__flush_page_to_ram, tsunami_flush_page_to_ram, BTFIXUPCALL_NOP);
1716 BTFIXUPSET_CALL(flush_sig_insns, tsunami_flush_sig_insns, BTFIXUPCALL_NORM);
1717 BTFIXUPSET_CALL(flush_page_for_dma, tsunami_flush_page_for_dma, BTFIXUPCALL_NORM);
1719 poke_srmmu = poke_tsunami;
1721 tsunami_setup_blockops();
1724 static void __cpuinit poke_viking(void)
1726 unsigned long mreg = srmmu_get_mmureg();
1727 static int smp_catch;
1729 if(viking_mxcc_present) {
1730 unsigned long mxcc_control = mxcc_get_creg();
1732 mxcc_control |= (MXCC_CTL_ECE | MXCC_CTL_PRE | MXCC_CTL_MCE);
1733 mxcc_control &= ~(MXCC_CTL_RRC);
1734 mxcc_set_creg(mxcc_control);
1737 * We don't need memory parity checks.
1738 * XXX This is a mess, have to dig out later. ecd.
1739 viking_mxcc_turn_off_parity(&mreg, &mxcc_control);
1742 /* We do cache ptables on MXCC. */
1743 mreg |= VIKING_TCENABLE;
1745 unsigned long bpreg;
1747 mreg &= ~(VIKING_TCENABLE);
1749 /* Must disable mixed-cmd mode here for other cpu's. */
1750 bpreg = viking_get_bpreg();
1751 bpreg &= ~(VIKING_ACTION_MIX);
1752 viking_set_bpreg(bpreg);
1754 /* Just in case PROM does something funny. */
1759 mreg |= VIKING_SPENABLE;
1760 mreg |= (VIKING_ICENABLE | VIKING_DCENABLE);
1761 mreg |= VIKING_SBENABLE;
1762 mreg &= ~(VIKING_ACENABLE);
1763 srmmu_set_mmureg(mreg);
1766 static void __init init_viking(void)
1768 unsigned long mreg = srmmu_get_mmureg();
1770 /* Ahhh, the viking. SRMMU VLSI abortion number two... */
1771 if(mreg & VIKING_MMODE) {
1772 srmmu_name = "TI Viking";
1773 viking_mxcc_present = 0;
1777 * We need this to make sure old viking takes no hits
1778 * on it's cache for dma snoops to workaround the
1779 * "load from non-cacheable memory" interrupt bug.
1780 * This is only necessary because of the new way in
1781 * which we use the IOMMU.
1783 BTFIXUPSET_CALL(flush_page_for_dma, viking_flush_page, BTFIXUPCALL_NORM);
1785 flush_page_for_dma_global = 0;
1787 srmmu_name = "TI Viking/MXCC";
1788 viking_mxcc_present = 1;
1790 srmmu_cache_pagetables = 1;
1792 /* MXCC vikings lack the DMA snooping bug. */
1793 BTFIXUPSET_CALL(flush_page_for_dma, viking_flush_page_for_dma, BTFIXUPCALL_NOP);
1796 BTFIXUPSET_CALL(flush_cache_all, viking_flush_cache_all, BTFIXUPCALL_NORM);
1797 BTFIXUPSET_CALL(flush_cache_mm, viking_flush_cache_mm, BTFIXUPCALL_NORM);
1798 BTFIXUPSET_CALL(flush_cache_page, viking_flush_cache_page, BTFIXUPCALL_NORM);
1799 BTFIXUPSET_CALL(flush_cache_range, viking_flush_cache_range, BTFIXUPCALL_NORM);
1802 if (sparc_cpu_model == sun4d) {
1803 BTFIXUPSET_CALL(flush_tlb_all, sun4dsmp_flush_tlb_all, BTFIXUPCALL_NORM);
1804 BTFIXUPSET_CALL(flush_tlb_mm, sun4dsmp_flush_tlb_mm, BTFIXUPCALL_NORM);
1805 BTFIXUPSET_CALL(flush_tlb_page, sun4dsmp_flush_tlb_page, BTFIXUPCALL_NORM);
1806 BTFIXUPSET_CALL(flush_tlb_range, sun4dsmp_flush_tlb_range, BTFIXUPCALL_NORM);
1810 BTFIXUPSET_CALL(flush_tlb_all, viking_flush_tlb_all, BTFIXUPCALL_NORM);
1811 BTFIXUPSET_CALL(flush_tlb_mm, viking_flush_tlb_mm, BTFIXUPCALL_NORM);
1812 BTFIXUPSET_CALL(flush_tlb_page, viking_flush_tlb_page, BTFIXUPCALL_NORM);
1813 BTFIXUPSET_CALL(flush_tlb_range, viking_flush_tlb_range, BTFIXUPCALL_NORM);
1816 BTFIXUPSET_CALL(__flush_page_to_ram, viking_flush_page_to_ram, BTFIXUPCALL_NOP);
1817 BTFIXUPSET_CALL(flush_sig_insns, viking_flush_sig_insns, BTFIXUPCALL_NOP);
1819 poke_srmmu = poke_viking;
1822 #ifdef CONFIG_SPARC_LEON
1824 void __init poke_leonsparc(void)
1828 void __init init_leon(void)
1831 srmmu_name = "LEON";
1833 BTFIXUPSET_CALL(flush_cache_all, leon_flush_cache_all,
1835 BTFIXUPSET_CALL(flush_cache_mm, leon_flush_cache_all,
1837 BTFIXUPSET_CALL(flush_cache_page, leon_flush_pcache_all,
1839 BTFIXUPSET_CALL(flush_cache_range, leon_flush_cache_all,
1841 BTFIXUPSET_CALL(flush_page_for_dma, leon_flush_dcache_all,
1844 BTFIXUPSET_CALL(flush_tlb_all, leon_flush_tlb_all, BTFIXUPCALL_NORM);
1845 BTFIXUPSET_CALL(flush_tlb_mm, leon_flush_tlb_all, BTFIXUPCALL_NORM);
1846 BTFIXUPSET_CALL(flush_tlb_page, leon_flush_tlb_all, BTFIXUPCALL_NORM);
1847 BTFIXUPSET_CALL(flush_tlb_range, leon_flush_tlb_all, BTFIXUPCALL_NORM);
1849 BTFIXUPSET_CALL(__flush_page_to_ram, leon_flush_cache_all,
1851 BTFIXUPSET_CALL(flush_sig_insns, leon_flush_cache_all, BTFIXUPCALL_NOP);
1853 poke_srmmu = poke_leonsparc;
1855 srmmu_cache_pagetables = 0;
1857 leon_flush_during_switch = leon_flush_needed();
1861 /* Probe for the srmmu chip version. */
1862 static void __init get_srmmu_type(void)
1864 unsigned long mreg, psr;
1865 unsigned long mod_typ, mod_rev, psr_typ, psr_vers;
1867 srmmu_modtype = SRMMU_INVAL_MOD;
1870 mreg = srmmu_get_mmureg(); psr = get_psr();
1871 mod_typ = (mreg & 0xf0000000) >> 28;
1872 mod_rev = (mreg & 0x0f000000) >> 24;
1873 psr_typ = (psr >> 28) & 0xf;
1874 psr_vers = (psr >> 24) & 0xf;
1876 /* First, check for sparc-leon. */
1877 if (sparc_cpu_model == sparc_leon) {
1882 /* Second, check for HyperSparc or Cypress. */
1886 /* UP or MP Hypersparc */
1891 /* Uniprocessor Cypress */
1897 /* _REALLY OLD_ Cypress MP chips... */
1901 /* MP Cypress mmu/cache-controller */
1902 init_cypress_605(mod_rev);
1905 /* Some other Cypress revision, assume a 605. */
1906 init_cypress_605(mod_rev);
1913 * Now Fujitsu TurboSparc. It might happen that it is
1914 * in Swift emulation mode, so we will check later...
1916 if (psr_typ == 0 && psr_vers == 5) {
1921 /* Next check for Fujitsu Swift. */
1922 if(psr_typ == 0 && psr_vers == 4) {
1926 /* Look if it is not a TurboSparc emulating Swift... */
1927 cpunode = prom_getchild(prom_root_node);
1928 while((cpunode = prom_getsibling(cpunode)) != 0) {
1929 prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
1930 if(!strcmp(node_str, "cpu")) {
1931 if (!prom_getintdefault(cpunode, "psr-implementation", 1) &&
1932 prom_getintdefault(cpunode, "psr-version", 1) == 5) {
1944 /* Now the Viking family of srmmu. */
1947 ((psr_vers == 1) && (mod_typ == 0) && (mod_rev == 0)))) {
1952 /* Finally the Tsunami. */
1953 if(psr_typ == 4 && psr_vers == 1 && (mod_typ || mod_rev)) {
1962 extern unsigned long spwin_mmu_patchme, fwin_mmu_patchme,
1963 tsetup_mmu_patchme, rtrap_mmu_patchme;
1965 extern unsigned long spwin_srmmu_stackchk, srmmu_fwin_stackchk,
1966 tsetup_srmmu_stackchk, srmmu_rett_stackchk;
1969 /* Local cross-calls. */
1970 static void smp_flush_page_for_dma(unsigned long page)
1972 xc1((smpfunc_t) BTFIXUP_CALL(local_flush_page_for_dma), page);
1973 local_flush_page_for_dma(page);
1978 /* Load up routines and constants for sun4m and sun4d mmu */
1979 void __init load_mmu(void)
1981 extern void ld_mmu_iommu(void);
1982 extern void ld_mmu_iounit(void);
1985 BTFIXUPSET_CALL(update_mmu_cache, srmmu_update_mmu_cache, BTFIXUPCALL_NOP);
1990 /* El switcheroo... */
1992 BTFIXUPCOPY_CALL(local_flush_cache_all, flush_cache_all);
1993 BTFIXUPCOPY_CALL(local_flush_cache_mm, flush_cache_mm);
1994 BTFIXUPCOPY_CALL(local_flush_cache_range, flush_cache_range);
1995 BTFIXUPCOPY_CALL(local_flush_cache_page, flush_cache_page);
1996 BTFIXUPCOPY_CALL(local_flush_tlb_all, flush_tlb_all);
1997 BTFIXUPCOPY_CALL(local_flush_tlb_mm, flush_tlb_mm);
1998 BTFIXUPCOPY_CALL(local_flush_tlb_range, flush_tlb_range);
1999 BTFIXUPCOPY_CALL(local_flush_tlb_page, flush_tlb_page);
2000 BTFIXUPCOPY_CALL(local_flush_page_to_ram, __flush_page_to_ram);
2001 BTFIXUPCOPY_CALL(local_flush_sig_insns, flush_sig_insns);
2002 BTFIXUPCOPY_CALL(local_flush_page_for_dma, flush_page_for_dma);
2004 BTFIXUPSET_CALL(flush_cache_all, smp_flush_cache_all, BTFIXUPCALL_NORM);
2005 BTFIXUPSET_CALL(flush_cache_mm, smp_flush_cache_mm, BTFIXUPCALL_NORM);
2006 BTFIXUPSET_CALL(flush_cache_range, smp_flush_cache_range, BTFIXUPCALL_NORM);
2007 BTFIXUPSET_CALL(flush_cache_page, smp_flush_cache_page, BTFIXUPCALL_NORM);
2008 if (sparc_cpu_model != sun4d &&
2009 sparc_cpu_model != sparc_leon) {
2010 BTFIXUPSET_CALL(flush_tlb_all, smp_flush_tlb_all, BTFIXUPCALL_NORM);
2011 BTFIXUPSET_CALL(flush_tlb_mm, smp_flush_tlb_mm, BTFIXUPCALL_NORM);
2012 BTFIXUPSET_CALL(flush_tlb_range, smp_flush_tlb_range, BTFIXUPCALL_NORM);
2013 BTFIXUPSET_CALL(flush_tlb_page, smp_flush_tlb_page, BTFIXUPCALL_NORM);
2015 BTFIXUPSET_CALL(__flush_page_to_ram, smp_flush_page_to_ram, BTFIXUPCALL_NORM);
2016 BTFIXUPSET_CALL(flush_sig_insns, smp_flush_sig_insns, BTFIXUPCALL_NORM);
2017 BTFIXUPSET_CALL(flush_page_for_dma, smp_flush_page_for_dma, BTFIXUPCALL_NORM);
2019 if (poke_srmmu == poke_viking) {
2020 /* Avoid unnecessary cross calls. */
2021 BTFIXUPCOPY_CALL(flush_cache_all, local_flush_cache_all);
2022 BTFIXUPCOPY_CALL(flush_cache_mm, local_flush_cache_mm);
2023 BTFIXUPCOPY_CALL(flush_cache_range, local_flush_cache_range);
2024 BTFIXUPCOPY_CALL(flush_cache_page, local_flush_cache_page);
2025 BTFIXUPCOPY_CALL(__flush_page_to_ram, local_flush_page_to_ram);
2026 BTFIXUPCOPY_CALL(flush_sig_insns, local_flush_sig_insns);
2027 BTFIXUPCOPY_CALL(flush_page_for_dma, local_flush_page_for_dma);
2031 if (sparc_cpu_model == sun4d)
2036 if (sparc_cpu_model == sun4d)
2038 else if (sparc_cpu_model == sparc_leon)