arch/sparc/mm/init_64.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *  arch/sparc64/mm/init.c
   4  *
   5  *  Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
   6  *  Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   7  */
   8
   9 #include <linux/extable.h>
  10 #include <linux/kernel.h>
  11 #include <linux/sched.h>
  12 #include <linux/string.h>
  13 #include <linux/init.h>
  14 #include <linux/memblock.h>
  15 #include <linux/mm.h>
  16 #include <linux/hugetlb.h>
  17 #include <linux/initrd.h>
  18 #include <linux/swap.h>
  19 #include <linux/pagemap.h>
  20 #include <linux/poison.h>
  21 #include <linux/fs.h>
  22 #include <linux/seq_file.h>
  23 #include <linux/kprobes.h>
  24 #include <linux/cache.h>
  25 #include <linux/sort.h>
  26 #include <linux/ioport.h>
  27 #include <linux/percpu.h>
  28 #include <linux/mmzone.h>
  29 #include <linux/gfp.h>
  30
  31 #include <asm/head.h>
  32 #include <asm/page.h>
  33 #include <asm/pgalloc.h>
  34 #include <asm/oplib.h>
  35 #include <asm/iommu.h>
  36 #include <asm/io.h>
  37 #include <linux/uaccess.h>
  38 #include <asm/mmu_context.h>
  39 #include <asm/tlbflush.h>
  40 #include <asm/dma.h>
  41 #include <asm/starfire.h>
  42 #include <asm/tlb.h>
  43 #include <asm/spitfire.h>
  44 #include <asm/sections.h>
  45 #include <asm/tsb.h>
  46 #include <asm/hypervisor.h>
  47 #include <asm/prom.h>
  48 #include <asm/mdesc.h>
  49 #include <asm/cpudata.h>
  50 #include <asm/setup.h>
  51 #include <asm/irq.h>
  52
  53 #include "init_64.h"
  54
  55 unsigned long kern_linear_pte_xor[4] __read_mostly;
  56 static unsigned long page_cache4v_flag;
  57
  58 /* A bitmap, two bits for every 256MB of physical memory.  These two
  59  * bits determine what page size we use for kernel linear
  60  * translations.  They form an index into kern_linear_pte_xor[].  The
  61  * value in the indexed slot is XOR'd with the TLB miss virtual
  62  * address to form the resulting TTE.  The mapping is:
  63  *
  64  *      0       ==>     4MB
  65  *      1       ==>     256MB
  66  *      2       ==>     2GB
  67  *      3       ==>     16GB
  68  *
  69  * All sun4v chips support 256MB pages.  Only SPARC-T4 and later
  70  * support 2GB pages, and hopefully future cpus will support the 16GB
  71  * pages as well.  For slots 2 and 3, we encode a 256MB TTE xor there
  72  * if these larger page sizes are not supported by the cpu.
  73  *
  74  * It would be nice to determine this from the machine description
  75  * 'cpu' properties, but we need to have this table setup before the
  76  * MDESC is initialized.
  77  */
  78
  79 #ifndef CONFIG_DEBUG_PAGEALLOC
  80 /* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings.
  81  * Space is allocated for this right after the trap table in
  82  * arch/sparc64/kernel/head.S
  83  */
  84 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
  85 #endif
  86 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
  87
  88 static unsigned long cpu_pgsz_mask;
  89
  90 #define MAX_BANKS       1024
  91
  92 static struct linux_prom64_registers pavail[MAX_BANKS];
  93 static int pavail_ents;
  94
  95 u64 numa_latency[MAX_NUMNODES][MAX_NUMNODES];
  96
  97 static int cmp_p64(const void *a, const void *b)
  98 {
  99         const struct linux_prom64_registers *x = a, *y = b;
 100
 101         if (x->phys_addr > y->phys_addr)
 102                 return 1;
 103         if (x->phys_addr < y->phys_addr)
 104                 return -1;
 105         return 0;
 106 }
 107
 108 static void __init read_obp_memory(const char *property,
 109                                    struct linux_prom64_registers *regs,
 110                                    int *num_ents)
 111 {
 112         phandle node = prom_finddevice("/memory");
 113         int prop_size = prom_getproplen(node, property);
 114         int ents, ret, i;
 115
 116         ents = prop_size / sizeof(struct linux_prom64_registers);
 117         if (ents > MAX_BANKS) {
 118                 prom_printf("The machine has more %s property entries than "
 119                             "this kernel can support (%d).\n",
 120                             property, MAX_BANKS);
 121                 prom_halt();
 122         }
 123
 124         ret = prom_getproperty(node, property, (char *) regs, prop_size);
 125         if (ret == -1) {
 126                 prom_printf("Couldn't get %s property from /memory.\n",
 127                                 property);
 128                 prom_halt();
 129         }
 130
 131         /* Sanitize what we got from the firmware, by page aligning
 132          * everything.
 133          */
 134         for (i = 0; i < ents; i++) {
 135                 unsigned long base, size;
 136
 137                 base = regs[i].phys_addr;
 138                 size = regs[i].reg_size;
 139
 140                 size &= PAGE_MASK;
 141                 if (base & ~PAGE_MASK) {
 142                         unsigned long new_base = PAGE_ALIGN(base);
 143
 144                         size -= new_base - base;
 145                         if ((long) size < 0L)
 146                                 size = 0UL;
 147                         base = new_base;
 148                 }
 149                 if (size == 0UL) {
 150                         /* If it is empty, simply get rid of it.
 151                          * This simplifies the logic of the other
 152                          * functions that process these arrays.
 153                          */
 154                         memmove(&regs[i], &regs[i + 1],
 155                                 (ents - i - 1) * sizeof(regs[0]));
 156                         i--;
 157                         ents--;
 158                         continue;
 159                 }
 160                 regs[i].phys_addr = base;
 161                 regs[i].reg_size = size;
 162         }
 163
 164         *num_ents = ents;
 165
 166         sort(regs, ents, sizeof(struct linux_prom64_registers),
 167              cmp_p64, NULL);
 168 }
 169
 170 /* Kernel physical address base and size in bytes.  */
 171 unsigned long kern_base __read_mostly;
 172 unsigned long kern_size __read_mostly;
 173
 174 /* Initial ramdisk setup */
 175 extern unsigned long sparc_ramdisk_image64;
 176 extern unsigned int sparc_ramdisk_image;
 177 extern unsigned int sparc_ramdisk_size;
 178
 179 struct page *mem_map_zero __read_mostly;
 180 EXPORT_SYMBOL(mem_map_zero);
 181
 182 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
 183
 184 unsigned long sparc64_kern_pri_context __read_mostly;
 185 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
 186 unsigned long sparc64_kern_sec_context __read_mostly;
 187
 188 int num_kernel_image_mappings;
 189
 190 #ifdef CONFIG_DEBUG_DCFLUSH
 191 atomic_t dcpage_flushes = ATOMIC_INIT(0);
 192 #ifdef CONFIG_SMP
 193 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
 194 #endif
 195 #endif
 196
 197 inline void flush_dcache_page_impl(struct page *page)
 198 {
 199         BUG_ON(tlb_type == hypervisor);
 200 #ifdef CONFIG_DEBUG_DCFLUSH
 201         atomic_inc(&dcpage_flushes);
 202 #endif
 203
 204 #ifdef DCACHE_ALIASING_POSSIBLE
 205         __flush_dcache_page(page_address(page),
 206                             ((tlb_type == spitfire) &&
 207                              page_mapping_file(page) != NULL));
 208 #else
 209         if (page_mapping_file(page) != NULL &&
 210             tlb_type == spitfire)
 211                 __flush_icache_page(__pa(page_address(page)));
 212 #endif
 213 }
 214
 215 #define PG_dcache_dirty         PG_arch_1
 216 #define PG_dcache_cpu_shift     32UL
 217 #define PG_dcache_cpu_mask      \
 218         ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
 219
 220 #define dcache_dirty_cpu(page) \
 221         (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
 222
 223 static inline void set_dcache_dirty(struct page *page, int this_cpu)
 224 {
 225         unsigned long mask = this_cpu;
 226         unsigned long non_cpu_bits;
 227
 228         non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
 229         mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
 230
 231         __asm__ __volatile__("1:\n\t"
 232                              "ldx       [%2], %%g7\n\t"
 233                              "and       %%g7, %1, %%g1\n\t"
 234                              "or        %%g1, %0, %%g1\n\t"
 235                              "casx      [%2], %%g7, %%g1\n\t"
 236                              "cmp       %%g7, %%g1\n\t"
 237                              "bne,pn    %%xcc, 1b\n\t"
 238                              " nop"
 239                              : /* no outputs */
 240                              : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
 241                              : "g1", "g7");
 242 }
 243
 244 static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
 245 {
 246         unsigned long mask = (1UL << PG_dcache_dirty);
 247
 248         __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
 249                              "1:\n\t"
 250                              "ldx       [%2], %%g7\n\t"
 251                              "srlx      %%g7, %4, %%g1\n\t"
 252                              "and       %%g1, %3, %%g1\n\t"
 253                              "cmp       %%g1, %0\n\t"
 254                              "bne,pn    %%icc, 2f\n\t"
 255                              " andn     %%g7, %1, %%g1\n\t"
 256                              "casx      [%2], %%g7, %%g1\n\t"
 257                              "cmp       %%g7, %%g1\n\t"
 258                              "bne,pn    %%xcc, 1b\n\t"
 259                              " nop\n"
 260                              "2:"
 261                              : /* no outputs */
 262                              : "r" (cpu), "r" (mask), "r" (&page->flags),
 263                                "i" (PG_dcache_cpu_mask),
 264                                "i" (PG_dcache_cpu_shift)
 265                              : "g1", "g7");
 266 }
 267
 268 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
 269 {
 270         unsigned long tsb_addr = (unsigned long) ent;
 271
 272         if (tlb_type == cheetah_plus || tlb_type == hypervisor)
 273                 tsb_addr = __pa(tsb_addr);
 274
 275         __tsb_insert(tsb_addr, tag, pte);
 276 }
 277
 278 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
 279
 280 static void flush_dcache(unsigned long pfn)
 281 {
 282         struct page *page;
 283
 284         page = pfn_to_page(pfn);
 285         if (page) {
 286                 unsigned long pg_flags;
 287
 288                 pg_flags = page->flags;
 289                 if (pg_flags & (1UL << PG_dcache_dirty)) {
 290                         int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
 291                                    PG_dcache_cpu_mask);
 292                         int this_cpu = get_cpu();
 293
 294                         /* This is just to optimize away some function calls
 295                          * in the SMP case.
 296                          */
 297                         if (cpu == this_cpu)
 298                                 flush_dcache_page_impl(page);
 299                         else
 300                                 smp_flush_dcache_page_impl(page, cpu);
 301
 302                         clear_dcache_dirty_cpu(page, cpu);
 303
 304                         put_cpu();
 305                 }
 306         }
 307 }
 308
 309 /* mm->context.lock must be held */
 310 static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_index,
 311                                     unsigned long tsb_hash_shift, unsigned long address,
 312                                     unsigned long tte)
 313 {
 314         struct tsb *tsb = mm->context.tsb_block[tsb_index].tsb;
 315         unsigned long tag;
 316
 317         if (unlikely(!tsb))
 318                 return;
 319
 320         tsb += ((address >> tsb_hash_shift) &
 321                 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
 322         tag = (address >> 22UL);
 323         tsb_insert(tsb, tag, tte);
 324 }
 325
 326 #ifdef CONFIG_HUGETLB_PAGE
 327 static int __init hugetlbpage_init(void)
 328 {
 329         hugetlb_add_hstate(HPAGE_64K_SHIFT - PAGE_SHIFT);
 330         hugetlb_add_hstate(HPAGE_SHIFT - PAGE_SHIFT);
 331         hugetlb_add_hstate(HPAGE_256MB_SHIFT - PAGE_SHIFT);
 332         hugetlb_add_hstate(HPAGE_2GB_SHIFT - PAGE_SHIFT);
 333
 334         return 0;
 335 }
 336
 337 arch_initcall(hugetlbpage_init);
 338
 339 static void __init pud_huge_patch(void)
 340 {
 341         struct pud_huge_patch_entry *p;
 342         unsigned long addr;
 343
 344         p = &__pud_huge_patch;
 345         addr = p->addr;
 346         *(unsigned int *)addr = p->insn;
 347
 348         __asm__ __volatile__("flush %0" : : "r" (addr));
 349 }
 350
 351 bool __init arch_hugetlb_valid_size(unsigned long size)
 352 {
 353         unsigned int hugepage_shift = ilog2(size);
 354         unsigned short hv_pgsz_idx;
 355         unsigned int hv_pgsz_mask;
 356
 357         switch (hugepage_shift) {
 358         case HPAGE_16GB_SHIFT:
 359                 hv_pgsz_mask = HV_PGSZ_MASK_16GB;
 360                 hv_pgsz_idx = HV_PGSZ_IDX_16GB;
 361                 pud_huge_patch();
 362                 break;
 363         case HPAGE_2GB_SHIFT:
 364                 hv_pgsz_mask = HV_PGSZ_MASK_2GB;
 365                 hv_pgsz_idx = HV_PGSZ_IDX_2GB;
 366                 break;
 367         case HPAGE_256MB_SHIFT:
 368                 hv_pgsz_mask = HV_PGSZ_MASK_256MB;
 369                 hv_pgsz_idx = HV_PGSZ_IDX_256MB;
 370                 break;
 371         case HPAGE_SHIFT:
 372                 hv_pgsz_mask = HV_PGSZ_MASK_4MB;
 373                 hv_pgsz_idx = HV_PGSZ_IDX_4MB;
 374                 break;
 375         case HPAGE_64K_SHIFT:
 376                 hv_pgsz_mask = HV_PGSZ_MASK_64K;
 377                 hv_pgsz_idx = HV_PGSZ_IDX_64K;
 378                 break;
 379         default:
 380                 hv_pgsz_mask = 0;
 381         }
 382
 383         if ((hv_pgsz_mask & cpu_pgsz_mask) == 0U)
 384                 return false;
 385
 386         return true;
 387 }
 388 #endif  /* CONFIG_HUGETLB_PAGE */
 389
 390 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
 391 {
 392         struct mm_struct *mm;
 393         unsigned long flags;
 394         bool is_huge_tsb;
 395         pte_t pte = *ptep;
 396
 397         if (tlb_type != hypervisor) {
 398                 unsigned long pfn = pte_pfn(pte);
 399
 400                 if (pfn_valid(pfn))
 401                         flush_dcache(pfn);
 402         }
 403
 404         mm = vma->vm_mm;
 405
 406         /* Don't insert a non-valid PTE into the TSB, we'll deadlock.  */
 407         if (!pte_accessible(mm, pte))
 408                 return;
 409
 410         spin_lock_irqsave(&mm->context.lock, flags);
 411
 412         is_huge_tsb = false;
 413 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
 414         if (mm->context.hugetlb_pte_count || mm->context.thp_pte_count) {
 415                 unsigned long hugepage_size = PAGE_SIZE;
 416
 417                 if (is_vm_hugetlb_page(vma))
 418                         hugepage_size = huge_page_size(hstate_vma(vma));
 419
 420                 if (hugepage_size >= PUD_SIZE) {
 421                         unsigned long mask = 0x1ffc00000UL;
 422
 423                         /* Transfer bits [32:22] from address to resolve
 424                          * at 4M granularity.
 425                          */
 426                         pte_val(pte) &= ~mask;
 427                         pte_val(pte) |= (address & mask);
 428                 } else if (hugepage_size >= PMD_SIZE) {
 429                         /* We are fabricating 8MB pages using 4MB
 430                          * real hw pages.
 431                          */
 432                         pte_val(pte) |= (address & (1UL << REAL_HPAGE_SHIFT));
 433                 }
 434
 435                 if (hugepage_size >= PMD_SIZE) {
 436                         __update_mmu_tsb_insert(mm, MM_TSB_HUGE,
 437                                 REAL_HPAGE_SHIFT, address, pte_val(pte));
 438                         is_huge_tsb = true;
 439                 }
 440         }
 441 #endif
 442         if (!is_huge_tsb)
 443                 __update_mmu_tsb_insert(mm, MM_TSB_BASE, PAGE_SHIFT,
 444                                         address, pte_val(pte));
 445
 446         spin_unlock_irqrestore(&mm->context.lock, flags);
 447 }
 448
 449 void flush_dcache_page(struct page *page)
 450 {
 451         struct address_space *mapping;
 452         int this_cpu;
 453
 454         if (tlb_type == hypervisor)
 455                 return;
 456
 457         /* Do not bother with the expensive D-cache flush if it
 458          * is merely the zero page.  The 'bigcore' testcase in GDB
 459          * causes this case to run millions of times.
 460          */
 461         if (page == ZERO_PAGE(0))
 462                 return;
 463
 464         this_cpu = get_cpu();
 465
 466         mapping = page_mapping_file(page);
 467         if (mapping && !mapping_mapped(mapping)) {
 468                 int dirty = test_bit(PG_dcache_dirty, &page->flags);
 469                 if (dirty) {
 470                         int dirty_cpu = dcache_dirty_cpu(page);
 471
 472                         if (dirty_cpu == this_cpu)
 473                                 goto out;
 474                         smp_flush_dcache_page_impl(page, dirty_cpu);
 475                 }
 476                 set_dcache_dirty(page, this_cpu);
 477         } else {
 478                 /* We could delay the flush for the !page_mapping
 479                  * case too.  But that case is for exec env/arg
 480                  * pages and those are %99 certainly going to get
 481                  * faulted into the tlb (and thus flushed) anyways.
 482                  */
 483                 flush_dcache_page_impl(page);
 484         }
 485
 486 out:
 487         put_cpu();
 488 }
 489 EXPORT_SYMBOL(flush_dcache_page);
 490
 491 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
 492 {
 493         /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
 494         if (tlb_type == spitfire) {
 495                 unsigned long kaddr;
 496
 497                 /* This code only runs on Spitfire cpus so this is
 498                  * why we can assume _PAGE_PADDR_4U.
 499                  */
 500                 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
 501                         unsigned long paddr, mask = _PAGE_PADDR_4U;
 502
 503                         if (kaddr >= PAGE_OFFSET)
 504                                 paddr = kaddr & mask;
 505                         else {
 506                                 pgd_t *pgdp = pgd_offset_k(kaddr);
 507                                 p4d_t *p4dp = p4d_offset(pgdp, kaddr);
 508                                 pud_t *pudp = pud_offset(p4dp, kaddr);
 509                                 pmd_t *pmdp = pmd_offset(pudp, kaddr);
 510                                 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
 511
 512                                 paddr = pte_val(*ptep) & mask;
 513                         }
 514                         __flush_icache_page(paddr);
 515                 }
 516         }
 517 }
 518 EXPORT_SYMBOL(flush_icache_range);
 519
 520 void mmu_info(struct seq_file *m)
 521 {
 522         static const char *pgsz_strings[] = {
 523                 "8K", "64K", "512K", "4MB", "32MB",
 524                 "256MB", "2GB", "16GB",
 525         };
 526         int i, printed;
 527
 528         if (tlb_type == cheetah)
 529                 seq_printf(m, "MMU Type\t: Cheetah\n");
 530         else if (tlb_type == cheetah_plus)
 531                 seq_printf(m, "MMU Type\t: Cheetah+\n");
 532         else if (tlb_type == spitfire)
 533                 seq_printf(m, "MMU Type\t: Spitfire\n");
 534         else if (tlb_type == hypervisor)
 535                 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
 536         else
 537                 seq_printf(m, "MMU Type\t: ???\n");
 538
 539         seq_printf(m, "MMU PGSZs\t: ");
 540         printed = 0;
 541         for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) {
 542                 if (cpu_pgsz_mask & (1UL << i)) {
 543                         seq_printf(m, "%s%s",
 544                                    printed ? "," : "", pgsz_strings[i]);
 545                         printed++;
 546                 }
 547         }
 548         seq_putc(m, '\n');
 549
 550 #ifdef CONFIG_DEBUG_DCFLUSH
 551         seq_printf(m, "DCPageFlushes\t: %d\n",
 552                    atomic_read(&dcpage_flushes));
 553 #ifdef CONFIG_SMP
 554         seq_printf(m, "DCPageFlushesXC\t: %d\n",
 555                    atomic_read(&dcpage_flushes_xcall));
 556 #endif /* CONFIG_SMP */
 557 #endif /* CONFIG_DEBUG_DCFLUSH */
 558 }
 559
 560 struct linux_prom_translation prom_trans[512] __read_mostly;
 561 unsigned int prom_trans_ents __read_mostly;
 562
 563 unsigned long kern_locked_tte_data;
 564
 565 /* The obp translations are saved based on 8k pagesize, since obp can
 566  * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
 567  * HI_OBP_ADDRESS range are handled in ktlb.S.
 568  */
 569 static inline int in_obp_range(unsigned long vaddr)
 570 {
 571         return (vaddr >= LOW_OBP_ADDRESS &&
 572                 vaddr < HI_OBP_ADDRESS);
 573 }
 574
 575 static int cmp_ptrans(const void *a, const void *b)
 576 {
 577         const struct linux_prom_translation *x = a, *y = b;
 578
 579         if (x->virt > y->virt)
 580                 return 1;
 581         if (x->virt < y->virt)
 582                 return -1;
 583         return 0;
 584 }
 585
 586 /* Read OBP translations property into 'prom_trans[]'.  */
 587 static void __init read_obp_translations(void)
 588 {
 589         int n, node, ents, first, last, i;
 590
 591         node = prom_finddevice("/virtual-memory");
 592         n = prom_getproplen(node, "translations");
 593         if (unlikely(n == 0 || n == -1)) {
 594                 prom_printf("prom_mappings: Couldn't get size.\n");
 595                 prom_halt();
 596         }
 597         if (unlikely(n > sizeof(prom_trans))) {
 598                 prom_printf("prom_mappings: Size %d is too big.\n", n);
 599                 prom_halt();
 600         }
 601
 602         if ((n = prom_getproperty(node, "translations",
 603                                   (char *)&prom_trans[0],
 604                                   sizeof(prom_trans))) == -1) {
 605                 prom_printf("prom_mappings: Couldn't get property.\n");
 606                 prom_halt();
 607         }
 608
 609         n = n / sizeof(struct linux_prom_translation);
 610
 611         ents = n;
 612
 613         sort(prom_trans, ents, sizeof(struct linux_prom_translation),
 614              cmp_ptrans, NULL);
 615
 616         /* Now kick out all the non-OBP entries.  */
 617         for (i = 0; i < ents; i++) {
 618                 if (in_obp_range(prom_trans[i].virt))
 619                         break;
 620         }
 621         first = i;
 622         for (; i < ents; i++) {
 623                 if (!in_obp_range(prom_trans[i].virt))
 624                         break;
 625         }
 626         last = i;
 627
 628         for (i = 0; i < (last - first); i++) {
 629                 struct linux_prom_translation *src = &prom_trans[i + first];
 630                 struct linux_prom_translation *dest = &prom_trans[i];
 631
 632                 *dest = *src;
 633         }
 634         for (; i < ents; i++) {
 635                 struct linux_prom_translation *dest = &prom_trans[i];
 636                 dest->virt = dest->size = dest->data = 0x0UL;
 637         }
 638
 639         prom_trans_ents = last - first;
 640
 641         if (tlb_type == spitfire) {
 642                 /* Clear diag TTE bits. */
 643                 for (i = 0; i < prom_trans_ents; i++)
 644                         prom_trans[i].data &= ~0x0003fe0000000000UL;
 645         }
 646
 647         /* Force execute bit on.  */
 648         for (i = 0; i < prom_trans_ents; i++)
 649                 prom_trans[i].data |= (tlb_type == hypervisor ?
 650                                        _PAGE_EXEC_4V : _PAGE_EXEC_4U);
 651 }
 652
 653 static void __init hypervisor_tlb_lock(unsigned long vaddr,
 654                                        unsigned long pte,
 655                                        unsigned long mmu)
 656 {
 657         unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
 658
 659         if (ret != 0) {
 660                 prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: "
 661                             "errors with %lx\n", vaddr, 0, pte, mmu, ret);
 662                 prom_halt();
 663         }
 664 }
 665
 666 static unsigned long kern_large_tte(unsigned long paddr);
 667
 668 static void __init remap_kernel(void)
 669 {
 670         unsigned long phys_page, tte_vaddr, tte_data;
 671         int i, tlb_ent = sparc64_highest_locked_tlbent();
 672
 673         tte_vaddr = (unsigned long) KERNBASE;
 674         phys_page = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
 675         tte_data = kern_large_tte(phys_page);
 676
 677         kern_locked_tte_data = tte_data;
 678
 679         /* Now lock us into the TLBs via Hypervisor or OBP. */
 680         if (tlb_type == hypervisor) {
 681                 for (i = 0; i < num_kernel_image_mappings; i++) {
 682                         hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
 683                         hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
 684                         tte_vaddr += 0x400000;
 685                         tte_data += 0x400000;
 686                 }
 687         } else {
 688                 for (i = 0; i < num_kernel_image_mappings; i++) {
 689                         prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
 690                         prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
 691                         tte_vaddr += 0x400000;
 692                         tte_data += 0x400000;
 693                 }
 694                 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
 695         }
 696         if (tlb_type == cheetah_plus) {
 697                 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
 698                                             CTX_CHEETAH_PLUS_NUC);
 699                 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
 700                 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
 701         }
 702 }
 703
 704
 705 static void __init inherit_prom_mappings(void)
 706 {
 707         /* Now fixup OBP's idea about where we really are mapped. */
 708         printk("Remapping the kernel... ");
 709         remap_kernel();
 710         printk("done.\n");
 711 }
 712
 713 void prom_world(int enter)
 714 {
 715         if (!enter)
 716                 set_fs(get_fs());
 717
 718         __asm__ __volatile__("flushw");
 719 }
 720
 721 void __flush_dcache_range(unsigned long start, unsigned long end)
 722 {
 723         unsigned long va;
 724
 725         if (tlb_type == spitfire) {
 726                 int n = 0;
 727
 728                 for (va = start; va < end; va += 32) {
 729                         spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
 730                         if (++n >= 512)
 731                                 break;
 732                 }
 733         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 734                 start = __pa(start);
 735                 end = __pa(end);
 736                 for (va = start; va < end; va += 32)
 737                         __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 738                                              "membar #Sync"
 739                                              : /* no outputs */
 740                                              : "r" (va),
 741                                                "i" (ASI_DCACHE_INVALIDATE));
 742         }
 743 }
 744 EXPORT_SYMBOL(__flush_dcache_range);
 745
 746 /* get_new_mmu_context() uses "cache + 1".  */
 747 DEFINE_SPINLOCK(ctx_alloc_lock);
 748 unsigned long tlb_context_cache = CTX_FIRST_VERSION;
 749 #define MAX_CTX_NR      (1UL << CTX_NR_BITS)
 750 #define CTX_BMAP_SLOTS  BITS_TO_LONGS(MAX_CTX_NR)
 751 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
 752 DEFINE_PER_CPU(struct mm_struct *, per_cpu_secondary_mm) = {0};
 753
 754 static void mmu_context_wrap(void)
 755 {
 756         unsigned long old_ver = tlb_context_cache & CTX_VERSION_MASK;
 757         unsigned long new_ver, new_ctx, old_ctx;
 758         struct mm_struct *mm;
 759         int cpu;
 760
 761         bitmap_zero(mmu_context_bmap, 1 << CTX_NR_BITS);
 762
 763         /* Reserve kernel context */
 764         set_bit(0, mmu_context_bmap);
 765
 766         new_ver = (tlb_context_cache & CTX_VERSION_MASK) + CTX_FIRST_VERSION;
 767         if (unlikely(new_ver == 0))
 768                 new_ver = CTX_FIRST_VERSION;
 769         tlb_context_cache = new_ver;
 770
 771         /*
 772          * Make sure that any new mm that are added into per_cpu_secondary_mm,
 773          * are going to go through get_new_mmu_context() path.
 774          */
 775         mb();
 776
 777         /*
 778          * Updated versions to current on those CPUs that had valid secondary
 779          * contexts
 780          */
 781         for_each_online_cpu(cpu) {
 782                 /*
 783                  * If a new mm is stored after we took this mm from the array,
 784                  * it will go into get_new_mmu_context() path, because we
 785                  * already bumped the version in tlb_context_cache.
 786                  */
 787                 mm = per_cpu(per_cpu_secondary_mm, cpu);
 788
 789                 if (unlikely(!mm || mm == &init_mm))
 790                         continue;
 791
 792                 old_ctx = mm->context.sparc64_ctx_val;
 793                 if (likely((old_ctx & CTX_VERSION_MASK) == old_ver)) {
 794                         new_ctx = (old_ctx & ~CTX_VERSION_MASK) | new_ver;
 795                         set_bit(new_ctx & CTX_NR_MASK, mmu_context_bmap);
 796                         mm->context.sparc64_ctx_val = new_ctx;
 797                 }
 798         }
 799 }
 800
 801 /* Caller does TLB context flushing on local CPU if necessary.
 802  * The caller also ensures that CTX_VALID(mm->context) is false.
 803  *
 804  * We must be careful about boundary cases so that we never
 805  * let the user have CTX 0 (nucleus) or we ever use a CTX
 806  * version of zero (and thus NO_CONTEXT would not be caught
 807  * by version mis-match tests in mmu_context.h).
 808  *
 809  * Always invoked with interrupts disabled.
 810  */
 811 void get_new_mmu_context(struct mm_struct *mm)
 812 {
 813         unsigned long ctx, new_ctx;
 814         unsigned long orig_pgsz_bits;
 815
 816         spin_lock(&ctx_alloc_lock);
 817 retry:
 818         /* wrap might have happened, test again if our context became valid */
 819         if (unlikely(CTX_VALID(mm->context)))
 820                 goto out;
 821         orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
 822         ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
 823         new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
 824         if (new_ctx >= (1 << CTX_NR_BITS)) {
 825                 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
 826                 if (new_ctx >= ctx) {
 827                         mmu_context_wrap();
 828                         goto retry;
 829                 }
 830         }
 831         if (mm->context.sparc64_ctx_val)
 832                 cpumask_clear(mm_cpumask(mm));
 833         mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
 834         new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
 835         tlb_context_cache = new_ctx;
 836         mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
 837 out:
 838         spin_unlock(&ctx_alloc_lock);
 839 }
 840
 841 static int numa_enabled = 1;
 842 static int numa_debug;
 843
 844 static int __init early_numa(char *p)
 845 {
 846         if (!p)
 847                 return 0;
 848
 849         if (strstr(p, "off"))
 850                 numa_enabled = 0;
 851
 852         if (strstr(p, "debug"))
 853                 numa_debug = 1;
 854
 855         return 0;
 856 }
 857 early_param("numa", early_numa);
 858
 859 #define numadbg(f, a...) \
 860 do {    if (numa_debug) \
 861                 printk(KERN_INFO f, ## a); \
 862 } while (0)
 863
 864 static void __init find_ramdisk(unsigned long phys_base)
 865 {
 866 #ifdef CONFIG_BLK_DEV_INITRD
 867         if (sparc_ramdisk_image || sparc_ramdisk_image64) {
 868                 unsigned long ramdisk_image;
 869
 870                 /* Older versions of the bootloader only supported a
 871                  * 32-bit physical address for the ramdisk image
 872                  * location, stored at sparc_ramdisk_image.  Newer
 873                  * SILO versions set sparc_ramdisk_image to zero and
 874                  * provide a full 64-bit physical address at
 875                  * sparc_ramdisk_image64.
 876                  */
 877                 ramdisk_image = sparc_ramdisk_image;
 878                 if (!ramdisk_image)
 879                         ramdisk_image = sparc_ramdisk_image64;
 880
 881                 /* Another bootloader quirk.  The bootloader normalizes
 882                  * the physical address to KERNBASE, so we have to
 883                  * factor that back out and add in the lowest valid
 884                  * physical page address to get the true physical address.
 885                  */
 886                 ramdisk_image -= KERNBASE;
 887                 ramdisk_image += phys_base;
 888
 889                 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
 890                         ramdisk_image, sparc_ramdisk_size);
 891
 892                 initrd_start = ramdisk_image;
 893                 initrd_end = ramdisk_image + sparc_ramdisk_size;
 894
 895                 memblock_reserve(initrd_start, sparc_ramdisk_size);
 896
 897                 initrd_start += PAGE_OFFSET;
 898                 initrd_end += PAGE_OFFSET;
 899         }
 900 #endif
 901 }
 902
 903 struct node_mem_mask {
 904         unsigned long mask;
 905         unsigned long match;
 906 };
 907 static struct node_mem_mask node_masks[MAX_NUMNODES];
 908 static int num_node_masks;
 909
 910 #ifdef CONFIG_NEED_MULTIPLE_NODES
 911
 912 struct mdesc_mlgroup {
 913         u64     node;
 914         u64     latency;
 915         u64     match;
 916         u64     mask;
 917 };
 918
 919 static struct mdesc_mlgroup *mlgroups;
 920 static int num_mlgroups;
 921
 922 int numa_cpu_lookup_table[NR_CPUS];
 923 cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
 924
 925 struct mdesc_mblock {
 926         u64     base;
 927         u64     size;
 928         u64     offset; /* RA-to-PA */
 929 };
 930 static struct mdesc_mblock *mblocks;
 931 static int num_mblocks;
 932
 933 static struct mdesc_mblock * __init addr_to_mblock(unsigned long addr)
 934 {
 935         struct mdesc_mblock *m = NULL;
 936         int i;
 937
 938         for (i = 0; i < num_mblocks; i++) {
 939                 m = &mblocks[i];
 940
 941                 if (addr >= m->base &&
 942                     addr < (m->base + m->size)) {
 943                         break;
 944                 }
 945         }
 946
 947         return m;
 948 }
 949
 950 static u64 __init memblock_nid_range_sun4u(u64 start, u64 end, int *nid)
 951 {
 952         int prev_nid, new_nid;
 953
 954         prev_nid = NUMA_NO_NODE;
 955         for ( ; start < end; start += PAGE_SIZE) {
 956                 for (new_nid = 0; new_nid < num_node_masks; new_nid++) {
 957                         struct node_mem_mask *p = &node_masks[new_nid];
 958
 959                         if ((start & p->mask) == p->match) {
 960                                 if (prev_nid == NUMA_NO_NODE)
 961                                         prev_nid = new_nid;
 962                                 break;
 963                         }
 964                 }
 965
 966                 if (new_nid == num_node_masks) {
 967                         prev_nid = 0;
 968                         WARN_ONCE(1, "addr[%Lx] doesn't match a NUMA node rule. Some memory will be owned by node 0.",
 969                                   start);
 970                         break;
 971                 }
 972
 973                 if (prev_nid != new_nid)
 974                         break;
 975         }
 976         *nid = prev_nid;
 977
 978         return start > end ? end : start;
 979 }
 980
 981 static u64 __init memblock_nid_range(u64 start, u64 end, int *nid)
 982 {
 983         u64 ret_end, pa_start, m_mask, m_match, m_end;
 984         struct mdesc_mblock *mblock;
 985         int _nid, i;
 986
 987         if (tlb_type != hypervisor)
 988                 return memblock_nid_range_sun4u(start, end, nid);
 989
 990         mblock = addr_to_mblock(start);
 991         if (!mblock) {
 992                 WARN_ONCE(1, "memblock_nid_range: Can't find mblock addr[%Lx]",
 993                           start);
 994
 995                 _nid = 0;
 996                 ret_end = end;
 997                 goto done;
 998         }
 999
1000         pa_start = start + mblock->offset;
1001         m_match = 0;
1002         m_mask = 0;
1003
1004         for (_nid = 0; _nid < num_node_masks; _nid++) {
1005                 struct node_mem_mask *const m = &node_masks[_nid];
1006
1007                 if ((pa_start & m->mask) == m->match) {
1008                         m_match = m->match;
1009                         m_mask = m->mask;
1010                         break;
1011                 }
1012         }
1013
1014         if (num_node_masks == _nid) {
1015                 /* We could not find NUMA group, so default to 0, but lets
1016                  * search for latency group, so we could calculate the correct
1017                  * end address that we return
1018                  */
1019                 _nid = 0;
1020
1021                 for (i = 0; i < num_mlgroups; i++) {
1022                         struct mdesc_mlgroup *const m = &mlgroups[i];
1023
1024                         if ((pa_start & m->mask) == m->match) {
1025                                 m_match = m->match;
1026                                 m_mask = m->mask;
1027                                 break;
1028                         }
1029                 }
1030
1031                 if (i == num_mlgroups) {
1032                         WARN_ONCE(1, "memblock_nid_range: Can't find latency group addr[%Lx]",
1033                                   start);
1034
1035                         ret_end = end;
1036                         goto done;
1037                 }
1038         }
1039
1040         /*
1041          * Each latency group has match and mask, and each memory block has an
1042          * offset.  An address belongs to a latency group if its address matches
1043          * the following formula: ((addr + offset) & mask) == match
1044          * It is, however, slow to check every single page if it matches a
1045          * particular latency group. As optimization we calculate end value by
1046          * using bit arithmetics.
1047          */
1048         m_end = m_match + (1ul << __ffs(m_mask)) - mblock->offset;
1049         m_end += pa_start & ~((1ul << fls64(m_mask)) - 1);
1050         ret_end = m_end > end ? end : m_end;
1051
1052 done:
1053         *nid = _nid;
1054         return ret_end;
1055 }
1056 #endif
1057
1058 /* This must be invoked after performing all of the necessary
1059  * memblock_set_node() calls for 'nid'.  We need to be able to get
1060  * correct data from get_pfn_range_for_nid().
1061  */
1062 static void __init allocate_node_data(int nid)
1063 {
1064         struct pglist_data *p;
1065         unsigned long start_pfn, end_pfn;
1066 #ifdef CONFIG_NEED_MULTIPLE_NODES
1067
1068         NODE_DATA(nid) = memblock_alloc_node(sizeof(struct pglist_data),
1069                                              SMP_CACHE_BYTES, nid);
1070         if (!NODE_DATA(nid)) {
1071                 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
1072                 prom_halt();
1073         }
1074
1075         NODE_DATA(nid)->node_id = nid;
1076 #endif
1077
1078         p = NODE_DATA(nid);
1079
1080         get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
1081         p->node_start_pfn = start_pfn;
1082         p->node_spanned_pages = end_pfn - start_pfn;
1083 }
1084
1085 static void init_node_masks_nonnuma(void)
1086 {
1087 #ifdef CONFIG_NEED_MULTIPLE_NODES
1088         int i;
1089 #endif
1090
1091         numadbg("Initializing tables for non-numa.\n");
1092
1093         node_masks[0].mask = 0;
1094         node_masks[0].match = 0;
1095         num_node_masks = 1;
1096
1097 #ifdef CONFIG_NEED_MULTIPLE_NODES
1098         for (i = 0; i < NR_CPUS; i++)
1099                 numa_cpu_lookup_table[i] = 0;
1100
1101         cpumask_setall(&numa_cpumask_lookup_table[0]);
1102 #endif
1103 }
1104
1105 #ifdef CONFIG_NEED_MULTIPLE_NODES
1106 struct pglist_data *node_data[MAX_NUMNODES];
1107
1108 EXPORT_SYMBOL(numa_cpu_lookup_table);
1109 EXPORT_SYMBOL(numa_cpumask_lookup_table);
1110 EXPORT_SYMBOL(node_data);
1111
1112 static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
1113                                    u32 cfg_handle)
1114 {
1115         u64 arc;
1116
1117         mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
1118                 u64 target = mdesc_arc_target(md, arc);
1119                 const u64 *val;
1120
1121                 val = mdesc_get_property(md, target,
1122                                          "cfg-handle", NULL);
1123                 if (val && *val == cfg_handle)
1124                         return 0;
1125         }
1126         return -ENODEV;
1127 }
1128
1129 static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
1130                                     u32 cfg_handle)
1131 {
1132         u64 arc, candidate, best_latency = ~(u64)0;
1133
1134         candidate = MDESC_NODE_NULL;
1135         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1136                 u64 target = mdesc_arc_target(md, arc);
1137                 const char *name = mdesc_node_name(md, target);
1138                 const u64 *val;
1139
1140                 if (strcmp(name, "pio-latency-group"))
1141                         continue;
1142
1143                 val = mdesc_get_property(md, target, "latency", NULL);
1144                 if (!val)
1145                         continue;
1146
1147                 if (*val < best_latency) {
1148                         candidate = target;
1149                         best_latency = *val;
1150                 }
1151         }
1152
1153         if (candidate == MDESC_NODE_NULL)
1154                 return -ENODEV;
1155
1156         return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
1157 }
1158
1159 int of_node_to_nid(struct device_node *dp)
1160 {
1161         const struct linux_prom64_registers *regs;
1162         struct mdesc_handle *md;
1163         u32 cfg_handle;
1164         int count, nid;
1165         u64 grp;
1166
1167         /* This is the right thing to do on currently supported
1168          * SUN4U NUMA platforms as well, as the PCI controller does
1169          * not sit behind any particular memory controller.
1170          */
1171         if (!mlgroups)
1172                 return -1;
1173
1174         regs = of_get_property(dp, "reg", NULL);
1175         if (!regs)
1176                 return -1;
1177
1178         cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
1179
1180         md = mdesc_grab();
1181
1182         count = 0;
1183         nid = NUMA_NO_NODE;
1184         mdesc_for_each_node_by_name(md, grp, "group") {
1185                 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
1186                         nid = count;
1187                         break;
1188                 }
1189                 count++;
1190         }
1191
1192         mdesc_release(md);
1193
1194         return nid;
1195 }
1196
1197 static void __init add_node_ranges(void)
1198 {
1199         struct memblock_region *reg;
1200         unsigned long prev_max;
1201
1202 memblock_resized:
1203         prev_max = memblock.memory.max;
1204
1205         for_each_memblock(memory, reg) {
1206                 unsigned long size = reg->size;
1207                 unsigned long start, end;
1208
1209                 start = reg->base;
1210                 end = start + size;
1211                 while (start < end) {
1212                         unsigned long this_end;
1213                         int nid;
1214
1215                         this_end = memblock_nid_range(start, end, &nid);
1216
1217                         numadbg("Setting memblock NUMA node nid[%d] "
1218                                 "start[%lx] end[%lx]\n",
1219                                 nid, start, this_end);
1220
1221                         memblock_set_node(start, this_end - start,
1222                                           &memblock.memory, nid);
1223                         if (memblock.memory.max != prev_max)
1224                                 goto memblock_resized;
1225                         start = this_end;
1226                 }
1227         }
1228 }
1229
1230 static int __init grab_mlgroups(struct mdesc_handle *md)
1231 {
1232         unsigned long paddr;
1233         int count = 0;
1234         u64 node;
1235
1236         mdesc_for_each_node_by_name(md, node, "memory-latency-group")
1237                 count++;
1238         if (!count)
1239                 return -ENOENT;
1240
1241         paddr = memblock_phys_alloc(count * sizeof(struct mdesc_mlgroup),
1242                                     SMP_CACHE_BYTES);
1243         if (!paddr)
1244                 return -ENOMEM;
1245
1246         mlgroups = __va(paddr);
1247         num_mlgroups = count;
1248
1249         count = 0;
1250         mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1251                 struct mdesc_mlgroup *m = &mlgroups[count++];
1252                 const u64 *val;
1253
1254                 m->node = node;
1255
1256                 val = mdesc_get_property(md, node, "latency", NULL);
1257                 m->latency = *val;
1258                 val = mdesc_get_property(md, node, "address-match", NULL);
1259                 m->match = *val;
1260                 val = mdesc_get_property(md, node, "address-mask", NULL);
1261                 m->mask = *val;
1262
1263                 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
1264                         "match[%llx] mask[%llx]\n",
1265                         count - 1, m->node, m->latency, m->match, m->mask);
1266         }
1267
1268         return 0;
1269 }
1270
1271 static int __init grab_mblocks(struct mdesc_handle *md)
1272 {
1273         unsigned long paddr;
1274         int count = 0;
1275         u64 node;
1276
1277         mdesc_for_each_node_by_name(md, node, "mblock")
1278                 count++;
1279         if (!count)
1280                 return -ENOENT;
1281
1282         paddr = memblock_phys_alloc(count * sizeof(struct mdesc_mblock),
1283                                     SMP_CACHE_BYTES);
1284         if (!paddr)
1285                 return -ENOMEM;
1286
1287         mblocks = __va(paddr);
1288         num_mblocks = count;
1289
1290         count = 0;
1291         mdesc_for_each_node_by_name(md, node, "mblock") {
1292                 struct mdesc_mblock *m = &mblocks[count++];
1293                 const u64 *val;
1294
1295                 val = mdesc_get_property(md, node, "base", NULL);
1296                 m->base = *val;
1297                 val = mdesc_get_property(md, node, "size", NULL);
1298                 m->size = *val;
1299                 val = mdesc_get_property(md, node,
1300                                          "address-congruence-offset", NULL);
1301
1302                 /* The address-congruence-offset property is optional.
1303                  * Explicity zero it be identifty this.
1304                  */
1305                 if (val)
1306                         m->offset = *val;
1307                 else
1308                         m->offset = 0UL;
1309
1310                 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
1311                         count - 1, m->base, m->size, m->offset);
1312         }
1313
1314         return 0;
1315 }
1316
1317 static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1318                                                u64 grp, cpumask_t *mask)
1319 {
1320         u64 arc;
1321
1322         cpumask_clear(mask);
1323
1324         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1325                 u64 target = mdesc_arc_target(md, arc);
1326                 const char *name = mdesc_node_name(md, target);
1327                 const u64 *id;
1328
1329                 if (strcmp(name, "cpu"))
1330                         continue;
1331                 id = mdesc_get_property(md, target, "id", NULL);
1332                 if (*id < nr_cpu_ids)
1333                         cpumask_set_cpu(*id, mask);
1334         }
1335 }
1336
1337 static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1338 {
1339         int i;
1340
1341         for (i = 0; i < num_mlgroups; i++) {
1342                 struct mdesc_mlgroup *m = &mlgroups[i];
1343                 if (m->node == node)
1344                         return m;
1345         }
1346         return NULL;
1347 }
1348
1349 int __node_distance(int from, int to)
1350 {
1351         if ((from >= MAX_NUMNODES) || (to >= MAX_NUMNODES)) {
1352                 pr_warn("Returning default NUMA distance value for %d->%d\n",
1353                         from, to);
1354                 return (from == to) ? LOCAL_DISTANCE : REMOTE_DISTANCE;
1355         }
1356         return numa_latency[from][to];
1357 }
1358 EXPORT_SYMBOL(__node_distance);
1359
1360 static int __init find_best_numa_node_for_mlgroup(struct mdesc_mlgroup *grp)
1361 {
1362         int i;
1363
1364         for (i = 0; i < MAX_NUMNODES; i++) {
1365                 struct node_mem_mask *n = &node_masks[i];
1366
1367                 if ((grp->mask == n->mask) && (grp->match == n->match))
1368                         break;
1369         }
1370         return i;
1371 }
1372
1373 static void __init find_numa_latencies_for_group(struct mdesc_handle *md,
1374                                                  u64 grp, int index)
1375 {
1376         u64 arc;
1377
1378         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1379                 int tnode;
1380                 u64 target = mdesc_arc_target(md, arc);
1381                 struct mdesc_mlgroup *m = find_mlgroup(target);
1382
1383                 if (!m)
1384                         continue;
1385                 tnode = find_best_numa_node_for_mlgroup(m);
1386                 if (tnode == MAX_NUMNODES)
1387                         continue;
1388                 numa_latency[index][tnode] = m->latency;
1389         }
1390 }
1391
1392 static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1393                                       int index)
1394 {
1395         struct mdesc_mlgroup *candidate = NULL;
1396         u64 arc, best_latency = ~(u64)0;
1397         struct node_mem_mask *n;
1398
1399         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1400                 u64 target = mdesc_arc_target(md, arc);
1401                 struct mdesc_mlgroup *m = find_mlgroup(target);
1402                 if (!m)
1403                         continue;
1404                 if (m->latency < best_latency) {
1405                         candidate = m;
1406                         best_latency = m->latency;
1407                 }
1408         }
1409         if (!candidate)
1410                 return -ENOENT;
1411
1412         if (num_node_masks != index) {
1413                 printk(KERN_ERR "Inconsistent NUMA state, "
1414                        "index[%d] != num_node_masks[%d]\n",
1415                        index, num_node_masks);
1416                 return -EINVAL;
1417         }
1418
1419         n = &node_masks[num_node_masks++];
1420
1421         n->mask = candidate->mask;
1422         n->match = candidate->match;
1423
1424         numadbg("NUMA NODE[%d]: mask[%lx] match[%lx] (latency[%llx])\n",
1425                 index, n->mask, n->match, candidate->latency);
1426
1427         return 0;
1428 }
1429
1430 static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1431                                          int index)
1432 {
1433         cpumask_t mask;
1434         int cpu;
1435
1436         numa_parse_mdesc_group_cpus(md, grp, &mask);
1437
1438         for_each_cpu(cpu, &mask)
1439                 numa_cpu_lookup_table[cpu] = index;
1440         cpumask_copy(&numa_cpumask_lookup_table[index], &mask);
1441
1442         if (numa_debug) {
1443                 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
1444                 for_each_cpu(cpu, &mask)
1445                         printk("%d ", cpu);
1446                 printk("]\n");
1447         }
1448
1449         return numa_attach_mlgroup(md, grp, index);
1450 }
1451
1452 static int __init numa_parse_mdesc(void)
1453 {
1454         struct mdesc_handle *md = mdesc_grab();
1455         int i, j, err, count;
1456         u64 node;
1457
1458         node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1459         if (node == MDESC_NODE_NULL) {
1460                 mdesc_release(md);
1461                 return -ENOENT;
1462         }
1463
1464         err = grab_mblocks(md);
1465         if (err < 0)
1466                 goto out;
1467
1468         err = grab_mlgroups(md);
1469         if (err < 0)
1470                 goto out;
1471
1472         count = 0;
1473         mdesc_for_each_node_by_name(md, node, "group") {
1474                 err = numa_parse_mdesc_group(md, node, count);
1475                 if (err < 0)
1476                         break;
1477                 count++;
1478         }
1479
1480         count = 0;
1481         mdesc_for_each_node_by_name(md, node, "group") {
1482                 find_numa_latencies_for_group(md, node, count);
1483                 count++;
1484         }
1485
1486         /* Normalize numa latency matrix according to ACPI SLIT spec. */
1487         for (i = 0; i < MAX_NUMNODES; i++) {
1488                 u64 self_latency = numa_latency[i][i];
1489
1490                 for (j = 0; j < MAX_NUMNODES; j++) {
1491                         numa_latency[i][j] =
1492                                 (numa_latency[i][j] * LOCAL_DISTANCE) /
1493                                 self_latency;
1494                 }
1495         }
1496
1497         add_node_ranges();
1498
1499         for (i = 0; i < num_node_masks; i++) {
1500                 allocate_node_data(i);
1501                 node_set_online(i);
1502         }
1503
1504         err = 0;
1505 out:
1506         mdesc_release(md);
1507         return err;
1508 }
1509
1510 static int __init numa_parse_jbus(void)
1511 {
1512         unsigned long cpu, index;
1513
1514         /* NUMA node id is encoded in bits 36 and higher, and there is
1515          * a 1-to-1 mapping from CPU ID to NUMA node ID.
1516          */
1517         index = 0;
1518         for_each_present_cpu(cpu) {
1519                 numa_cpu_lookup_table[cpu] = index;
1520                 cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu));
1521                 node_masks[index].mask = ~((1UL << 36UL) - 1UL);
1522                 node_masks[index].match = cpu << 36UL;
1523
1524                 index++;
1525         }
1526         num_node_masks = index;
1527
1528         add_node_ranges();
1529
1530         for (index = 0; index < num_node_masks; index++) {
1531                 allocate_node_data(index);
1532                 node_set_online(index);
1533         }
1534
1535         return 0;
1536 }
1537
1538 static int __init numa_parse_sun4u(void)
1539 {
1540         if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1541                 unsigned long ver;
1542
1543                 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
1544                 if ((ver >> 32UL) == __JALAPENO_ID ||
1545                     (ver >> 32UL) == __SERRANO_ID)
1546                         return numa_parse_jbus();
1547         }
1548         return -1;
1549 }
1550
1551 static int __init bootmem_init_numa(void)
1552 {
1553         int i, j;
1554         int err = -1;
1555
1556         numadbg("bootmem_init_numa()\n");
1557
1558         /* Some sane defaults for numa latency values */
1559         for (i = 0; i < MAX_NUMNODES; i++) {
1560                 for (j = 0; j < MAX_NUMNODES; j++)
1561                         numa_latency[i][j] = (i == j) ?
1562                                 LOCAL_DISTANCE : REMOTE_DISTANCE;
1563         }
1564
1565         if (numa_enabled) {
1566                 if (tlb_type == hypervisor)
1567                         err = numa_parse_mdesc();
1568                 else
1569                         err = numa_parse_sun4u();
1570         }
1571         return err;
1572 }
1573
1574 #else
1575
1576 static int bootmem_init_numa(void)
1577 {
1578         return -1;
1579 }
1580
1581 #endif
1582
1583 static void __init bootmem_init_nonnuma(void)
1584 {
1585         unsigned long top_of_ram = memblock_end_of_DRAM();
1586         unsigned long total_ram = memblock_phys_mem_size();
1587
1588         numadbg("bootmem_init_nonnuma()\n");
1589
1590         printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1591                top_of_ram, total_ram);
1592         printk(KERN_INFO "Memory hole size: %ldMB\n",
1593                (top_of_ram - total_ram) >> 20);
1594
1595         init_node_masks_nonnuma();
1596         memblock_set_node(0, PHYS_ADDR_MAX, &memblock.memory, 0);
1597         allocate_node_data(0);
1598         node_set_online(0);
1599 }
1600
1601 static unsigned long __init bootmem_init(unsigned long phys_base)
1602 {
1603         unsigned long end_pfn;
1604
1605         end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT;
1606         max_pfn = max_low_pfn = end_pfn;
1607         min_low_pfn = (phys_base >> PAGE_SHIFT);
1608
1609         if (bootmem_init_numa() < 0)
1610                 bootmem_init_nonnuma();
1611
1612         /* Dump memblock with node info. */
1613         memblock_dump_all();
1614
1615         /* XXX cpu notifier XXX */
1616
1617         sparse_memory_present_with_active_regions(MAX_NUMNODES);
1618         sparse_init();
1619
1620         return end_pfn;
1621 }
1622
1623 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1624 static int pall_ents __initdata;
1625
1626 static unsigned long max_phys_bits = 40;
1627
1628 bool kern_addr_valid(unsigned long addr)
1629 {
1630         pgd_t *pgd;
1631         p4d_t *p4d;
1632         pud_t *pud;
1633         pmd_t *pmd;
1634         pte_t *pte;
1635
1636         if ((long)addr < 0L) {
1637                 unsigned long pa = __pa(addr);
1638
1639                 if ((pa >> max_phys_bits) != 0UL)
1640                         return false;
1641
1642                 return pfn_valid(pa >> PAGE_SHIFT);
1643         }
1644
1645         if (addr >= (unsigned long) KERNBASE &&
1646             addr < (unsigned long)&_end)
1647                 return true;
1648
1649         pgd = pgd_offset_k(addr);
1650         if (pgd_none(*pgd))
1651                 return false;
1652
1653         p4d = p4d_offset(pgd, addr);
1654         if (p4d_none(*p4d))
1655                 return false;
1656
1657         pud = pud_offset(p4d, addr);
1658         if (pud_none(*pud))
1659                 return false;
1660
1661         if (pud_large(*pud))
1662                 return pfn_valid(pud_pfn(*pud));
1663
1664         pmd = pmd_offset(pud, addr);
1665         if (pmd_none(*pmd))
1666                 return false;
1667
1668         if (pmd_large(*pmd))
1669                 return pfn_valid(pmd_pfn(*pmd));
1670
1671         pte = pte_offset_kernel(pmd, addr);
1672         if (pte_none(*pte))
1673                 return false;
1674
1675         return pfn_valid(pte_pfn(*pte));
1676 }
1677 EXPORT_SYMBOL(kern_addr_valid);
1678
1679 static unsigned long __ref kernel_map_hugepud(unsigned long vstart,
1680                                               unsigned long vend,
1681                                               pud_t *pud)
1682 {
1683         const unsigned long mask16gb = (1UL << 34) - 1UL;
1684         u64 pte_val = vstart;
1685
1686         /* Each PUD is 8GB */
1687         if ((vstart & mask16gb) ||
1688             (vend - vstart <= mask16gb)) {
1689                 pte_val ^= kern_linear_pte_xor[2];
1690                 pud_val(*pud) = pte_val | _PAGE_PUD_HUGE;
1691
1692                 return vstart + PUD_SIZE;
1693         }
1694
1695         pte_val ^= kern_linear_pte_xor[3];
1696         pte_val |= _PAGE_PUD_HUGE;
1697
1698         vend = vstart + mask16gb + 1UL;
1699         while (vstart < vend) {
1700                 pud_val(*pud) = pte_val;
1701
1702                 pte_val += PUD_SIZE;
1703                 vstart += PUD_SIZE;
1704                 pud++;
1705         }
1706         return vstart;
1707 }
1708
1709 static bool kernel_can_map_hugepud(unsigned long vstart, unsigned long vend,
1710                                    bool guard)
1711 {
1712         if (guard && !(vstart & ~PUD_MASK) && (vend - vstart) >= PUD_SIZE)
1713                 return true;
1714
1715         return false;
1716 }
1717
1718 static unsigned long __ref kernel_map_hugepmd(unsigned long vstart,
1719                                               unsigned long vend,
1720                                               pmd_t *pmd)
1721 {
1722         const unsigned long mask256mb = (1UL << 28) - 1UL;
1723         const unsigned long mask2gb = (1UL << 31) - 1UL;
1724         u64 pte_val = vstart;
1725
1726         /* Each PMD is 8MB */
1727         if ((vstart & mask256mb) ||
1728             (vend - vstart <= mask256mb)) {
1729                 pte_val ^= kern_linear_pte_xor[0];
1730                 pmd_val(*pmd) = pte_val | _PAGE_PMD_HUGE;
1731
1732                 return vstart + PMD_SIZE;
1733         }
1734
1735         if ((vstart & mask2gb) ||
1736             (vend - vstart <= mask2gb)) {
1737                 pte_val ^= kern_linear_pte_xor[1];
1738                 pte_val |= _PAGE_PMD_HUGE;
1739                 vend = vstart + mask256mb + 1UL;
1740         } else {
1741                 pte_val ^= kern_linear_pte_xor[2];
1742                 pte_val |= _PAGE_PMD_HUGE;
1743                 vend = vstart + mask2gb + 1UL;
1744         }
1745
1746         while (vstart < vend) {
1747                 pmd_val(*pmd) = pte_val;
1748
1749                 pte_val += PMD_SIZE;
1750                 vstart += PMD_SIZE;
1751                 pmd++;
1752         }
1753
1754         return vstart;
1755 }
1756
1757 static bool kernel_can_map_hugepmd(unsigned long vstart, unsigned long vend,
1758                                    bool guard)
1759 {
1760         if (guard && !(vstart & ~PMD_MASK) && (vend - vstart) >= PMD_SIZE)
1761                 return true;
1762
1763         return false;
1764 }
1765
1766 static unsigned long __ref kernel_map_range(unsigned long pstart,
1767                                             unsigned long pend, pgprot_t prot,
1768                                             bool use_huge)
1769 {
1770         unsigned long vstart = PAGE_OFFSET + pstart;
1771         unsigned long vend = PAGE_OFFSET + pend;
1772         unsigned long alloc_bytes = 0UL;
1773
1774         if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1775                 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1776                             vstart, vend);
1777                 prom_halt();
1778         }
1779
1780         while (vstart < vend) {
1781                 unsigned long this_end, paddr = __pa(vstart);
1782                 pgd_t *pgd = pgd_offset_k(vstart);
1783                 p4d_t *p4d;
1784                 pud_t *pud;
1785                 pmd_t *pmd;
1786                 pte_t *pte;
1787
1788                 if (pgd_none(*pgd)) {
1789                         pud_t *new;
1790
1791                         new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
1792                                                   PAGE_SIZE);
1793                         if (!new)
1794                                 goto err_alloc;
1795                         alloc_bytes += PAGE_SIZE;
1796                         pgd_populate(&init_mm, pgd, new);
1797                 }
1798
1799                 p4d = p4d_offset(pgd, vstart);
1800                 if (p4d_none(*p4d)) {
1801                         pud_t *new;
1802
1803                         new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
1804                                                   PAGE_SIZE);
1805                         if (!new)
1806                                 goto err_alloc;
1807                         alloc_bytes += PAGE_SIZE;
1808                         p4d_populate(&init_mm, p4d, new);
1809                 }
1810
1811                 pud = pud_offset(p4d, vstart);
1812                 if (pud_none(*pud)) {
1813                         pmd_t *new;
1814
1815                         if (kernel_can_map_hugepud(vstart, vend, use_huge)) {
1816                                 vstart = kernel_map_hugepud(vstart, vend, pud);
1817                                 continue;
1818                         }
1819                         new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
1820                                                   PAGE_SIZE);
1821                         if (!new)
1822                                 goto err_alloc;
1823                         alloc_bytes += PAGE_SIZE;
1824                         pud_populate(&init_mm, pud, new);
1825                 }
1826
1827                 pmd = pmd_offset(pud, vstart);
1828                 if (pmd_none(*pmd)) {
1829                         pte_t *new;
1830
1831                         if (kernel_can_map_hugepmd(vstart, vend, use_huge)) {
1832                                 vstart = kernel_map_hugepmd(vstart, vend, pmd);
1833                                 continue;
1834                         }
1835                         new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
1836                                                   PAGE_SIZE);
1837                         if (!new)
1838                                 goto err_alloc;
1839                         alloc_bytes += PAGE_SIZE;
1840                         pmd_populate_kernel(&init_mm, pmd, new);
1841                 }
1842
1843                 pte = pte_offset_kernel(pmd, vstart);
1844                 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1845                 if (this_end > vend)
1846                         this_end = vend;
1847
1848                 while (vstart < this_end) {
1849                         pte_val(*pte) = (paddr | pgprot_val(prot));
1850
1851                         vstart += PAGE_SIZE;
1852                         paddr += PAGE_SIZE;
1853                         pte++;
1854                 }
1855         }
1856
1857         return alloc_bytes;
1858
1859 err_alloc:
1860         panic("%s: Failed to allocate %lu bytes align=%lx from=%lx\n",
1861               __func__, PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1862         return -ENOMEM;
1863 }
1864
1865 static void __init flush_all_kernel_tsbs(void)
1866 {
1867         int i;
1868
1869         for (i = 0; i < KERNEL_TSB_NENTRIES; i++) {
1870                 struct tsb *ent = &swapper_tsb[i];
1871
1872                 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1873         }
1874 #ifndef CONFIG_DEBUG_PAGEALLOC
1875         for (i = 0; i < KERNEL_TSB4M_NENTRIES; i++) {
1876                 struct tsb *ent = &swapper_4m_tsb[i];
1877
1878                 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1879         }
1880 #endif
1881 }
1882
1883 extern unsigned int kvmap_linear_patch[1];
1884
1885 static void __init kernel_physical_mapping_init(void)
1886 {
1887         unsigned long i, mem_alloced = 0UL;
1888         bool use_huge = true;
1889
1890 #ifdef CONFIG_DEBUG_PAGEALLOC
1891         use_huge = false;
1892 #endif
1893         for (i = 0; i < pall_ents; i++) {
1894                 unsigned long phys_start, phys_end;
1895
1896                 phys_start = pall[i].phys_addr;
1897                 phys_end = phys_start + pall[i].reg_size;
1898
1899                 mem_alloced += kernel_map_range(phys_start, phys_end,
1900                                                 PAGE_KERNEL, use_huge);
1901         }
1902
1903         printk("Allocated %ld bytes for kernel page tables.\n",
1904                mem_alloced);
1905
1906         kvmap_linear_patch[0] = 0x01000000; /* nop */
1907         flushi(&kvmap_linear_patch[0]);
1908
1909         flush_all_kernel_tsbs();
1910
1911         __flush_tlb_all();
1912 }
1913
1914 #ifdef CONFIG_DEBUG_PAGEALLOC
1915 void __kernel_map_pages(struct page *page, int numpages, int enable)
1916 {
1917         unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1918         unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1919
1920         kernel_map_range(phys_start, phys_end,
1921                          (enable ? PAGE_KERNEL : __pgprot(0)), false);
1922
1923         flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1924                                PAGE_OFFSET + phys_end);
1925
1926         /* we should perform an IPI and flush all tlbs,
1927          * but that can deadlock->flush only current cpu.
1928          */
1929         __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1930                                  PAGE_OFFSET + phys_end);
1931 }
1932 #endif
1933
1934 unsigned long __init find_ecache_flush_span(unsigned long size)
1935 {
1936         int i;
1937
1938         for (i = 0; i < pavail_ents; i++) {
1939                 if (pavail[i].reg_size >= size)
1940                         return pavail[i].phys_addr;
1941         }
1942
1943         return ~0UL;
1944 }
1945
1946 unsigned long PAGE_OFFSET;
1947 EXPORT_SYMBOL(PAGE_OFFSET);
1948
1949 unsigned long VMALLOC_END   = 0x0000010000000000UL;
1950 EXPORT_SYMBOL(VMALLOC_END);
1951
1952 unsigned long sparc64_va_hole_top =    0xfffff80000000000UL;
1953 unsigned long sparc64_va_hole_bottom = 0x0000080000000000UL;
1954
1955 static void __init setup_page_offset(void)
1956 {
1957         if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1958                 /* Cheetah/Panther support a full 64-bit virtual
1959                  * address, so we can use all that our page tables
1960                  * support.
1961                  */
1962                 sparc64_va_hole_top =    0xfff0000000000000UL;
1963                 sparc64_va_hole_bottom = 0x0010000000000000UL;
1964
1965                 max_phys_bits = 42;
1966         } else if (tlb_type == hypervisor) {
1967                 switch (sun4v_chip_type) {
1968                 case SUN4V_CHIP_NIAGARA1:
1969                 case SUN4V_CHIP_NIAGARA2:
1970                         /* T1 and T2 support 48-bit virtual addresses.  */
1971                         sparc64_va_hole_top =    0xffff800000000000UL;
1972                         sparc64_va_hole_bottom = 0x0000800000000000UL;
1973
1974                         max_phys_bits = 39;
1975                         break;
1976                 case SUN4V_CHIP_NIAGARA3:
1977                         /* T3 supports 48-bit virtual addresses.  */
1978                         sparc64_va_hole_top =    0xffff800000000000UL;
1979                         sparc64_va_hole_bottom = 0x0000800000000000UL;
1980
1981                         max_phys_bits = 43;
1982                         break;
1983                 case SUN4V_CHIP_NIAGARA4:
1984                 case SUN4V_CHIP_NIAGARA5:
1985                 case SUN4V_CHIP_SPARC64X:
1986                 case SUN4V_CHIP_SPARC_M6:
1987                         /* T4 and later support 52-bit virtual addresses.  */
1988                         sparc64_va_hole_top =    0xfff8000000000000UL;
1989                         sparc64_va_hole_bottom = 0x0008000000000000UL;
1990                         max_phys_bits = 47;
1991                         break;
1992                 case SUN4V_CHIP_SPARC_M7:
1993                 case SUN4V_CHIP_SPARC_SN:
1994                         /* M7 and later support 52-bit virtual addresses.  */
1995                         sparc64_va_hole_top =    0xfff8000000000000UL;
1996                         sparc64_va_hole_bottom = 0x0008000000000000UL;
1997                         max_phys_bits = 49;
1998                         break;
1999                 case SUN4V_CHIP_SPARC_M8:
2000                 default:
2001                         /* M8 and later support 54-bit virtual addresses.
2002                          * However, restricting M8 and above VA bits to 53
2003                          * as 4-level page table cannot support more than
2004                          * 53 VA bits.
2005                          */
2006                         sparc64_va_hole_top =    0xfff0000000000000UL;
2007                         sparc64_va_hole_bottom = 0x0010000000000000UL;
2008                         max_phys_bits = 51;
2009                         break;
2010                 }
2011         }
2012
2013         if (max_phys_bits > MAX_PHYS_ADDRESS_BITS) {
2014                 prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n",
2015                             max_phys_bits);
2016                 prom_halt();
2017         }
2018
2019         PAGE_OFFSET = sparc64_va_hole_top;
2020         VMALLOC_END = ((sparc64_va_hole_bottom >> 1) +
2021                        (sparc64_va_hole_bottom >> 2));
2022
2023         pr_info("MM: PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n",
2024                 PAGE_OFFSET, max_phys_bits);
2025         pr_info("MM: VMALLOC [0x%016lx --> 0x%016lx]\n",
2026                 VMALLOC_START, VMALLOC_END);
2027         pr_info("MM: VMEMMAP [0x%016lx --> 0x%016lx]\n",
2028                 VMEMMAP_BASE, VMEMMAP_BASE << 1);
2029 }
2030
2031 static void __init tsb_phys_patch(void)
2032 {
2033         struct tsb_ldquad_phys_patch_entry *pquad;
2034         struct tsb_phys_patch_entry *p;
2035
2036         pquad = &__tsb_ldquad_phys_patch;
2037         while (pquad < &__tsb_ldquad_phys_patch_end) {
2038                 unsigned long addr = pquad->addr;
2039
2040                 if (tlb_type == hypervisor)
2041                         *(unsigned int *) addr = pquad->sun4v_insn;
2042                 else
2043                         *(unsigned int *) addr = pquad->sun4u_insn;
2044                 wmb();
2045                 __asm__ __volatile__("flush     %0"
2046                                      : /* no outputs */
2047                                      : "r" (addr));
2048
2049                 pquad++;
2050         }
2051
2052         p = &__tsb_phys_patch;
2053         while (p < &__tsb_phys_patch_end) {
2054                 unsigned long addr = p->addr;
2055
2056                 *(unsigned int *) addr = p->insn;
2057                 wmb();
2058                 __asm__ __volatile__("flush     %0"
2059                                      : /* no outputs */
2060                                      : "r" (addr));
2061
2062                 p++;
2063         }
2064 }
2065
2066 /* Don't mark as init, we give this to the Hypervisor.  */
2067 #ifndef CONFIG_DEBUG_PAGEALLOC
2068 #define NUM_KTSB_DESCR  2
2069 #else
2070 #define NUM_KTSB_DESCR  1
2071 #endif
2072 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
2073
2074 /* The swapper TSBs are loaded with a base sequence of:
2075  *
2076  *      sethi   %uhi(SYMBOL), REG1
2077  *      sethi   %hi(SYMBOL), REG2
2078  *      or      REG1, %ulo(SYMBOL), REG1
2079  *      or      REG2, %lo(SYMBOL), REG2
2080  *      sllx    REG1, 32, REG1
2081  *      or      REG1, REG2, REG1
2082  *
2083  * When we use physical addressing for the TSB accesses, we patch the
2084  * first four instructions in the above sequence.
2085  */
2086
2087 static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa)
2088 {
2089         unsigned long high_bits, low_bits;
2090
2091         high_bits = (pa >> 32) & 0xffffffff;
2092         low_bits = (pa >> 0) & 0xffffffff;
2093
2094         while (start < end) {
2095                 unsigned int *ia = (unsigned int *)(unsigned long)*start;
2096
2097                 ia[0] = (ia[0] & ~0x3fffff) | (high_bits >> 10);
2098                 __asm__ __volatile__("flush     %0" : : "r" (ia));
2099
2100                 ia[1] = (ia[1] & ~0x3fffff) | (low_bits >> 10);
2101                 __asm__ __volatile__("flush     %0" : : "r" (ia + 1));
2102
2103                 ia[2] = (ia[2] & ~0x1fff) | (high_bits & 0x3ff);
2104                 __asm__ __volatile__("flush     %0" : : "r" (ia + 2));
2105
2106                 ia[3] = (ia[3] & ~0x1fff) | (low_bits & 0x3ff);
2107                 __asm__ __volatile__("flush     %0" : : "r" (ia + 3));
2108
2109                 start++;
2110         }
2111 }
2112
2113 static void ktsb_phys_patch(void)
2114 {
2115         extern unsigned int __swapper_tsb_phys_patch;
2116         extern unsigned int __swapper_tsb_phys_patch_end;
2117         unsigned long ktsb_pa;
2118
2119         ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
2120         patch_one_ktsb_phys(&__swapper_tsb_phys_patch,
2121                             &__swapper_tsb_phys_patch_end, ktsb_pa);
2122 #ifndef CONFIG_DEBUG_PAGEALLOC
2123         {
2124         extern unsigned int __swapper_4m_tsb_phys_patch;
2125         extern unsigned int __swapper_4m_tsb_phys_patch_end;
2126         ktsb_pa = (kern_base +
2127                    ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
2128         patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch,
2129                             &__swapper_4m_tsb_phys_patch_end, ktsb_pa);
2130         }
2131 #endif
2132 }
2133
2134 static void __init sun4v_ktsb_init(void)
2135 {
2136         unsigned long ktsb_pa;
2137
2138         /* First KTSB for PAGE_SIZE mappings.  */
2139         ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
2140
2141         switch (PAGE_SIZE) {
2142         case 8 * 1024:
2143         default:
2144                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
2145                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
2146                 break;
2147
2148         case 64 * 1024:
2149                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
2150                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
2151                 break;
2152
2153         case 512 * 1024:
2154                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
2155                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
2156                 break;
2157
2158         case 4 * 1024 * 1024:
2159                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
2160                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
2161                 break;
2162         }
2163
2164         ktsb_descr[0].assoc = 1;
2165         ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
2166         ktsb_descr[0].ctx_idx = 0;
2167         ktsb_descr[0].tsb_base = ktsb_pa;
2168         ktsb_descr[0].resv = 0;
2169
2170 #ifndef CONFIG_DEBUG_PAGEALLOC
2171         /* Second KTSB for 4MB/256MB/2GB/16GB mappings.  */
2172         ktsb_pa = (kern_base +
2173                    ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
2174
2175         ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
2176         ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB |
2177                                     HV_PGSZ_MASK_256MB |
2178                                     HV_PGSZ_MASK_2GB |
2179                                     HV_PGSZ_MASK_16GB) &
2180                                    cpu_pgsz_mask);
2181         ktsb_descr[1].assoc = 1;
2182         ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
2183         ktsb_descr[1].ctx_idx = 0;
2184         ktsb_descr[1].tsb_base = ktsb_pa;
2185         ktsb_descr[1].resv = 0;
2186 #endif
2187 }
2188
2189 void sun4v_ktsb_register(void)
2190 {
2191         unsigned long pa, ret;
2192
2193         pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
2194
2195         ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
2196         if (ret != 0) {
2197                 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
2198                             "errors with %lx\n", pa, ret);
2199                 prom_halt();
2200         }
2201 }
2202
2203 static void __init sun4u_linear_pte_xor_finalize(void)
2204 {
2205 #ifndef CONFIG_DEBUG_PAGEALLOC
2206         /* This is where we would add Panther support for
2207          * 32MB and 256MB pages.
2208          */
2209 #endif
2210 }
2211
2212 static void __init sun4v_linear_pte_xor_finalize(void)
2213 {
2214         unsigned long pagecv_flag;
2215
2216         /* Bit 9 of TTE is no longer CV bit on M7 processor and it instead
2217          * enables MCD error. Do not set bit 9 on M7 processor.
2218          */
2219         switch (sun4v_chip_type) {
2220         case SUN4V_CHIP_SPARC_M7:
2221         case SUN4V_CHIP_SPARC_M8:
2222         case SUN4V_CHIP_SPARC_SN:
2223                 pagecv_flag = 0x00;
2224                 break;
2225         default:
2226                 pagecv_flag = _PAGE_CV_4V;
2227                 break;
2228         }
2229 #ifndef CONFIG_DEBUG_PAGEALLOC
2230         if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) {
2231                 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
2232                         PAGE_OFFSET;
2233                 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | pagecv_flag |
2234                                            _PAGE_P_4V | _PAGE_W_4V);
2235         } else {
2236                 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
2237         }
2238
2239         if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) {
2240                 kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^
2241                         PAGE_OFFSET;
2242                 kern_linear_pte_xor[2] |= (_PAGE_CP_4V | pagecv_flag |
2243                                            _PAGE_P_4V | _PAGE_W_4V);
2244         } else {
2245                 kern_linear_pte_xor[2] = kern_linear_pte_xor[1];
2246         }
2247
2248         if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) {
2249                 kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^
2250                         PAGE_OFFSET;
2251                 kern_linear_pte_xor[3] |= (_PAGE_CP_4V | pagecv_flag |
2252                                            _PAGE_P_4V | _PAGE_W_4V);
2253         } else {
2254                 kern_linear_pte_xor[3] = kern_linear_pte_xor[2];
2255         }
2256 #endif
2257 }
2258
2259 /* paging_init() sets up the page tables */
2260
2261 static unsigned long last_valid_pfn;
2262
2263 static void sun4u_pgprot_init(void);
2264 static void sun4v_pgprot_init(void);
2265
2266 #define _PAGE_CACHE_4U  (_PAGE_CP_4U | _PAGE_CV_4U)
2267 #define _PAGE_CACHE_4V  (_PAGE_CP_4V | _PAGE_CV_4V)
2268 #define __DIRTY_BITS_4U  (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2269 #define __DIRTY_BITS_4V  (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2270 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2271 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2272
2273 /* We need to exclude reserved regions. This exclusion will include
2274  * vmlinux and initrd. To be more precise the initrd size could be used to
2275  * compute a new lower limit because it is freed later during initialization.
2276  */
2277 static void __init reduce_memory(phys_addr_t limit_ram)
2278 {
2279         limit_ram += memblock_reserved_size();
2280         memblock_enforce_memory_limit(limit_ram);
2281 }
2282
2283 void __init paging_init(void)
2284 {
2285         unsigned long end_pfn, shift, phys_base;
2286         unsigned long real_end, i;
2287
2288         setup_page_offset();
2289
2290         /* These build time checkes make sure that the dcache_dirty_cpu()
2291          * page->flags usage will work.
2292          *
2293          * When a page gets marked as dcache-dirty, we store the
2294          * cpu number starting at bit 32 in the page->flags.  Also,
2295          * functions like clear_dcache_dirty_cpu use the cpu mask
2296          * in 13-bit signed-immediate instruction fields.
2297          */
2298
2299         /*
2300          * Page flags must not reach into upper 32 bits that are used
2301          * for the cpu number
2302          */
2303         BUILD_BUG_ON(NR_PAGEFLAGS > 32);
2304
2305         /*
2306          * The bit fields placed in the high range must not reach below
2307          * the 32 bit boundary. Otherwise we cannot place the cpu field
2308          * at the 32 bit boundary.
2309          */
2310         BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
2311                 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
2312
2313         BUILD_BUG_ON(NR_CPUS > 4096);
2314
2315         kern_base = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
2316         kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
2317
2318         /* Invalidate both kernel TSBs.  */
2319         memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
2320 #ifndef CONFIG_DEBUG_PAGEALLOC
2321         memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2322 #endif
2323
2324         /* TTE.cv bit on sparc v9 occupies the same position as TTE.mcde
2325          * bit on M7 processor. This is a conflicting usage of the same
2326          * bit. Enabling TTE.cv on M7 would turn on Memory Corruption
2327          * Detection error on all pages and this will lead to problems
2328          * later. Kernel does not run with MCD enabled and hence rest
2329          * of the required steps to fully configure memory corruption
2330          * detection are not taken. We need to ensure TTE.mcde is not
2331          * set on M7 processor. Compute the value of cacheability
2332          * flag for use later taking this into consideration.
2333          */
2334         switch (sun4v_chip_type) {
2335         case SUN4V_CHIP_SPARC_M7:
2336         case SUN4V_CHIP_SPARC_M8:
2337         case SUN4V_CHIP_SPARC_SN:
2338                 page_cache4v_flag = _PAGE_CP_4V;
2339                 break;
2340         default:
2341                 page_cache4v_flag = _PAGE_CACHE_4V;
2342                 break;
2343         }
2344
2345         if (tlb_type == hypervisor)
2346                 sun4v_pgprot_init();
2347         else
2348                 sun4u_pgprot_init();
2349
2350         if (tlb_type == cheetah_plus ||
2351             tlb_type == hypervisor) {
2352                 tsb_phys_patch();
2353                 ktsb_phys_patch();
2354         }
2355
2356         if (tlb_type == hypervisor)
2357                 sun4v_patch_tlb_handlers();
2358
2359         /* Find available physical memory...
2360          *
2361          * Read it twice in order to work around a bug in openfirmware.
2362          * The call to grab this table itself can cause openfirmware to
2363          * allocate memory, which in turn can take away some space from
2364          * the list of available memory.  Reading it twice makes sure
2365          * we really do get the final value.
2366          */
2367         read_obp_translations();
2368         read_obp_memory("reg", &pall[0], &pall_ents);
2369         read_obp_memory("available", &pavail[0], &pavail_ents);
2370         read_obp_memory("available", &pavail[0], &pavail_ents);
2371
2372         phys_base = 0xffffffffffffffffUL;
2373         for (i = 0; i < pavail_ents; i++) {
2374                 phys_base = min(phys_base, pavail[i].phys_addr);
2375                 memblock_add(pavail[i].phys_addr, pavail[i].reg_size);
2376         }
2377
2378         memblock_reserve(kern_base, kern_size);
2379
2380         find_ramdisk(phys_base);
2381
2382         if (cmdline_memory_size)
2383                 reduce_memory(cmdline_memory_size);
2384
2385         memblock_allow_resize();
2386         memblock_dump_all();
2387
2388         set_bit(0, mmu_context_bmap);
2389
2390         shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
2391
2392         real_end = (unsigned long)_end;
2393         num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << ILOG2_4MB);
2394         printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
2395                num_kernel_image_mappings);
2396
2397         /* Set kernel pgd to upper alias so physical page computations
2398          * work.
2399          */
2400         init_mm.pgd += ((shift) / (sizeof(pgd_t)));
2401
2402         memset(swapper_pg_dir, 0, sizeof(swapper_pg_dir));
2403
2404         inherit_prom_mappings();
2405
2406         /* Ok, we can use our TLB miss and window trap handlers safely.  */
2407         setup_tba();
2408
2409         __flush_tlb_all();
2410
2411         prom_build_devicetree();
2412         of_populate_present_mask();
2413 #ifndef CONFIG_SMP
2414         of_fill_in_cpu_data();
2415 #endif
2416
2417         if (tlb_type == hypervisor) {
2418                 sun4v_mdesc_init();
2419                 mdesc_populate_present_mask(cpu_all_mask);
2420 #ifndef CONFIG_SMP
2421                 mdesc_fill_in_cpu_data(cpu_all_mask);
2422 #endif
2423                 mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask);
2424
2425                 sun4v_linear_pte_xor_finalize();
2426
2427                 sun4v_ktsb_init();
2428                 sun4v_ktsb_register();
2429         } else {
2430                 unsigned long impl, ver;
2431
2432                 cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K |
2433                                  HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB);
2434
2435                 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
2436                 impl = ((ver >> 32) & 0xffff);
2437                 if (impl == PANTHER_IMPL)
2438                         cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB |
2439                                           HV_PGSZ_MASK_256MB);
2440
2441                 sun4u_linear_pte_xor_finalize();
2442         }
2443
2444         /* Flush the TLBs and the 4M TSB so that the updated linear
2445          * pte XOR settings are realized for all mappings.
2446          */
2447         __flush_tlb_all();
2448 #ifndef CONFIG_DEBUG_PAGEALLOC
2449         memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2450 #endif
2451         __flush_tlb_all();
2452
2453         /* Setup bootmem... */
2454         last_valid_pfn = end_pfn = bootmem_init(phys_base);
2455
2456         kernel_physical_mapping_init();
2457
2458         {
2459                 unsigned long max_zone_pfns[MAX_NR_ZONES];
2460
2461                 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
2462
2463                 max_zone_pfns[ZONE_NORMAL] = end_pfn;
2464
2465                 free_area_init(max_zone_pfns);
2466         }
2467
2468         printk("Booting Linux...\n");
2469 }
2470
2471 int page_in_phys_avail(unsigned long paddr)
2472 {
2473         int i;
2474
2475         paddr &= PAGE_MASK;
2476
2477         for (i = 0; i < pavail_ents; i++) {
2478                 unsigned long start, end;
2479
2480                 start = pavail[i].phys_addr;
2481                 end = start + pavail[i].reg_size;
2482
2483                 if (paddr >= start && paddr < end)
2484                         return 1;
2485         }
2486         if (paddr >= kern_base && paddr < (kern_base + kern_size))
2487                 return 1;
2488 #ifdef CONFIG_BLK_DEV_INITRD
2489         if (paddr >= __pa(initrd_start) &&
2490             paddr < __pa(PAGE_ALIGN(initrd_end)))
2491                 return 1;
2492 #endif
2493
2494         return 0;
2495 }
2496
2497 static void __init register_page_bootmem_info(void)
2498 {
2499 #ifdef CONFIG_NEED_MULTIPLE_NODES
2500         int i;
2501
2502         for_each_online_node(i)
2503                 if (NODE_DATA(i)->node_spanned_pages)
2504                         register_page_bootmem_info_node(NODE_DATA(i));
2505 #endif
2506 }
2507 void __init mem_init(void)
2508 {
2509         high_memory = __va(last_valid_pfn << PAGE_SHIFT);
2510
2511         memblock_free_all();
2512
2513         /*
2514          * Must be done after boot memory is put on freelist, because here we
2515          * might set fields in deferred struct pages that have not yet been
2516          * initialized, and memblock_free_all() initializes all the reserved
2517          * deferred pages for us.
2518          */
2519         register_page_bootmem_info();
2520
2521         /*
2522          * Set up the zero page, mark it reserved, so that page count
2523          * is not manipulated when freeing the page from user ptes.
2524          */
2525         mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
2526         if (mem_map_zero == NULL) {
2527                 prom_printf("paging_init: Cannot alloc zero page.\n");
2528                 prom_halt();
2529         }
2530         mark_page_reserved(mem_map_zero);
2531
2532         mem_init_print_info(NULL);
2533
2534         if (tlb_type == cheetah || tlb_type == cheetah_plus)
2535                 cheetah_ecache_flush_init();
2536 }
2537
2538 void free_initmem(void)
2539 {
2540         unsigned long addr, initend;
2541         int do_free = 1;
2542
2543         /* If the physical memory maps were trimmed by kernel command
2544          * line options, don't even try freeing this initmem stuff up.
2545          * The kernel image could have been in the trimmed out region
2546          * and if so the freeing below will free invalid page structs.
2547          */
2548         if (cmdline_memory_size)
2549                 do_free = 0;
2550
2551         /*
2552          * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
2553          */
2554         addr = PAGE_ALIGN((unsigned long)(__init_begin));
2555         initend = (unsigned long)(__init_end) & PAGE_MASK;
2556         for (; addr < initend; addr += PAGE_SIZE) {
2557                 unsigned long page;
2558
2559                 page = (addr +
2560                         ((unsigned long) __va(kern_base)) -
2561                         ((unsigned long) KERNBASE));
2562                 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
2563
2564                 if (do_free)
2565                         free_reserved_page(virt_to_page(page));
2566         }
2567 }
2568
2569 pgprot_t PAGE_KERNEL __read_mostly;
2570 EXPORT_SYMBOL(PAGE_KERNEL);
2571
2572 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2573 pgprot_t PAGE_COPY __read_mostly;
2574
2575 pgprot_t PAGE_SHARED __read_mostly;
2576 EXPORT_SYMBOL(PAGE_SHARED);
2577
2578 unsigned long pg_iobits __read_mostly;
2579
2580 unsigned long _PAGE_IE __read_mostly;
2581 EXPORT_SYMBOL(_PAGE_IE);
2582
2583 unsigned long _PAGE_E __read_mostly;
2584 EXPORT_SYMBOL(_PAGE_E);
2585
2586 unsigned long _PAGE_CACHE __read_mostly;
2587 EXPORT_SYMBOL(_PAGE_CACHE);
2588
2589 #ifdef CONFIG_SPARSEMEM_VMEMMAP
2590 int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend,
2591                                int node, struct vmem_altmap *altmap)
2592 {
2593         unsigned long pte_base;
2594
2595         pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2596                     _PAGE_CP_4U | _PAGE_CV_4U |
2597                     _PAGE_P_4U | _PAGE_W_4U);
2598         if (tlb_type == hypervisor)
2599                 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2600                             page_cache4v_flag | _PAGE_P_4V | _PAGE_W_4V);
2601
2602         pte_base |= _PAGE_PMD_HUGE;
2603
2604         vstart = vstart & PMD_MASK;
2605         vend = ALIGN(vend, PMD_SIZE);
2606         for (; vstart < vend; vstart += PMD_SIZE) {
2607                 pgd_t *pgd = vmemmap_pgd_populate(vstart, node);
2608                 unsigned long pte;
2609                 p4d_t *p4d;
2610                 pud_t *pud;
2611                 pmd_t *pmd;
2612
2613                 if (!pgd)
2614                         return -ENOMEM;
2615
2616                 p4d = vmemmap_p4d_populate(pgd, vstart, node);
2617                 if (!p4d)
2618                         return -ENOMEM;
2619
2620                 pud = vmemmap_pud_populate(p4d, vstart, node);
2621                 if (!pud)
2622                         return -ENOMEM;
2623
2624                 pmd = pmd_offset(pud, vstart);
2625                 pte = pmd_val(*pmd);
2626                 if (!(pte & _PAGE_VALID)) {
2627                         void *block = vmemmap_alloc_block(PMD_SIZE, node);
2628
2629                         if (!block)
2630                                 return -ENOMEM;
2631
2632                         pmd_val(*pmd) = pte_base | __pa(block);
2633                 }
2634         }
2635
2636         return 0;
2637 }
2638
2639 void vmemmap_free(unsigned long start, unsigned long end,
2640                 struct vmem_altmap *altmap)
2641 {
2642 }
2643 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
2644
2645 static void prot_init_common(unsigned long page_none,
2646                              unsigned long page_shared,
2647                              unsigned long page_copy,
2648                              unsigned long page_readonly,
2649                              unsigned long page_exec_bit)
2650 {
2651         PAGE_COPY = __pgprot(page_copy);
2652         PAGE_SHARED = __pgprot(page_shared);
2653
2654         protection_map[0x0] = __pgprot(page_none);
2655         protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2656         protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2657         protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2658         protection_map[0x4] = __pgprot(page_readonly);
2659         protection_map[0x5] = __pgprot(page_readonly);
2660         protection_map[0x6] = __pgprot(page_copy);
2661         protection_map[0x7] = __pgprot(page_copy);
2662         protection_map[0x8] = __pgprot(page_none);
2663         protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2664         protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2665         protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2666         protection_map[0xc] = __pgprot(page_readonly);
2667         protection_map[0xd] = __pgprot(page_readonly);
2668         protection_map[0xe] = __pgprot(page_shared);
2669         protection_map[0xf] = __pgprot(page_shared);
2670 }
2671
2672 static void __init sun4u_pgprot_init(void)
2673 {
2674         unsigned long page_none, page_shared, page_copy, page_readonly;
2675         unsigned long page_exec_bit;
2676         int i;
2677
2678         PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2679                                 _PAGE_CACHE_4U | _PAGE_P_4U |
2680                                 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2681                                 _PAGE_EXEC_4U);
2682         PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2683                                        _PAGE_CACHE_4U | _PAGE_P_4U |
2684                                        __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2685                                        _PAGE_EXEC_4U | _PAGE_L_4U);
2686
2687         _PAGE_IE = _PAGE_IE_4U;
2688         _PAGE_E = _PAGE_E_4U;
2689         _PAGE_CACHE = _PAGE_CACHE_4U;
2690
2691         pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2692                      __ACCESS_BITS_4U | _PAGE_E_4U);
2693
2694 #ifdef CONFIG_DEBUG_PAGEALLOC
2695         kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2696 #else
2697         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
2698                 PAGE_OFFSET;
2699 #endif
2700         kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2701                                    _PAGE_P_4U | _PAGE_W_4U);
2702
2703         for (i = 1; i < 4; i++)
2704                 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2705
2706         _PAGE_ALL_SZ_BITS =  (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2707                               _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2708                               _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2709
2710
2711         page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2712         page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2713                        __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2714         page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2715                        __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2716         page_readonly   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2717                            __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2718
2719         page_exec_bit = _PAGE_EXEC_4U;
2720
2721         prot_init_common(page_none, page_shared, page_copy, page_readonly,
2722                          page_exec_bit);
2723 }
2724
2725 static void __init sun4v_pgprot_init(void)
2726 {
2727         unsigned long page_none, page_shared, page_copy, page_readonly;
2728         unsigned long page_exec_bit;
2729         int i;
2730
2731         PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2732                                 page_cache4v_flag | _PAGE_P_4V |
2733                                 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2734                                 _PAGE_EXEC_4V);
2735         PAGE_KERNEL_LOCKED = PAGE_KERNEL;
2736
2737         _PAGE_IE = _PAGE_IE_4V;
2738         _PAGE_E = _PAGE_E_4V;
2739         _PAGE_CACHE = page_cache4v_flag;
2740
2741 #ifdef CONFIG_DEBUG_PAGEALLOC
2742         kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2743 #else
2744         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2745                 PAGE_OFFSET;
2746 #endif
2747         kern_linear_pte_xor[0] |= (page_cache4v_flag | _PAGE_P_4V |
2748                                    _PAGE_W_4V);
2749
2750         for (i = 1; i < 4; i++)
2751                 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2752
2753         pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2754                      __ACCESS_BITS_4V | _PAGE_E_4V);
2755
2756         _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2757                              _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2758                              _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2759                              _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2760
2761         page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | page_cache4v_flag;
2762         page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2763                        __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2764         page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2765                        __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2766         page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2767                          __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2768
2769         page_exec_bit = _PAGE_EXEC_4V;
2770
2771         prot_init_common(page_none, page_shared, page_copy, page_readonly,
2772                          page_exec_bit);
2773 }
2774
2775 unsigned long pte_sz_bits(unsigned long sz)
2776 {
2777         if (tlb_type == hypervisor) {
2778                 switch (sz) {
2779                 case 8 * 1024:
2780                 default:
2781                         return _PAGE_SZ8K_4V;
2782                 case 64 * 1024:
2783                         return _PAGE_SZ64K_4V;
2784                 case 512 * 1024:
2785                         return _PAGE_SZ512K_4V;
2786                 case 4 * 1024 * 1024:
2787                         return _PAGE_SZ4MB_4V;
2788                 }
2789         } else {
2790                 switch (sz) {
2791                 case 8 * 1024:
2792                 default:
2793                         return _PAGE_SZ8K_4U;
2794                 case 64 * 1024:
2795                         return _PAGE_SZ64K_4U;
2796                 case 512 * 1024:
2797                         return _PAGE_SZ512K_4U;
2798                 case 4 * 1024 * 1024:
2799                         return _PAGE_SZ4MB_4U;
2800                 }
2801         }
2802 }
2803
2804 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2805 {
2806         pte_t pte;
2807
2808         pte_val(pte)  = page | pgprot_val(pgprot_noncached(prot));
2809         pte_val(pte) |= (((unsigned long)space) << 32);
2810         pte_val(pte) |= pte_sz_bits(page_size);
2811
2812         return pte;
2813 }
2814
2815 static unsigned long kern_large_tte(unsigned long paddr)
2816 {
2817         unsigned long val;
2818
2819         val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2820                _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2821                _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2822         if (tlb_type == hypervisor)
2823                 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2824                        page_cache4v_flag | _PAGE_P_4V |
2825                        _PAGE_EXEC_4V | _PAGE_W_4V);
2826
2827         return val | paddr;
2828 }
2829
2830 /* If not locked, zap it. */
2831 void __flush_tlb_all(void)
2832 {
2833         unsigned long pstate;
2834         int i;
2835
2836         __asm__ __volatile__("flushw\n\t"
2837                              "rdpr      %%pstate, %0\n\t"
2838                              "wrpr      %0, %1, %%pstate"
2839                              : "=r" (pstate)
2840                              : "i" (PSTATE_IE));
2841         if (tlb_type == hypervisor) {
2842                 sun4v_mmu_demap_all();
2843         } else if (tlb_type == spitfire) {
2844                 for (i = 0; i < 64; i++) {
2845                         /* Spitfire Errata #32 workaround */
2846                         /* NOTE: Always runs on spitfire, so no
2847                          *       cheetah+ page size encodings.
2848                          */
2849                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
2850                                              "flush     %%g6"
2851                                              : /* No outputs */
2852                                              : "r" (0),
2853                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2854
2855                         if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2856                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2857                                                      "membar #Sync"
2858                                                      : /* no outputs */
2859                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2860                                 spitfire_put_dtlb_data(i, 0x0UL);
2861                         }
2862
2863                         /* Spitfire Errata #32 workaround */
2864                         /* NOTE: Always runs on spitfire, so no
2865                          *       cheetah+ page size encodings.
2866                          */
2867                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
2868                                              "flush     %%g6"
2869                                              : /* No outputs */
2870                                              : "r" (0),
2871                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2872
2873                         if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2874                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2875                                                      "membar #Sync"
2876                                                      : /* no outputs */
2877                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2878                                 spitfire_put_itlb_data(i, 0x0UL);
2879                         }
2880                 }
2881         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2882                 cheetah_flush_dtlb_all();
2883                 cheetah_flush_itlb_all();
2884         }
2885         __asm__ __volatile__("wrpr      %0, 0, %%pstate"
2886                              : : "r" (pstate));
2887 }
2888
2889 pte_t *pte_alloc_one_kernel(struct mm_struct *mm)
2890 {
2891         struct page *page = alloc_page(GFP_KERNEL | __GFP_ZERO);
2892         pte_t *pte = NULL;
2893
2894         if (page)
2895                 pte = (pte_t *) page_address(page);
2896
2897         return pte;
2898 }
2899
2900 pgtable_t pte_alloc_one(struct mm_struct *mm)
2901 {
2902         struct page *page = alloc_page(GFP_KERNEL | __GFP_ZERO);
2903         if (!page)
2904                 return NULL;
2905         if (!pgtable_pte_page_ctor(page)) {
2906                 free_unref_page(page);
2907                 return NULL;
2908         }
2909         return (pte_t *) page_address(page);
2910 }
2911
2912 void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
2913 {
2914         free_page((unsigned long)pte);
2915 }
2916
2917 static void __pte_free(pgtable_t pte)
2918 {
2919         struct page *page = virt_to_page(pte);
2920
2921         pgtable_pte_page_dtor(page);
2922         __free_page(page);
2923 }
2924
2925 void pte_free(struct mm_struct *mm, pgtable_t pte)
2926 {
2927         __pte_free(pte);
2928 }
2929
2930 void pgtable_free(void *table, bool is_page)
2931 {
2932         if (is_page)
2933                 __pte_free(table);
2934         else
2935                 kmem_cache_free(pgtable_cache, table);
2936 }
2937
2938 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
2939 void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
2940                           pmd_t *pmd)
2941 {
2942         unsigned long pte, flags;
2943         struct mm_struct *mm;
2944         pmd_t entry = *pmd;
2945
2946         if (!pmd_large(entry) || !pmd_young(entry))
2947                 return;
2948
2949         pte = pmd_val(entry);
2950
2951         /* Don't insert a non-valid PMD into the TSB, we'll deadlock.  */
2952         if (!(pte & _PAGE_VALID))
2953                 return;
2954
2955         /* We are fabricating 8MB pages using 4MB real hw pages.  */
2956         pte |= (addr & (1UL << REAL_HPAGE_SHIFT));
2957
2958         mm = vma->vm_mm;
2959
2960         spin_lock_irqsave(&mm->context.lock, flags);
2961
2962         if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL)
2963                 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT,
2964                                         addr, pte);
2965
2966         spin_unlock_irqrestore(&mm->context.lock, flags);
2967 }
2968 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
2969
2970 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
2971 static void context_reload(void *__data)
2972 {
2973         struct mm_struct *mm = __data;
2974
2975         if (mm == current->mm)
2976                 load_secondary_context(mm);
2977 }
2978
2979 void hugetlb_setup(struct pt_regs *regs)
2980 {
2981         struct mm_struct *mm = current->mm;
2982         struct tsb_config *tp;
2983
2984         if (faulthandler_disabled() || !mm) {
2985                 const struct exception_table_entry *entry;
2986
2987                 entry = search_exception_tables(regs->tpc);
2988                 if (entry) {
2989                         regs->tpc = entry->fixup;
2990                         regs->tnpc = regs->tpc + 4;
2991                         return;
2992                 }
2993                 pr_alert("Unexpected HugeTLB setup in atomic context.\n");
2994                 die_if_kernel("HugeTSB in atomic", regs);
2995         }
2996
2997         tp = &mm->context.tsb_block[MM_TSB_HUGE];
2998         if (likely(tp->tsb == NULL))
2999                 tsb_grow(mm, MM_TSB_HUGE, 0);
3000
3001         tsb_context_switch(mm);
3002         smp_tsb_sync(mm);
3003
3004         /* On UltraSPARC-III+ and later, configure the second half of
3005          * the Data-TLB for huge pages.
3006          */
3007         if (tlb_type == cheetah_plus) {
3008                 bool need_context_reload = false;
3009                 unsigned long ctx;
3010
3011                 spin_lock_irq(&ctx_alloc_lock);
3012                 ctx = mm->context.sparc64_ctx_val;
3013                 ctx &= ~CTX_PGSZ_MASK;
3014                 ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT;
3015                 ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT;
3016
3017                 if (ctx != mm->context.sparc64_ctx_val) {
3018                         /* When changing the page size fields, we
3019                          * must perform a context flush so that no
3020                          * stale entries match.  This flush must
3021                          * occur with the original context register
3022                          * settings.
3023                          */
3024                         do_flush_tlb_mm(mm);
3025
3026                         /* Reload the context register of all processors
3027                          * also executing in this address space.
3028                          */
3029                         mm->context.sparc64_ctx_val = ctx;
3030                         need_context_reload = true;
3031                 }
3032                 spin_unlock_irq(&ctx_alloc_lock);
3033
3034                 if (need_context_reload)
3035                         on_each_cpu(context_reload, mm, 0);
3036         }
3037 }
3038 #endif
3039
3040 static struct resource code_resource = {
3041         .name   = "Kernel code",
3042         .flags  = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
3043 };
3044
3045 static struct resource data_resource = {
3046         .name   = "Kernel data",
3047         .flags  = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
3048 };
3049
3050 static struct resource bss_resource = {
3051         .name   = "Kernel bss",
3052         .flags  = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
3053 };
3054
3055 static inline resource_size_t compute_kern_paddr(void *addr)
3056 {
3057         return (resource_size_t) (addr - KERNBASE + kern_base);
3058 }
3059
3060 static void __init kernel_lds_init(void)
3061 {
3062         code_resource.start = compute_kern_paddr(_text);
3063         code_resource.end   = compute_kern_paddr(_etext - 1);
3064         data_resource.start = compute_kern_paddr(_etext);
3065         data_resource.end   = compute_kern_paddr(_edata - 1);
3066         bss_resource.start  = compute_kern_paddr(__bss_start);
3067         bss_resource.end    = compute_kern_paddr(_end - 1);
3068 }
3069
3070 static int __init report_memory(void)
3071 {
3072         int i;
3073         struct resource *res;
3074
3075         kernel_lds_init();
3076
3077         for (i = 0; i < pavail_ents; i++) {
3078                 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
3079
3080                 if (!res) {
3081                         pr_warn("Failed to allocate source.\n");
3082                         break;
3083                 }
3084
3085                 res->name = "System RAM";
3086                 res->start = pavail[i].phys_addr;
3087                 res->end = pavail[i].phys_addr + pavail[i].reg_size - 1;
3088                 res->flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM;
3089
3090                 if (insert_resource(&iomem_resource, res) < 0) {
3091                         pr_warn("Resource insertion failed.\n");
3092                         break;
3093                 }
3094
3095                 insert_resource(res, &code_resource);
3096                 insert_resource(res, &data_resource);
3097                 insert_resource(res, &bss_resource);
3098         }
3099
3100         return 0;
3101 }
3102 arch_initcall(report_memory);
3103
3104 #ifdef CONFIG_SMP
3105 #define do_flush_tlb_kernel_range       smp_flush_tlb_kernel_range
3106 #else
3107 #define do_flush_tlb_kernel_range       __flush_tlb_kernel_range
3108 #endif
3109
3110 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
3111 {
3112         if (start < HI_OBP_ADDRESS && end > LOW_OBP_ADDRESS) {
3113                 if (start < LOW_OBP_ADDRESS) {
3114                         flush_tsb_kernel_range(start, LOW_OBP_ADDRESS);
3115                         do_flush_tlb_kernel_range(start, LOW_OBP_ADDRESS);
3116                 }
3117                 if (end > HI_OBP_ADDRESS) {
3118                         flush_tsb_kernel_range(HI_OBP_ADDRESS, end);
3119                         do_flush_tlb_kernel_range(HI_OBP_ADDRESS, end);
3120                 }
3121         } else {
3122                 flush_tsb_kernel_range(start, end);
3123                 do_flush_tlb_kernel_range(start, end);
3124         }
3125 }
3126
3127 void copy_user_highpage(struct page *to, struct page *from,
3128         unsigned long vaddr, struct vm_area_struct *vma)
3129 {
3130         char *vfrom, *vto;
3131
3132         vfrom = kmap_atomic(from);
3133         vto = kmap_atomic(to);
3134         copy_user_page(vto, vfrom, vaddr, to);
3135         kunmap_atomic(vto);
3136         kunmap_atomic(vfrom);
3137
3138         /* If this page has ADI enabled, copy over any ADI tags
3139          * as well
3140          */
3141         if (vma->vm_flags & VM_SPARC_ADI) {
3142                 unsigned long pfrom, pto, i, adi_tag;
3143
3144                 pfrom = page_to_phys(from);
3145                 pto = page_to_phys(to);
3146
3147                 for (i = pfrom; i < (pfrom + PAGE_SIZE); i += adi_blksize()) {
3148                         asm volatile("ldxa [%1] %2, %0\n\t"
3149                                         : "=r" (adi_tag)
3150                                         :  "r" (i), "i" (ASI_MCD_REAL));
3151                         asm volatile("stxa %0, [%1] %2\n\t"
3152                                         :
3153                                         : "r" (adi_tag), "r" (pto),
3154                                           "i" (ASI_MCD_REAL));
3155                         pto += adi_blksize();
3156                 }
3157                 asm volatile("membar #Sync\n\t");
3158         }
3159 }
3160 EXPORT_SYMBOL(copy_user_highpage);
3161
3162 void copy_highpage(struct page *to, struct page *from)
3163 {
3164         char *vfrom, *vto;
3165
3166         vfrom = kmap_atomic(from);
3167         vto = kmap_atomic(to);
3168         copy_page(vto, vfrom);
3169         kunmap_atomic(vto);
3170         kunmap_atomic(vfrom);
3171
3172         /* If this platform is ADI enabled, copy any ADI tags
3173          * as well
3174          */
3175         if (adi_capable()) {
3176                 unsigned long pfrom, pto, i, adi_tag;
3177
3178                 pfrom = page_to_phys(from);
3179                 pto = page_to_phys(to);
3180
3181                 for (i = pfrom; i < (pfrom + PAGE_SIZE); i += adi_blksize()) {
3182                         asm volatile("ldxa [%1] %2, %0\n\t"
3183                                         : "=r" (adi_tag)
3184                                         :  "r" (i), "i" (ASI_MCD_REAL));
3185                         asm volatile("stxa %0, [%1] %2\n\t"
3186                                         :
3187                                         : "r" (adi_tag), "r" (pto),
3188                                           "i" (ASI_MCD_REAL));
3189                         pto += adi_blksize();
3190                 }
3191                 asm volatile("membar #Sync\n\t");
3192         }
3193 }
3194 EXPORT_SYMBOL(copy_highpage);