1 /* smp.c: Sparc64 SMP support.
3 * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net)
6 #include <linux/export.h>
7 #include <linux/kernel.h>
8 #include <linux/sched.h>
10 #include <linux/pagemap.h>
11 #include <linux/threads.h>
12 #include <linux/smp.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/delay.h>
16 #include <linux/init.h>
17 #include <linux/spinlock.h>
19 #include <linux/seq_file.h>
20 #include <linux/cache.h>
21 #include <linux/jiffies.h>
22 #include <linux/profile.h>
23 #include <linux/bootmem.h>
24 #include <linux/vmalloc.h>
25 #include <linux/ftrace.h>
26 #include <linux/cpu.h>
27 #include <linux/slab.h>
30 #include <asm/ptrace.h>
31 #include <linux/atomic.h>
32 #include <asm/tlbflush.h>
33 #include <asm/mmu_context.h>
34 #include <asm/cpudata.h>
35 #include <asm/hvtramp.h>
37 #include <asm/timer.h>
40 #include <asm/irq_regs.h>
42 #include <asm/pgtable.h>
43 #include <asm/oplib.h>
44 #include <asm/uaccess.h>
45 #include <asm/starfire.h>
47 #include <asm/sections.h>
49 #include <asm/mdesc.h>
51 #include <asm/hypervisor.h>
56 int sparc64_multi_core __read_mostly;
58 DEFINE_PER_CPU(cpumask_t, cpu_sibling_map) = CPU_MASK_NONE;
59 cpumask_t cpu_core_map[NR_CPUS] __read_mostly =
60 { [0 ... NR_CPUS-1] = CPU_MASK_NONE };
62 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
63 EXPORT_SYMBOL(cpu_core_map);
65 static cpumask_t smp_commenced_mask;
67 void smp_info(struct seq_file *m)
71 seq_printf(m, "State:\n");
72 for_each_online_cpu(i)
73 seq_printf(m, "CPU%d:\t\tonline\n", i);
76 void smp_bogo(struct seq_file *m)
80 for_each_online_cpu(i)
82 "Cpu%dClkTck\t: %016lx\n",
83 i, cpu_data(i).clock_tick);
86 extern void setup_sparc64_timer(void);
88 static volatile unsigned long callin_flag = 0;
92 int cpuid = hard_smp_processor_id();
94 __local_per_cpu_offset = __per_cpu_offset(cpuid);
96 if (tlb_type == hypervisor)
97 sun4v_ktsb_register();
101 setup_sparc64_timer();
103 if (cheetah_pcache_forced_on)
104 cheetah_enable_pcache();
107 __asm__ __volatile__("membar #Sync\n\t"
108 "flush %%g6" : : : "memory");
110 /* Clear this or we will die instantly when we
111 * schedule back to this idler...
113 current_thread_info()->new_child = 0;
115 /* Attach to the address space of init_task. */
116 atomic_inc(&init_mm.mm_count);
117 current->active_mm = &init_mm;
119 /* inform the notifiers about the new cpu */
120 notify_cpu_starting(cpuid);
122 while (!cpumask_test_cpu(cpuid, &smp_commenced_mask))
125 set_cpu_online(cpuid, true);
127 /* idle thread is expected to have preempt disabled */
132 cpu_startup_entry(CPUHP_ONLINE);
137 printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
138 panic("SMP bolixed\n");
141 /* This tick register synchronization scheme is taken entirely from
142 * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit.
144 * The only change I've made is to rework it so that the master
145 * initiates the synchonization instead of the slave. -DaveM
149 #define SLAVE (SMP_CACHE_BYTES/sizeof(unsigned long))
151 #define NUM_ROUNDS 64 /* magic value */
152 #define NUM_ITERS 5 /* likewise */
154 static DEFINE_RAW_SPINLOCK(itc_sync_lock);
155 static unsigned long go[SLAVE + 1];
157 #define DEBUG_TICK_SYNC 0
159 static inline long get_delta (long *rt, long *master)
161 unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
162 unsigned long tcenter, t0, t1, tm;
165 for (i = 0; i < NUM_ITERS; i++) {
166 t0 = tick_ops->get_tick();
168 membar_safe("#StoreLoad");
169 while (!(tm = go[SLAVE]))
173 t1 = tick_ops->get_tick();
175 if (t1 - t0 < best_t1 - best_t0)
176 best_t0 = t0, best_t1 = t1, best_tm = tm;
179 *rt = best_t1 - best_t0;
180 *master = best_tm - best_t0;
182 /* average best_t0 and best_t1 without overflow: */
183 tcenter = (best_t0/2 + best_t1/2);
184 if (best_t0 % 2 + best_t1 % 2 == 2)
186 return tcenter - best_tm;
189 void smp_synchronize_tick_client(void)
191 long i, delta, adj, adjust_latency = 0, done = 0;
192 unsigned long flags, rt, master_time_stamp;
195 long rt; /* roundtrip time */
196 long master; /* master's timestamp */
197 long diff; /* difference between midpoint and master's timestamp */
198 long lat; /* estimate of itc adjustment latency */
207 local_irq_save(flags);
209 for (i = 0; i < NUM_ROUNDS; i++) {
210 delta = get_delta(&rt, &master_time_stamp);
212 done = 1; /* let's lock on to this... */
216 adjust_latency += -delta;
217 adj = -delta + adjust_latency/4;
221 tick_ops->add_tick(adj);
225 t[i].master = master_time_stamp;
227 t[i].lat = adjust_latency/4;
231 local_irq_restore(flags);
234 for (i = 0; i < NUM_ROUNDS; i++)
235 printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
236 t[i].rt, t[i].master, t[i].diff, t[i].lat);
239 printk(KERN_INFO "CPU %d: synchronized TICK with master CPU "
240 "(last diff %ld cycles, maxerr %lu cycles)\n",
241 smp_processor_id(), delta, rt);
244 static void smp_start_sync_tick_client(int cpu);
246 static void smp_synchronize_one_tick(int cpu)
248 unsigned long flags, i;
252 smp_start_sync_tick_client(cpu);
254 /* wait for client to be ready */
258 /* now let the client proceed into his loop */
260 membar_safe("#StoreLoad");
262 raw_spin_lock_irqsave(&itc_sync_lock, flags);
264 for (i = 0; i < NUM_ROUNDS*NUM_ITERS; i++) {
269 go[SLAVE] = tick_ops->get_tick();
270 membar_safe("#StoreLoad");
273 raw_spin_unlock_irqrestore(&itc_sync_lock, flags);
276 #if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
277 /* XXX Put this in some common place. XXX */
278 static unsigned long kimage_addr_to_ra(void *p)
280 unsigned long val = (unsigned long) p;
282 return kern_base + (val - KERNBASE);
285 static void ldom_startcpu_cpuid(unsigned int cpu, unsigned long thread_reg,
288 extern unsigned long sparc64_ttable_tl0;
289 extern unsigned long kern_locked_tte_data;
290 struct hvtramp_descr *hdesc;
291 unsigned long trampoline_ra;
292 struct trap_per_cpu *tb;
293 u64 tte_vaddr, tte_data;
294 unsigned long hv_err;
297 hdesc = kzalloc(sizeof(*hdesc) +
298 (sizeof(struct hvtramp_mapping) *
299 num_kernel_image_mappings - 1),
302 printk(KERN_ERR "ldom_startcpu_cpuid: Cannot allocate "
309 hdesc->num_mappings = num_kernel_image_mappings;
311 tb = &trap_block[cpu];
313 hdesc->fault_info_va = (unsigned long) &tb->fault_info;
314 hdesc->fault_info_pa = kimage_addr_to_ra(&tb->fault_info);
316 hdesc->thread_reg = thread_reg;
318 tte_vaddr = (unsigned long) KERNBASE;
319 tte_data = kern_locked_tte_data;
321 for (i = 0; i < hdesc->num_mappings; i++) {
322 hdesc->maps[i].vaddr = tte_vaddr;
323 hdesc->maps[i].tte = tte_data;
324 tte_vaddr += 0x400000;
325 tte_data += 0x400000;
328 trampoline_ra = kimage_addr_to_ra(hv_cpu_startup);
330 hv_err = sun4v_cpu_start(cpu, trampoline_ra,
331 kimage_addr_to_ra(&sparc64_ttable_tl0),
334 printk(KERN_ERR "ldom_startcpu_cpuid: sun4v_cpu_start() "
335 "gives error %lu\n", hv_err);
339 extern unsigned long sparc64_cpu_startup;
341 /* The OBP cpu startup callback truncates the 3rd arg cookie to
342 * 32-bits (I think) so to be safe we have it read the pointer
343 * contained here so we work on >4GB machines. -DaveM
345 static struct thread_info *cpu_new_thread = NULL;
347 static int smp_boot_one_cpu(unsigned int cpu, struct task_struct *idle)
349 unsigned long entry =
350 (unsigned long)(&sparc64_cpu_startup);
351 unsigned long cookie =
352 (unsigned long)(&cpu_new_thread);
357 cpu_new_thread = task_thread_info(idle);
359 if (tlb_type == hypervisor) {
360 #if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
361 if (ldom_domaining_enabled)
362 ldom_startcpu_cpuid(cpu,
363 (unsigned long) cpu_new_thread,
367 prom_startcpu_cpuid(cpu, entry, cookie);
369 struct device_node *dp = of_find_node_by_cpuid(cpu);
371 prom_startcpu(dp->phandle, entry, cookie);
374 for (timeout = 0; timeout < 50000; timeout++) {
383 printk("Processor %d is stuck.\n", cpu);
386 cpu_new_thread = NULL;
393 static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu)
398 if (this_is_starfire) {
399 /* map to real upaid */
400 cpu = (((cpu & 0x3c) << 1) |
401 ((cpu & 0x40) >> 4) |
405 target = (cpu << 14) | 0x70;
407 /* Ok, this is the real Spitfire Errata #54.
408 * One must read back from a UDB internal register
409 * after writes to the UDB interrupt dispatch, but
410 * before the membar Sync for that write.
411 * So we use the high UDB control register (ASI 0x7f,
412 * ADDR 0x20) for the dummy read. -DaveM
415 __asm__ __volatile__(
416 "wrpr %1, %2, %%pstate\n\t"
417 "stxa %4, [%0] %3\n\t"
418 "stxa %5, [%0+%8] %3\n\t"
420 "stxa %6, [%0+%8] %3\n\t"
422 "stxa %%g0, [%7] %3\n\t"
425 "ldxa [%%g1] 0x7f, %%g0\n\t"
428 : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W),
429 "r" (data0), "r" (data1), "r" (data2), "r" (target),
430 "r" (0x10), "0" (tmp)
433 /* NOTE: PSTATE_IE is still clear. */
436 __asm__ __volatile__("ldxa [%%g0] %1, %0"
438 : "i" (ASI_INTR_DISPATCH_STAT));
440 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
447 } while (result & 0x1);
448 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
451 printk("CPU[%d]: mondo stuckage result[%016llx]\n",
452 smp_processor_id(), result);
459 static void spitfire_xcall_deliver(struct trap_per_cpu *tb, int cnt)
461 u64 *mondo, data0, data1, data2;
466 __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
467 cpu_list = __va(tb->cpu_list_pa);
468 mondo = __va(tb->cpu_mondo_block_pa);
472 for (i = 0; i < cnt; i++)
473 spitfire_xcall_helper(data0, data1, data2, pstate, cpu_list[i]);
476 /* Cheetah now allows to send the whole 64-bytes of data in the interrupt
477 * packet, but we have no use for that. However we do take advantage of
478 * the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
480 static void cheetah_xcall_deliver(struct trap_per_cpu *tb, int cnt)
482 int nack_busy_id, is_jbus, need_more;
483 u64 *mondo, pstate, ver, busy_mask;
486 cpu_list = __va(tb->cpu_list_pa);
487 mondo = __va(tb->cpu_mondo_block_pa);
489 /* Unfortunately, someone at Sun had the brilliant idea to make the
490 * busy/nack fields hard-coded by ITID number for this Ultra-III
491 * derivative processor.
493 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
494 is_jbus = ((ver >> 32) == __JALAPENO_ID ||
495 (ver >> 32) == __SERRANO_ID);
497 __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
501 __asm__ __volatile__("wrpr %0, %1, %%pstate\n\t"
502 : : "r" (pstate), "i" (PSTATE_IE));
504 /* Setup the dispatch data registers. */
505 __asm__ __volatile__("stxa %0, [%3] %6\n\t"
506 "stxa %1, [%4] %6\n\t"
507 "stxa %2, [%5] %6\n\t"
510 : "r" (mondo[0]), "r" (mondo[1]), "r" (mondo[2]),
511 "r" (0x40), "r" (0x50), "r" (0x60),
519 for (i = 0; i < cnt; i++) {
526 target = (nr << 14) | 0x70;
528 busy_mask |= (0x1UL << (nr * 2));
530 target |= (nack_busy_id << 24);
531 busy_mask |= (0x1UL <<
534 __asm__ __volatile__(
535 "stxa %%g0, [%0] %1\n\t"
538 : "r" (target), "i" (ASI_INTR_W));
540 if (nack_busy_id == 32) {
547 /* Now, poll for completion. */
549 u64 dispatch_stat, nack_mask;
552 stuck = 100000 * nack_busy_id;
553 nack_mask = busy_mask << 1;
555 __asm__ __volatile__("ldxa [%%g0] %1, %0"
556 : "=r" (dispatch_stat)
557 : "i" (ASI_INTR_DISPATCH_STAT));
558 if (!(dispatch_stat & (busy_mask | nack_mask))) {
559 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
561 if (unlikely(need_more)) {
563 for (i = 0; i < cnt; i++) {
564 if (cpu_list[i] == 0xffff)
566 cpu_list[i] = 0xffff;
577 } while (dispatch_stat & busy_mask);
579 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
582 if (dispatch_stat & busy_mask) {
583 /* Busy bits will not clear, continue instead
584 * of freezing up on this cpu.
586 printk("CPU[%d]: mondo stuckage result[%016llx]\n",
587 smp_processor_id(), dispatch_stat);
589 int i, this_busy_nack = 0;
591 /* Delay some random time with interrupts enabled
592 * to prevent deadlock.
594 udelay(2 * nack_busy_id);
596 /* Clear out the mask bits for cpus which did not
599 for (i = 0; i < cnt; i++) {
607 check_mask = (0x2UL << (2*nr));
609 check_mask = (0x2UL <<
611 if ((dispatch_stat & check_mask) == 0)
612 cpu_list[i] = 0xffff;
614 if (this_busy_nack == 64)
623 /* Multi-cpu list version. */
624 static void hypervisor_xcall_deliver(struct trap_per_cpu *tb, int cnt)
626 int retries, this_cpu, prev_sent, i, saw_cpu_error;
627 unsigned long status;
630 this_cpu = smp_processor_id();
632 cpu_list = __va(tb->cpu_list_pa);
638 int forward_progress, n_sent;
640 status = sun4v_cpu_mondo_send(cnt,
642 tb->cpu_mondo_block_pa);
644 /* HV_EOK means all cpus received the xcall, we're done. */
645 if (likely(status == HV_EOK))
648 /* First, see if we made any forward progress.
650 * The hypervisor indicates successful sends by setting
651 * cpu list entries to the value 0xffff.
654 for (i = 0; i < cnt; i++) {
655 if (likely(cpu_list[i] == 0xffff))
659 forward_progress = 0;
660 if (n_sent > prev_sent)
661 forward_progress = 1;
665 /* If we get a HV_ECPUERROR, then one or more of the cpus
666 * in the list are in error state. Use the cpu_state()
667 * hypervisor call to find out which cpus are in error state.
669 if (unlikely(status == HV_ECPUERROR)) {
670 for (i = 0; i < cnt; i++) {
678 err = sun4v_cpu_state(cpu);
679 if (err == HV_CPU_STATE_ERROR) {
680 saw_cpu_error = (cpu + 1);
681 cpu_list[i] = 0xffff;
684 } else if (unlikely(status != HV_EWOULDBLOCK))
685 goto fatal_mondo_error;
687 /* Don't bother rewriting the CPU list, just leave the
688 * 0xffff and non-0xffff entries in there and the
689 * hypervisor will do the right thing.
691 * Only advance timeout state if we didn't make any
694 if (unlikely(!forward_progress)) {
695 if (unlikely(++retries > 10000))
696 goto fatal_mondo_timeout;
698 /* Delay a little bit to let other cpus catch up
699 * on their cpu mondo queue work.
705 if (unlikely(saw_cpu_error))
706 goto fatal_mondo_cpu_error;
710 fatal_mondo_cpu_error:
711 printk(KERN_CRIT "CPU[%d]: SUN4V mondo cpu error, some target cpus "
712 "(including %d) were in error state\n",
713 this_cpu, saw_cpu_error - 1);
717 printk(KERN_CRIT "CPU[%d]: SUN4V mondo timeout, no forward "
718 " progress after %d retries.\n",
720 goto dump_cpu_list_and_out;
723 printk(KERN_CRIT "CPU[%d]: Unexpected SUN4V mondo error %lu\n",
725 printk(KERN_CRIT "CPU[%d]: Args were cnt(%d) cpulist_pa(%lx) "
726 "mondo_block_pa(%lx)\n",
727 this_cpu, cnt, tb->cpu_list_pa, tb->cpu_mondo_block_pa);
729 dump_cpu_list_and_out:
730 printk(KERN_CRIT "CPU[%d]: CPU list [ ", this_cpu);
731 for (i = 0; i < cnt; i++)
732 printk("%u ", cpu_list[i]);
736 static void (*xcall_deliver_impl)(struct trap_per_cpu *, int);
738 static void xcall_deliver(u64 data0, u64 data1, u64 data2, const cpumask_t *mask)
740 struct trap_per_cpu *tb;
741 int this_cpu, i, cnt;
746 /* We have to do this whole thing with interrupts fully disabled.
747 * Otherwise if we send an xcall from interrupt context it will
748 * corrupt both our mondo block and cpu list state.
750 * One consequence of this is that we cannot use timeout mechanisms
751 * that depend upon interrupts being delivered locally. So, for
752 * example, we cannot sample jiffies and expect it to advance.
754 * Fortunately, udelay() uses %stick/%tick so we can use that.
756 local_irq_save(flags);
758 this_cpu = smp_processor_id();
759 tb = &trap_block[this_cpu];
761 mondo = __va(tb->cpu_mondo_block_pa);
767 cpu_list = __va(tb->cpu_list_pa);
769 /* Setup the initial cpu list. */
771 for_each_cpu(i, mask) {
772 if (i == this_cpu || !cpu_online(i))
778 xcall_deliver_impl(tb, cnt);
780 local_irq_restore(flags);
783 /* Send cross call to all processors mentioned in MASK_P
784 * except self. Really, there are only two cases currently,
785 * "cpu_online_mask" and "mm_cpumask(mm)".
787 static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, const cpumask_t *mask)
789 u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff));
791 xcall_deliver(data0, data1, data2, mask);
794 /* Send cross call to all processors except self. */
795 static void smp_cross_call(unsigned long *func, u32 ctx, u64 data1, u64 data2)
797 smp_cross_call_masked(func, ctx, data1, data2, cpu_online_mask);
800 extern unsigned long xcall_sync_tick;
802 static void smp_start_sync_tick_client(int cpu)
804 xcall_deliver((u64) &xcall_sync_tick, 0, 0,
808 extern unsigned long xcall_call_function;
810 void arch_send_call_function_ipi_mask(const struct cpumask *mask)
812 xcall_deliver((u64) &xcall_call_function, 0, 0, mask);
815 extern unsigned long xcall_call_function_single;
817 void arch_send_call_function_single_ipi(int cpu)
819 xcall_deliver((u64) &xcall_call_function_single, 0, 0,
823 void __irq_entry smp_call_function_client(int irq, struct pt_regs *regs)
825 clear_softint(1 << irq);
827 generic_smp_call_function_interrupt();
831 void __irq_entry smp_call_function_single_client(int irq, struct pt_regs *regs)
833 clear_softint(1 << irq);
835 generic_smp_call_function_single_interrupt();
839 static void tsb_sync(void *info)
841 struct trap_per_cpu *tp = &trap_block[raw_smp_processor_id()];
842 struct mm_struct *mm = info;
844 /* It is not valid to test "current->active_mm == mm" here.
846 * The value of "current" is not changed atomically with
847 * switch_mm(). But that's OK, we just need to check the
848 * current cpu's trap block PGD physical address.
850 if (tp->pgd_paddr == __pa(mm->pgd))
851 tsb_context_switch(mm);
854 void smp_tsb_sync(struct mm_struct *mm)
856 smp_call_function_many(mm_cpumask(mm), tsb_sync, mm, 1);
859 extern unsigned long xcall_flush_tlb_mm;
860 extern unsigned long xcall_flush_tlb_page;
861 extern unsigned long xcall_flush_tlb_kernel_range;
862 extern unsigned long xcall_fetch_glob_regs;
863 extern unsigned long xcall_fetch_glob_pmu;
864 extern unsigned long xcall_fetch_glob_pmu_n4;
865 extern unsigned long xcall_receive_signal;
866 extern unsigned long xcall_new_mmu_context_version;
868 extern unsigned long xcall_kgdb_capture;
871 #ifdef DCACHE_ALIASING_POSSIBLE
872 extern unsigned long xcall_flush_dcache_page_cheetah;
874 extern unsigned long xcall_flush_dcache_page_spitfire;
876 #ifdef CONFIG_DEBUG_DCFLUSH
877 extern atomic_t dcpage_flushes;
878 extern atomic_t dcpage_flushes_xcall;
881 static inline void __local_flush_dcache_page(struct page *page)
883 #ifdef DCACHE_ALIASING_POSSIBLE
884 __flush_dcache_page(page_address(page),
885 ((tlb_type == spitfire) &&
886 page_mapping(page) != NULL));
888 if (page_mapping(page) != NULL &&
889 tlb_type == spitfire)
890 __flush_icache_page(__pa(page_address(page)));
894 void smp_flush_dcache_page_impl(struct page *page, int cpu)
898 if (tlb_type == hypervisor)
901 #ifdef CONFIG_DEBUG_DCFLUSH
902 atomic_inc(&dcpage_flushes);
905 this_cpu = get_cpu();
907 if (cpu == this_cpu) {
908 __local_flush_dcache_page(page);
909 } else if (cpu_online(cpu)) {
910 void *pg_addr = page_address(page);
913 if (tlb_type == spitfire) {
914 data0 = ((u64)&xcall_flush_dcache_page_spitfire);
915 if (page_mapping(page) != NULL)
916 data0 |= ((u64)1 << 32);
917 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
918 #ifdef DCACHE_ALIASING_POSSIBLE
919 data0 = ((u64)&xcall_flush_dcache_page_cheetah);
923 xcall_deliver(data0, __pa(pg_addr),
924 (u64) pg_addr, cpumask_of(cpu));
925 #ifdef CONFIG_DEBUG_DCFLUSH
926 atomic_inc(&dcpage_flushes_xcall);
934 void flush_dcache_page_all(struct mm_struct *mm, struct page *page)
939 if (tlb_type == hypervisor)
944 #ifdef CONFIG_DEBUG_DCFLUSH
945 atomic_inc(&dcpage_flushes);
948 pg_addr = page_address(page);
949 if (tlb_type == spitfire) {
950 data0 = ((u64)&xcall_flush_dcache_page_spitfire);
951 if (page_mapping(page) != NULL)
952 data0 |= ((u64)1 << 32);
953 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
954 #ifdef DCACHE_ALIASING_POSSIBLE
955 data0 = ((u64)&xcall_flush_dcache_page_cheetah);
959 xcall_deliver(data0, __pa(pg_addr),
960 (u64) pg_addr, cpu_online_mask);
961 #ifdef CONFIG_DEBUG_DCFLUSH
962 atomic_inc(&dcpage_flushes_xcall);
965 __local_flush_dcache_page(page);
970 void __irq_entry smp_new_mmu_context_version_client(int irq, struct pt_regs *regs)
972 struct mm_struct *mm;
975 clear_softint(1 << irq);
977 /* See if we need to allocate a new TLB context because
978 * the version of the one we are using is now out of date.
980 mm = current->active_mm;
981 if (unlikely(!mm || (mm == &init_mm)))
984 spin_lock_irqsave(&mm->context.lock, flags);
986 if (unlikely(!CTX_VALID(mm->context)))
987 get_new_mmu_context(mm);
989 spin_unlock_irqrestore(&mm->context.lock, flags);
991 load_secondary_context(mm);
992 __flush_tlb_mm(CTX_HWBITS(mm->context),
996 void smp_new_mmu_context_version(void)
998 smp_cross_call(&xcall_new_mmu_context_version, 0, 0, 0);
1002 void kgdb_roundup_cpus(unsigned long flags)
1004 smp_cross_call(&xcall_kgdb_capture, 0, 0, 0);
1008 void smp_fetch_global_regs(void)
1010 smp_cross_call(&xcall_fetch_glob_regs, 0, 0, 0);
1013 void smp_fetch_global_pmu(void)
1015 if (tlb_type == hypervisor &&
1016 sun4v_chip_type >= SUN4V_CHIP_NIAGARA4)
1017 smp_cross_call(&xcall_fetch_glob_pmu_n4, 0, 0, 0);
1019 smp_cross_call(&xcall_fetch_glob_pmu, 0, 0, 0);
1022 /* We know that the window frames of the user have been flushed
1023 * to the stack before we get here because all callers of us
1024 * are flush_tlb_*() routines, and these run after flush_cache_*()
1025 * which performs the flushw.
1027 * The SMP TLB coherency scheme we use works as follows:
1029 * 1) mm->cpu_vm_mask is a bit mask of which cpus an address
1030 * space has (potentially) executed on, this is the heuristic
1031 * we use to avoid doing cross calls.
1033 * Also, for flushing from kswapd and also for clones, we
1034 * use cpu_vm_mask as the list of cpus to make run the TLB.
1036 * 2) TLB context numbers are shared globally across all processors
1037 * in the system, this allows us to play several games to avoid
1040 * One invariant is that when a cpu switches to a process, and
1041 * that processes tsk->active_mm->cpu_vm_mask does not have the
1042 * current cpu's bit set, that tlb context is flushed locally.
1044 * If the address space is non-shared (ie. mm->count == 1) we avoid
1045 * cross calls when we want to flush the currently running process's
1046 * tlb state. This is done by clearing all cpu bits except the current
1047 * processor's in current->mm->cpu_vm_mask and performing the
1048 * flush locally only. This will force any subsequent cpus which run
1049 * this task to flush the context from the local tlb if the process
1050 * migrates to another cpu (again).
1052 * 3) For shared address spaces (threads) and swapping we bite the
1053 * bullet for most cases and perform the cross call (but only to
1054 * the cpus listed in cpu_vm_mask).
1056 * The performance gain from "optimizing" away the cross call for threads is
1057 * questionable (in theory the big win for threads is the massive sharing of
1058 * address space state across processors).
1061 /* This currently is only used by the hugetlb arch pre-fault
1062 * hook on UltraSPARC-III+ and later when changing the pagesize
1063 * bits of the context register for an address space.
1065 void smp_flush_tlb_mm(struct mm_struct *mm)
1067 u32 ctx = CTX_HWBITS(mm->context);
1068 int cpu = get_cpu();
1070 if (atomic_read(&mm->mm_users) == 1) {
1071 cpumask_copy(mm_cpumask(mm), cpumask_of(cpu));
1072 goto local_flush_and_out;
1075 smp_cross_call_masked(&xcall_flush_tlb_mm,
1079 local_flush_and_out:
1080 __flush_tlb_mm(ctx, SECONDARY_CONTEXT);
1085 struct tlb_pending_info {
1088 unsigned long *vaddrs;
1091 static void tlb_pending_func(void *info)
1093 struct tlb_pending_info *t = info;
1095 __flush_tlb_pending(t->ctx, t->nr, t->vaddrs);
1098 void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs)
1100 u32 ctx = CTX_HWBITS(mm->context);
1101 struct tlb_pending_info info;
1102 int cpu = get_cpu();
1106 info.vaddrs = vaddrs;
1108 if (mm == current->mm && atomic_read(&mm->mm_users) == 1)
1109 cpumask_copy(mm_cpumask(mm), cpumask_of(cpu));
1111 smp_call_function_many(mm_cpumask(mm), tlb_pending_func,
1114 __flush_tlb_pending(ctx, nr, vaddrs);
1119 void smp_flush_tlb_page(struct mm_struct *mm, unsigned long vaddr)
1121 unsigned long context = CTX_HWBITS(mm->context);
1122 int cpu = get_cpu();
1124 if (mm == current->mm && atomic_read(&mm->mm_users) == 1)
1125 cpumask_copy(mm_cpumask(mm), cpumask_of(cpu));
1127 smp_cross_call_masked(&xcall_flush_tlb_page,
1130 __flush_tlb_page(context, vaddr);
1135 void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end)
1138 end = PAGE_ALIGN(end);
1140 smp_cross_call(&xcall_flush_tlb_kernel_range,
1143 __flush_tlb_kernel_range(start, end);
1148 /* #define CAPTURE_DEBUG */
1149 extern unsigned long xcall_capture;
1151 static atomic_t smp_capture_depth = ATOMIC_INIT(0);
1152 static atomic_t smp_capture_registry = ATOMIC_INIT(0);
1153 static unsigned long penguins_are_doing_time;
1155 void smp_capture(void)
1157 int result = atomic_add_ret(1, &smp_capture_depth);
1160 int ncpus = num_online_cpus();
1162 #ifdef CAPTURE_DEBUG
1163 printk("CPU[%d]: Sending penguins to jail...",
1164 smp_processor_id());
1166 penguins_are_doing_time = 1;
1167 atomic_inc(&smp_capture_registry);
1168 smp_cross_call(&xcall_capture, 0, 0, 0);
1169 while (atomic_read(&smp_capture_registry) != ncpus)
1171 #ifdef CAPTURE_DEBUG
1177 void smp_release(void)
1179 if (atomic_dec_and_test(&smp_capture_depth)) {
1180 #ifdef CAPTURE_DEBUG
1181 printk("CPU[%d]: Giving pardon to "
1182 "imprisoned penguins\n",
1183 smp_processor_id());
1185 penguins_are_doing_time = 0;
1186 membar_safe("#StoreLoad");
1187 atomic_dec(&smp_capture_registry);
1191 /* Imprisoned penguins run with %pil == PIL_NORMAL_MAX, but PSTATE_IE
1192 * set, so they can service tlb flush xcalls...
1194 extern void prom_world(int);
1196 void __irq_entry smp_penguin_jailcell(int irq, struct pt_regs *regs)
1198 clear_softint(1 << irq);
1202 __asm__ __volatile__("flushw");
1204 atomic_inc(&smp_capture_registry);
1205 membar_safe("#StoreLoad");
1206 while (penguins_are_doing_time)
1208 atomic_dec(&smp_capture_registry);
1214 /* /proc/profile writes can call this, don't __init it please. */
1215 int setup_profiling_timer(unsigned int multiplier)
1220 void __init smp_prepare_cpus(unsigned int max_cpus)
1224 void smp_prepare_boot_cpu(void)
1228 void __init smp_setup_processor_id(void)
1230 if (tlb_type == spitfire)
1231 xcall_deliver_impl = spitfire_xcall_deliver;
1232 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
1233 xcall_deliver_impl = cheetah_xcall_deliver;
1235 xcall_deliver_impl = hypervisor_xcall_deliver;
1238 void smp_fill_in_sib_core_maps(void)
1242 for_each_present_cpu(i) {
1245 cpumask_clear(&cpu_core_map[i]);
1246 if (cpu_data(i).core_id == 0) {
1247 cpumask_set_cpu(i, &cpu_core_map[i]);
1251 for_each_present_cpu(j) {
1252 if (cpu_data(i).core_id ==
1253 cpu_data(j).core_id)
1254 cpumask_set_cpu(j, &cpu_core_map[i]);
1258 for_each_present_cpu(i) {
1261 cpumask_clear(&per_cpu(cpu_sibling_map, i));
1262 if (cpu_data(i).proc_id == -1) {
1263 cpumask_set_cpu(i, &per_cpu(cpu_sibling_map, i));
1267 for_each_present_cpu(j) {
1268 if (cpu_data(i).proc_id ==
1269 cpu_data(j).proc_id)
1270 cpumask_set_cpu(j, &per_cpu(cpu_sibling_map, i));
1275 int __cpu_up(unsigned int cpu, struct task_struct *tidle)
1277 int ret = smp_boot_one_cpu(cpu, tidle);
1280 cpumask_set_cpu(cpu, &smp_commenced_mask);
1281 while (!cpu_online(cpu))
1283 if (!cpu_online(cpu)) {
1286 /* On SUN4V, writes to %tick and %stick are
1289 if (tlb_type != hypervisor)
1290 smp_synchronize_one_tick(cpu);
1296 #ifdef CONFIG_HOTPLUG_CPU
1297 void cpu_play_dead(void)
1299 int cpu = smp_processor_id();
1300 unsigned long pstate;
1304 if (tlb_type == hypervisor) {
1305 struct trap_per_cpu *tb = &trap_block[cpu];
1307 sun4v_cpu_qconf(HV_CPU_QUEUE_CPU_MONDO,
1308 tb->cpu_mondo_pa, 0);
1309 sun4v_cpu_qconf(HV_CPU_QUEUE_DEVICE_MONDO,
1310 tb->dev_mondo_pa, 0);
1311 sun4v_cpu_qconf(HV_CPU_QUEUE_RES_ERROR,
1312 tb->resum_mondo_pa, 0);
1313 sun4v_cpu_qconf(HV_CPU_QUEUE_NONRES_ERROR,
1314 tb->nonresum_mondo_pa, 0);
1317 cpumask_clear_cpu(cpu, &smp_commenced_mask);
1318 membar_safe("#Sync");
1320 local_irq_disable();
1322 __asm__ __volatile__(
1323 "rdpr %%pstate, %0\n\t"
1324 "wrpr %0, %1, %%pstate"
1332 int __cpu_disable(void)
1334 int cpu = smp_processor_id();
1338 for_each_cpu(i, &cpu_core_map[cpu])
1339 cpumask_clear_cpu(cpu, &cpu_core_map[i]);
1340 cpumask_clear(&cpu_core_map[cpu]);
1342 for_each_cpu(i, &per_cpu(cpu_sibling_map, cpu))
1343 cpumask_clear_cpu(cpu, &per_cpu(cpu_sibling_map, i));
1344 cpumask_clear(&per_cpu(cpu_sibling_map, cpu));
1353 /* Make sure no interrupts point to this cpu. */
1358 local_irq_disable();
1360 set_cpu_online(cpu, false);
1367 void __cpu_die(unsigned int cpu)
1371 for (i = 0; i < 100; i++) {
1373 if (!cpumask_test_cpu(cpu, &smp_commenced_mask))
1377 if (cpumask_test_cpu(cpu, &smp_commenced_mask)) {
1378 printk(KERN_ERR "CPU %u didn't die...\n", cpu);
1380 #if defined(CONFIG_SUN_LDOMS)
1381 unsigned long hv_err;
1385 hv_err = sun4v_cpu_stop(cpu);
1386 if (hv_err == HV_EOK) {
1387 set_cpu_present(cpu, false);
1390 } while (--limit > 0);
1392 printk(KERN_ERR "sun4v_cpu_stop() fails err=%lu\n",
1400 void __init smp_cpus_done(unsigned int max_cpus)
1404 void smp_send_reschedule(int cpu)
1406 if (cpu == smp_processor_id()) {
1407 WARN_ON_ONCE(preemptible());
1408 set_softint(1 << PIL_SMP_RECEIVE_SIGNAL);
1410 xcall_deliver((u64) &xcall_receive_signal,
1411 0, 0, cpumask_of(cpu));
1415 void __irq_entry smp_receive_signal_client(int irq, struct pt_regs *regs)
1417 clear_softint(1 << irq);
1421 /* This is a nop because we capture all other cpus
1422 * anyways when making the PROM active.
1424 void smp_send_stop(void)
1429 * pcpu_alloc_bootmem - NUMA friendly alloc_bootmem wrapper for percpu
1430 * @cpu: cpu to allocate for
1431 * @size: size allocation in bytes
1434 * Allocate @size bytes aligned at @align for cpu @cpu. This wrapper
1435 * does the right thing for NUMA regardless of the current
1439 * Pointer to the allocated area on success, NULL on failure.
1441 static void * __init pcpu_alloc_bootmem(unsigned int cpu, size_t size,
1444 const unsigned long goal = __pa(MAX_DMA_ADDRESS);
1445 #ifdef CONFIG_NEED_MULTIPLE_NODES
1446 int node = cpu_to_node(cpu);
1449 if (!node_online(node) || !NODE_DATA(node)) {
1450 ptr = __alloc_bootmem(size, align, goal);
1451 pr_info("cpu %d has no node %d or node-local memory\n",
1453 pr_debug("per cpu data for cpu%d %lu bytes at %016lx\n",
1454 cpu, size, __pa(ptr));
1456 ptr = __alloc_bootmem_node(NODE_DATA(node),
1458 pr_debug("per cpu data for cpu%d %lu bytes on node%d at "
1459 "%016lx\n", cpu, size, node, __pa(ptr));
1463 return __alloc_bootmem(size, align, goal);
1467 static void __init pcpu_free_bootmem(void *ptr, size_t size)
1469 free_bootmem(__pa(ptr), size);
1472 static int __init pcpu_cpu_distance(unsigned int from, unsigned int to)
1474 if (cpu_to_node(from) == cpu_to_node(to))
1475 return LOCAL_DISTANCE;
1477 return REMOTE_DISTANCE;
1480 static void __init pcpu_populate_pte(unsigned long addr)
1482 pgd_t *pgd = pgd_offset_k(addr);
1486 if (pgd_none(*pgd)) {
1489 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1490 pgd_populate(&init_mm, pgd, new);
1493 pud = pud_offset(pgd, addr);
1494 if (pud_none(*pud)) {
1497 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1498 pud_populate(&init_mm, pud, new);
1501 pmd = pmd_offset(pud, addr);
1502 if (!pmd_present(*pmd)) {
1505 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1506 pmd_populate_kernel(&init_mm, pmd, new);
1510 void __init setup_per_cpu_areas(void)
1512 unsigned long delta;
1516 if (pcpu_chosen_fc != PCPU_FC_PAGE) {
1517 rc = pcpu_embed_first_chunk(PERCPU_MODULE_RESERVE,
1518 PERCPU_DYNAMIC_RESERVE, 4 << 20,
1523 pr_warning("PERCPU: %s allocator failed (%d), "
1524 "falling back to page size\n",
1525 pcpu_fc_names[pcpu_chosen_fc], rc);
1528 rc = pcpu_page_first_chunk(PERCPU_MODULE_RESERVE,
1533 panic("cannot initialize percpu area (err=%d)", rc);
1535 delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
1536 for_each_possible_cpu(cpu)
1537 __per_cpu_offset(cpu) = delta + pcpu_unit_offsets[cpu];
1539 /* Setup %g5 for the boot cpu. */
1540 __local_per_cpu_offset = __per_cpu_offset(smp_processor_id());
1542 of_fill_in_cpu_data();
1543 if (tlb_type == hypervisor)
1544 mdesc_fill_in_cpu_data(cpu_all_mask);