arch/sparc/kernel/smp_64.c

   1 /* smp.c: Sparc64 SMP support.
   2  *
   3  * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net)
   4  */
   5
   6 #include <linux/export.h>
   7 #include <linux/kernel.h>
   8 #include <linux/sched.h>
   9 #include <linux/mm.h>
  10 #include <linux/pagemap.h>
  11 #include <linux/threads.h>
  12 #include <linux/smp.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/kernel_stat.h>
  15 #include <linux/delay.h>
  16 #include <linux/init.h>
  17 #include <linux/spinlock.h>
  18 #include <linux/fs.h>
  19 #include <linux/seq_file.h>
  20 #include <linux/cache.h>
  21 #include <linux/jiffies.h>
  22 #include <linux/profile.h>
  23 #include <linux/bootmem.h>
  24 #include <linux/vmalloc.h>
  25 #include <linux/ftrace.h>
  26 #include <linux/cpu.h>
  27 #include <linux/slab.h>
  28
  29 #include <asm/head.h>
  30 #include <asm/ptrace.h>
  31 #include <linux/atomic.h>
  32 #include <asm/tlbflush.h>
  33 #include <asm/mmu_context.h>
  34 #include <asm/cpudata.h>
  35 #include <asm/hvtramp.h>
  36 #include <asm/io.h>
  37 #include <asm/timer.h>
  38
  39 #include <asm/irq.h>
  40 #include <asm/irq_regs.h>
  41 #include <asm/page.h>
  42 #include <asm/pgtable.h>
  43 #include <asm/oplib.h>
  44 #include <asm/uaccess.h>
  45 #include <asm/starfire.h>
  46 #include <asm/tlb.h>
  47 #include <asm/sections.h>
  48 #include <asm/prom.h>
  49 #include <asm/mdesc.h>
  50 #include <asm/ldc.h>
  51 #include <asm/hypervisor.h>
  52 #include <asm/pcr.h>
  53
  54 #include "cpumap.h"
  55
  56 int sparc64_multi_core __read_mostly;
  57
  58 DEFINE_PER_CPU(cpumask_t, cpu_sibling_map) = CPU_MASK_NONE;
  59 cpumask_t cpu_core_map[NR_CPUS] __read_mostly =
  60         { [0 ... NR_CPUS-1] = CPU_MASK_NONE };
  61
  62 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
  63 EXPORT_SYMBOL(cpu_core_map);
  64
  65 static cpumask_t smp_commenced_mask;
  66
  67 void smp_info(struct seq_file *m)
  68 {
  69         int i;
  70
  71         seq_printf(m, "State:\n");
  72         for_each_online_cpu(i)
  73                 seq_printf(m, "CPU%d:\t\tonline\n", i);
  74 }
  75
  76 void smp_bogo(struct seq_file *m)
  77 {
  78         int i;
  79
  80         for_each_online_cpu(i)
  81                 seq_printf(m,
  82                            "Cpu%dClkTck\t: %016lx\n",
  83                            i, cpu_data(i).clock_tick);
  84 }
  85
  86 extern void setup_sparc64_timer(void);
  87
  88 static volatile unsigned long callin_flag = 0;
  89
  90 void smp_callin(void)
  91 {
  92         int cpuid = hard_smp_processor_id();
  93
  94         __local_per_cpu_offset = __per_cpu_offset(cpuid);
  95
  96         if (tlb_type == hypervisor)
  97                 sun4v_ktsb_register();
  98
  99         __flush_tlb_all();
 100
 101         setup_sparc64_timer();
 102
 103         if (cheetah_pcache_forced_on)
 104                 cheetah_enable_pcache();
 105
 106         callin_flag = 1;
 107         __asm__ __volatile__("membar #Sync\n\t"
 108                              "flush  %%g6" : : : "memory");
 109
 110         /* Clear this or we will die instantly when we
 111          * schedule back to this idler...
 112          */
 113         current_thread_info()->new_child = 0;
 114
 115         /* Attach to the address space of init_task. */
 116         atomic_inc(&init_mm.mm_count);
 117         current->active_mm = &init_mm;
 118
 119         /* inform the notifiers about the new cpu */
 120         notify_cpu_starting(cpuid);
 121
 122         while (!cpumask_test_cpu(cpuid, &smp_commenced_mask))
 123                 rmb();
 124
 125         set_cpu_online(cpuid, true);
 126
 127         /* idle thread is expected to have preempt disabled */
 128         preempt_disable();
 129
 130         local_irq_enable();
 131
 132         cpu_startup_entry(CPUHP_ONLINE);
 133 }
 134
 135 void cpu_panic(void)
 136 {
 137         printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
 138         panic("SMP bolixed\n");
 139 }
 140
 141 /* This tick register synchronization scheme is taken entirely from
 142  * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit.
 143  *
 144  * The only change I've made is to rework it so that the master
 145  * initiates the synchonization instead of the slave. -DaveM
 146  */
 147
 148 #define MASTER  0
 149 #define SLAVE   (SMP_CACHE_BYTES/sizeof(unsigned long))
 150
 151 #define NUM_ROUNDS      64      /* magic value */
 152 #define NUM_ITERS       5       /* likewise */
 153
 154 static DEFINE_RAW_SPINLOCK(itc_sync_lock);
 155 static unsigned long go[SLAVE + 1];
 156
 157 #define DEBUG_TICK_SYNC 0
 158
 159 static inline long get_delta (long *rt, long *master)
 160 {
 161         unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
 162         unsigned long tcenter, t0, t1, tm;
 163         unsigned long i;
 164
 165         for (i = 0; i < NUM_ITERS; i++) {
 166                 t0 = tick_ops->get_tick();
 167                 go[MASTER] = 1;
 168                 membar_safe("#StoreLoad");
 169                 while (!(tm = go[SLAVE]))
 170                         rmb();
 171                 go[SLAVE] = 0;
 172                 wmb();
 173                 t1 = tick_ops->get_tick();
 174
 175                 if (t1 - t0 < best_t1 - best_t0)
 176                         best_t0 = t0, best_t1 = t1, best_tm = tm;
 177         }
 178
 179         *rt = best_t1 - best_t0;
 180         *master = best_tm - best_t0;
 181
 182         /* average best_t0 and best_t1 without overflow: */
 183         tcenter = (best_t0/2 + best_t1/2);
 184         if (best_t0 % 2 + best_t1 % 2 == 2)
 185                 tcenter++;
 186         return tcenter - best_tm;
 187 }
 188
 189 void smp_synchronize_tick_client(void)
 190 {
 191         long i, delta, adj, adjust_latency = 0, done = 0;
 192         unsigned long flags, rt, master_time_stamp;
 193 #if DEBUG_TICK_SYNC
 194         struct {
 195                 long rt;        /* roundtrip time */
 196                 long master;    /* master's timestamp */
 197                 long diff;      /* difference between midpoint and master's timestamp */
 198                 long lat;       /* estimate of itc adjustment latency */
 199         } t[NUM_ROUNDS];
 200 #endif
 201
 202         go[MASTER] = 1;
 203
 204         while (go[MASTER])
 205                 rmb();
 206
 207         local_irq_save(flags);
 208         {
 209                 for (i = 0; i < NUM_ROUNDS; i++) {
 210                         delta = get_delta(&rt, &master_time_stamp);
 211                         if (delta == 0)
 212                                 done = 1;       /* let's lock on to this... */
 213
 214                         if (!done) {
 215                                 if (i > 0) {
 216                                         adjust_latency += -delta;
 217                                         adj = -delta + adjust_latency/4;
 218                                 } else
 219                                         adj = -delta;
 220
 221                                 tick_ops->add_tick(adj);
 222                         }
 223 #if DEBUG_TICK_SYNC
 224                         t[i].rt = rt;
 225                         t[i].master = master_time_stamp;
 226                         t[i].diff = delta;
 227                         t[i].lat = adjust_latency/4;
 228 #endif
 229                 }
 230         }
 231         local_irq_restore(flags);
 232
 233 #if DEBUG_TICK_SYNC
 234         for (i = 0; i < NUM_ROUNDS; i++)
 235                 printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
 236                        t[i].rt, t[i].master, t[i].diff, t[i].lat);
 237 #endif
 238
 239         printk(KERN_INFO "CPU %d: synchronized TICK with master CPU "
 240                "(last diff %ld cycles, maxerr %lu cycles)\n",
 241                smp_processor_id(), delta, rt);
 242 }
 243
 244 static void smp_start_sync_tick_client(int cpu);
 245
 246 static void smp_synchronize_one_tick(int cpu)
 247 {
 248         unsigned long flags, i;
 249
 250         go[MASTER] = 0;
 251
 252         smp_start_sync_tick_client(cpu);
 253
 254         /* wait for client to be ready */
 255         while (!go[MASTER])
 256                 rmb();
 257
 258         /* now let the client proceed into his loop */
 259         go[MASTER] = 0;
 260         membar_safe("#StoreLoad");
 261
 262         raw_spin_lock_irqsave(&itc_sync_lock, flags);
 263         {
 264                 for (i = 0; i < NUM_ROUNDS*NUM_ITERS; i++) {
 265                         while (!go[MASTER])
 266                                 rmb();
 267                         go[MASTER] = 0;
 268                         wmb();
 269                         go[SLAVE] = tick_ops->get_tick();
 270                         membar_safe("#StoreLoad");
 271                 }
 272         }
 273         raw_spin_unlock_irqrestore(&itc_sync_lock, flags);
 274 }
 275
 276 #if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
 277 /* XXX Put this in some common place. XXX */
 278 static unsigned long kimage_addr_to_ra(void *p)
 279 {
 280         unsigned long val = (unsigned long) p;
 281
 282         return kern_base + (val - KERNBASE);
 283 }
 284
 285 static void ldom_startcpu_cpuid(unsigned int cpu, unsigned long thread_reg,
 286                                 void **descrp)
 287 {
 288         extern unsigned long sparc64_ttable_tl0;
 289         extern unsigned long kern_locked_tte_data;
 290         struct hvtramp_descr *hdesc;
 291         unsigned long trampoline_ra;
 292         struct trap_per_cpu *tb;
 293         u64 tte_vaddr, tte_data;
 294         unsigned long hv_err;
 295         int i;
 296
 297         hdesc = kzalloc(sizeof(*hdesc) +
 298                         (sizeof(struct hvtramp_mapping) *
 299                          num_kernel_image_mappings - 1),
 300                         GFP_KERNEL);
 301         if (!hdesc) {
 302                 printk(KERN_ERR "ldom_startcpu_cpuid: Cannot allocate "
 303                        "hvtramp_descr.\n");
 304                 return;
 305         }
 306         *descrp = hdesc;
 307
 308         hdesc->cpu = cpu;
 309         hdesc->num_mappings = num_kernel_image_mappings;
 310
 311         tb = &trap_block[cpu];
 312
 313         hdesc->fault_info_va = (unsigned long) &tb->fault_info;
 314         hdesc->fault_info_pa = kimage_addr_to_ra(&tb->fault_info);
 315
 316         hdesc->thread_reg = thread_reg;
 317
 318         tte_vaddr = (unsigned long) KERNBASE;
 319         tte_data = kern_locked_tte_data;
 320
 321         for (i = 0; i < hdesc->num_mappings; i++) {
 322                 hdesc->maps[i].vaddr = tte_vaddr;
 323                 hdesc->maps[i].tte   = tte_data;
 324                 tte_vaddr += 0x400000;
 325                 tte_data  += 0x400000;
 326         }
 327
 328         trampoline_ra = kimage_addr_to_ra(hv_cpu_startup);
 329
 330         hv_err = sun4v_cpu_start(cpu, trampoline_ra,
 331                                  kimage_addr_to_ra(&sparc64_ttable_tl0),
 332                                  __pa(hdesc));
 333         if (hv_err)
 334                 printk(KERN_ERR "ldom_startcpu_cpuid: sun4v_cpu_start() "
 335                        "gives error %lu\n", hv_err);
 336 }
 337 #endif
 338
 339 extern unsigned long sparc64_cpu_startup;
 340
 341 /* The OBP cpu startup callback truncates the 3rd arg cookie to
 342  * 32-bits (I think) so to be safe we have it read the pointer
 343  * contained here so we work on >4GB machines. -DaveM
 344  */
 345 static struct thread_info *cpu_new_thread = NULL;
 346
 347 static int smp_boot_one_cpu(unsigned int cpu, struct task_struct *idle)
 348 {
 349         unsigned long entry =
 350                 (unsigned long)(&sparc64_cpu_startup);
 351         unsigned long cookie =
 352                 (unsigned long)(&cpu_new_thread);
 353         void *descr = NULL;
 354         int timeout, ret;
 355
 356         callin_flag = 0;
 357         cpu_new_thread = task_thread_info(idle);
 358
 359         if (tlb_type == hypervisor) {
 360 #if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
 361                 if (ldom_domaining_enabled)
 362                         ldom_startcpu_cpuid(cpu,
 363                                             (unsigned long) cpu_new_thread,
 364                                             &descr);
 365                 else
 366 #endif
 367                         prom_startcpu_cpuid(cpu, entry, cookie);
 368         } else {
 369                 struct device_node *dp = of_find_node_by_cpuid(cpu);
 370
 371                 prom_startcpu(dp->phandle, entry, cookie);
 372         }
 373
 374         for (timeout = 0; timeout < 50000; timeout++) {
 375                 if (callin_flag)
 376                         break;
 377                 udelay(100);
 378         }
 379
 380         if (callin_flag) {
 381                 ret = 0;
 382         } else {
 383                 printk("Processor %d is stuck.\n", cpu);
 384                 ret = -ENODEV;
 385         }
 386         cpu_new_thread = NULL;
 387
 388         kfree(descr);
 389
 390         return ret;
 391 }
 392
 393 static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu)
 394 {
 395         u64 result, target;
 396         int stuck, tmp;
 397
 398         if (this_is_starfire) {
 399                 /* map to real upaid */
 400                 cpu = (((cpu & 0x3c) << 1) |
 401                         ((cpu & 0x40) >> 4) |
 402                         (cpu & 0x3));
 403         }
 404
 405         target = (cpu << 14) | 0x70;
 406 again:
 407         /* Ok, this is the real Spitfire Errata #54.
 408          * One must read back from a UDB internal register
 409          * after writes to the UDB interrupt dispatch, but
 410          * before the membar Sync for that write.
 411          * So we use the high UDB control register (ASI 0x7f,
 412          * ADDR 0x20) for the dummy read. -DaveM
 413          */
 414         tmp = 0x40;
 415         __asm__ __volatile__(
 416         "wrpr   %1, %2, %%pstate\n\t"
 417         "stxa   %4, [%0] %3\n\t"
 418         "stxa   %5, [%0+%8] %3\n\t"
 419         "add    %0, %8, %0\n\t"
 420         "stxa   %6, [%0+%8] %3\n\t"
 421         "membar #Sync\n\t"
 422         "stxa   %%g0, [%7] %3\n\t"
 423         "membar #Sync\n\t"
 424         "mov    0x20, %%g1\n\t"
 425         "ldxa   [%%g1] 0x7f, %%g0\n\t"
 426         "membar #Sync"
 427         : "=r" (tmp)
 428         : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W),
 429           "r" (data0), "r" (data1), "r" (data2), "r" (target),
 430           "r" (0x10), "0" (tmp)
 431         : "g1");
 432
 433         /* NOTE: PSTATE_IE is still clear. */
 434         stuck = 100000;
 435         do {
 436                 __asm__ __volatile__("ldxa [%%g0] %1, %0"
 437                         : "=r" (result)
 438                         : "i" (ASI_INTR_DISPATCH_STAT));
 439                 if (result == 0) {
 440                         __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 441                                              : : "r" (pstate));
 442                         return;
 443                 }
 444                 stuck -= 1;
 445                 if (stuck == 0)
 446                         break;
 447         } while (result & 0x1);
 448         __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 449                              : : "r" (pstate));
 450         if (stuck == 0) {
 451                 printk("CPU[%d]: mondo stuckage result[%016llx]\n",
 452                        smp_processor_id(), result);
 453         } else {
 454                 udelay(2);
 455                 goto again;
 456         }
 457 }
 458
 459 static void spitfire_xcall_deliver(struct trap_per_cpu *tb, int cnt)
 460 {
 461         u64 *mondo, data0, data1, data2;
 462         u16 *cpu_list;
 463         u64 pstate;
 464         int i;
 465
 466         __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
 467         cpu_list = __va(tb->cpu_list_pa);
 468         mondo = __va(tb->cpu_mondo_block_pa);
 469         data0 = mondo[0];
 470         data1 = mondo[1];
 471         data2 = mondo[2];
 472         for (i = 0; i < cnt; i++)
 473                 spitfire_xcall_helper(data0, data1, data2, pstate, cpu_list[i]);
 474 }
 475
 476 /* Cheetah now allows to send the whole 64-bytes of data in the interrupt
 477  * packet, but we have no use for that.  However we do take advantage of
 478  * the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
 479  */
 480 static void cheetah_xcall_deliver(struct trap_per_cpu *tb, int cnt)
 481 {
 482         int nack_busy_id, is_jbus, need_more;
 483         u64 *mondo, pstate, ver, busy_mask;
 484         u16 *cpu_list;
 485
 486         cpu_list = __va(tb->cpu_list_pa);
 487         mondo = __va(tb->cpu_mondo_block_pa);
 488
 489         /* Unfortunately, someone at Sun had the brilliant idea to make the
 490          * busy/nack fields hard-coded by ITID number for this Ultra-III
 491          * derivative processor.
 492          */
 493         __asm__ ("rdpr %%ver, %0" : "=r" (ver));
 494         is_jbus = ((ver >> 32) == __JALAPENO_ID ||
 495                    (ver >> 32) == __SERRANO_ID);
 496
 497         __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
 498
 499 retry:
 500         need_more = 0;
 501         __asm__ __volatile__("wrpr %0, %1, %%pstate\n\t"
 502                              : : "r" (pstate), "i" (PSTATE_IE));
 503
 504         /* Setup the dispatch data registers. */
 505         __asm__ __volatile__("stxa      %0, [%3] %6\n\t"
 506                              "stxa      %1, [%4] %6\n\t"
 507                              "stxa      %2, [%5] %6\n\t"
 508                              "membar    #Sync\n\t"
 509                              : /* no outputs */
 510                              : "r" (mondo[0]), "r" (mondo[1]), "r" (mondo[2]),
 511                                "r" (0x40), "r" (0x50), "r" (0x60),
 512                                "i" (ASI_INTR_W));
 513
 514         nack_busy_id = 0;
 515         busy_mask = 0;
 516         {
 517                 int i;
 518
 519                 for (i = 0; i < cnt; i++) {
 520                         u64 target, nr;
 521
 522                         nr = cpu_list[i];
 523                         if (nr == 0xffff)
 524                                 continue;
 525
 526                         target = (nr << 14) | 0x70;
 527                         if (is_jbus) {
 528                                 busy_mask |= (0x1UL << (nr * 2));
 529                         } else {
 530                                 target |= (nack_busy_id << 24);
 531                                 busy_mask |= (0x1UL <<
 532                                               (nack_busy_id * 2));
 533                         }
 534                         __asm__ __volatile__(
 535                                 "stxa   %%g0, [%0] %1\n\t"
 536                                 "membar #Sync\n\t"
 537                                 : /* no outputs */
 538                                 : "r" (target), "i" (ASI_INTR_W));
 539                         nack_busy_id++;
 540                         if (nack_busy_id == 32) {
 541                                 need_more = 1;
 542                                 break;
 543                         }
 544                 }
 545         }
 546
 547         /* Now, poll for completion. */
 548         {
 549                 u64 dispatch_stat, nack_mask;
 550                 long stuck;
 551
 552                 stuck = 100000 * nack_busy_id;
 553                 nack_mask = busy_mask << 1;
 554                 do {
 555                         __asm__ __volatile__("ldxa      [%%g0] %1, %0"
 556                                              : "=r" (dispatch_stat)
 557                                              : "i" (ASI_INTR_DISPATCH_STAT));
 558                         if (!(dispatch_stat & (busy_mask | nack_mask))) {
 559                                 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 560                                                      : : "r" (pstate));
 561                                 if (unlikely(need_more)) {
 562                                         int i, this_cnt = 0;
 563                                         for (i = 0; i < cnt; i++) {
 564                                                 if (cpu_list[i] == 0xffff)
 565                                                         continue;
 566                                                 cpu_list[i] = 0xffff;
 567                                                 this_cnt++;
 568                                                 if (this_cnt == 32)
 569                                                         break;
 570                                         }
 571                                         goto retry;
 572                                 }
 573                                 return;
 574                         }
 575                         if (!--stuck)
 576                                 break;
 577                 } while (dispatch_stat & busy_mask);
 578
 579                 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 580                                      : : "r" (pstate));
 581
 582                 if (dispatch_stat & busy_mask) {
 583                         /* Busy bits will not clear, continue instead
 584                          * of freezing up on this cpu.
 585                          */
 586                         printk("CPU[%d]: mondo stuckage result[%016llx]\n",
 587                                smp_processor_id(), dispatch_stat);
 588                 } else {
 589                         int i, this_busy_nack = 0;
 590
 591                         /* Delay some random time with interrupts enabled
 592                          * to prevent deadlock.
 593                          */
 594                         udelay(2 * nack_busy_id);
 595
 596                         /* Clear out the mask bits for cpus which did not
 597                          * NACK us.
 598                          */
 599                         for (i = 0; i < cnt; i++) {
 600                                 u64 check_mask, nr;
 601
 602                                 nr = cpu_list[i];
 603                                 if (nr == 0xffff)
 604                                         continue;
 605
 606                                 if (is_jbus)
 607                                         check_mask = (0x2UL << (2*nr));
 608                                 else
 609                                         check_mask = (0x2UL <<
 610                                                       this_busy_nack);
 611                                 if ((dispatch_stat & check_mask) == 0)
 612                                         cpu_list[i] = 0xffff;
 613                                 this_busy_nack += 2;
 614                                 if (this_busy_nack == 64)
 615                                         break;
 616                         }
 617
 618                         goto retry;
 619                 }
 620         }
 621 }
 622
 623 /* Multi-cpu list version.  */
 624 static void hypervisor_xcall_deliver(struct trap_per_cpu *tb, int cnt)
 625 {
 626         int retries, this_cpu, prev_sent, i, saw_cpu_error;
 627         unsigned long status;
 628         u16 *cpu_list;
 629
 630         this_cpu = smp_processor_id();
 631
 632         cpu_list = __va(tb->cpu_list_pa);
 633
 634         saw_cpu_error = 0;
 635         retries = 0;
 636         prev_sent = 0;
 637         do {
 638                 int forward_progress, n_sent;
 639
 640                 status = sun4v_cpu_mondo_send(cnt,
 641                                               tb->cpu_list_pa,
 642                                               tb->cpu_mondo_block_pa);
 643
 644                 /* HV_EOK means all cpus received the xcall, we're done.  */
 645                 if (likely(status == HV_EOK))
 646                         break;
 647
 648                 /* First, see if we made any forward progress.
 649                  *
 650                  * The hypervisor indicates successful sends by setting
 651                  * cpu list entries to the value 0xffff.
 652                  */
 653                 n_sent = 0;
 654                 for (i = 0; i < cnt; i++) {
 655                         if (likely(cpu_list[i] == 0xffff))
 656                                 n_sent++;
 657                 }
 658
 659                 forward_progress = 0;
 660                 if (n_sent > prev_sent)
 661                         forward_progress = 1;
 662
 663                 prev_sent = n_sent;
 664
 665                 /* If we get a HV_ECPUERROR, then one or more of the cpus
 666                  * in the list are in error state.  Use the cpu_state()
 667                  * hypervisor call to find out which cpus are in error state.
 668                  */
 669                 if (unlikely(status == HV_ECPUERROR)) {
 670                         for (i = 0; i < cnt; i++) {
 671                                 long err;
 672                                 u16 cpu;
 673
 674                                 cpu = cpu_list[i];
 675                                 if (cpu == 0xffff)
 676                                         continue;
 677
 678                                 err = sun4v_cpu_state(cpu);
 679                                 if (err == HV_CPU_STATE_ERROR) {
 680                                         saw_cpu_error = (cpu + 1);
 681                                         cpu_list[i] = 0xffff;
 682                                 }
 683                         }
 684                 } else if (unlikely(status != HV_EWOULDBLOCK))
 685                         goto fatal_mondo_error;
 686
 687                 /* Don't bother rewriting the CPU list, just leave the
 688                  * 0xffff and non-0xffff entries in there and the
 689                  * hypervisor will do the right thing.
 690                  *
 691                  * Only advance timeout state if we didn't make any
 692                  * forward progress.
 693                  */
 694                 if (unlikely(!forward_progress)) {
 695                         if (unlikely(++retries > 10000))
 696                                 goto fatal_mondo_timeout;
 697
 698                         /* Delay a little bit to let other cpus catch up
 699                          * on their cpu mondo queue work.
 700                          */
 701                         udelay(2 * cnt);
 702                 }
 703         } while (1);
 704
 705         if (unlikely(saw_cpu_error))
 706                 goto fatal_mondo_cpu_error;
 707
 708         return;
 709
 710 fatal_mondo_cpu_error:
 711         printk(KERN_CRIT "CPU[%d]: SUN4V mondo cpu error, some target cpus "
 712                "(including %d) were in error state\n",
 713                this_cpu, saw_cpu_error - 1);
 714         return;
 715
 716 fatal_mondo_timeout:
 717         printk(KERN_CRIT "CPU[%d]: SUN4V mondo timeout, no forward "
 718                " progress after %d retries.\n",
 719                this_cpu, retries);
 720         goto dump_cpu_list_and_out;
 721
 722 fatal_mondo_error:
 723         printk(KERN_CRIT "CPU[%d]: Unexpected SUN4V mondo error %lu\n",
 724                this_cpu, status);
 725         printk(KERN_CRIT "CPU[%d]: Args were cnt(%d) cpulist_pa(%lx) "
 726                "mondo_block_pa(%lx)\n",
 727                this_cpu, cnt, tb->cpu_list_pa, tb->cpu_mondo_block_pa);
 728
 729 dump_cpu_list_and_out:
 730         printk(KERN_CRIT "CPU[%d]: CPU list [ ", this_cpu);
 731         for (i = 0; i < cnt; i++)
 732                 printk("%u ", cpu_list[i]);
 733         printk("]\n");
 734 }
 735
 736 static void (*xcall_deliver_impl)(struct trap_per_cpu *, int);
 737
 738 static void xcall_deliver(u64 data0, u64 data1, u64 data2, const cpumask_t *mask)
 739 {
 740         struct trap_per_cpu *tb;
 741         int this_cpu, i, cnt;
 742         unsigned long flags;
 743         u16 *cpu_list;
 744         u64 *mondo;
 745
 746         /* We have to do this whole thing with interrupts fully disabled.
 747          * Otherwise if we send an xcall from interrupt context it will
 748          * corrupt both our mondo block and cpu list state.
 749          *
 750          * One consequence of this is that we cannot use timeout mechanisms
 751          * that depend upon interrupts being delivered locally.  So, for
 752          * example, we cannot sample jiffies and expect it to advance.
 753          *
 754          * Fortunately, udelay() uses %stick/%tick so we can use that.
 755          */
 756         local_irq_save(flags);
 757
 758         this_cpu = smp_processor_id();
 759         tb = &trap_block[this_cpu];
 760
 761         mondo = __va(tb->cpu_mondo_block_pa);
 762         mondo[0] = data0;
 763         mondo[1] = data1;
 764         mondo[2] = data2;
 765         wmb();
 766
 767         cpu_list = __va(tb->cpu_list_pa);
 768
 769         /* Setup the initial cpu list.  */
 770         cnt = 0;
 771         for_each_cpu(i, mask) {
 772                 if (i == this_cpu || !cpu_online(i))
 773                         continue;
 774                 cpu_list[cnt++] = i;
 775         }
 776
 777         if (cnt)
 778                 xcall_deliver_impl(tb, cnt);
 779
 780         local_irq_restore(flags);
 781 }
 782
 783 /* Send cross call to all processors mentioned in MASK_P
 784  * except self.  Really, there are only two cases currently,
 785  * "cpu_online_mask" and "mm_cpumask(mm)".
 786  */
 787 static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, const cpumask_t *mask)
 788 {
 789         u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff));
 790
 791         xcall_deliver(data0, data1, data2, mask);
 792 }
 793
 794 /* Send cross call to all processors except self. */
 795 static void smp_cross_call(unsigned long *func, u32 ctx, u64 data1, u64 data2)
 796 {
 797         smp_cross_call_masked(func, ctx, data1, data2, cpu_online_mask);
 798 }
 799
 800 extern unsigned long xcall_sync_tick;
 801
 802 static void smp_start_sync_tick_client(int cpu)
 803 {
 804         xcall_deliver((u64) &xcall_sync_tick, 0, 0,
 805                       cpumask_of(cpu));
 806 }
 807
 808 extern unsigned long xcall_call_function;
 809
 810 void arch_send_call_function_ipi_mask(const struct cpumask *mask)
 811 {
 812         xcall_deliver((u64) &xcall_call_function, 0, 0, mask);
 813 }
 814
 815 extern unsigned long xcall_call_function_single;
 816
 817 void arch_send_call_function_single_ipi(int cpu)
 818 {
 819         xcall_deliver((u64) &xcall_call_function_single, 0, 0,
 820                       cpumask_of(cpu));
 821 }
 822
 823 void __irq_entry smp_call_function_client(int irq, struct pt_regs *regs)
 824 {
 825         clear_softint(1 << irq);
 826         irq_enter();
 827         generic_smp_call_function_interrupt();
 828         irq_exit();
 829 }
 830
 831 void __irq_entry smp_call_function_single_client(int irq, struct pt_regs *regs)
 832 {
 833         clear_softint(1 << irq);
 834         irq_enter();
 835         generic_smp_call_function_single_interrupt();
 836         irq_exit();
 837 }
 838
 839 static void tsb_sync(void *info)
 840 {
 841         struct trap_per_cpu *tp = &trap_block[raw_smp_processor_id()];
 842         struct mm_struct *mm = info;
 843
 844         /* It is not valid to test "current->active_mm == mm" here.
 845          *
 846          * The value of "current" is not changed atomically with
 847          * switch_mm().  But that's OK, we just need to check the
 848          * current cpu's trap block PGD physical address.
 849          */
 850         if (tp->pgd_paddr == __pa(mm->pgd))
 851                 tsb_context_switch(mm);
 852 }
 853
 854 void smp_tsb_sync(struct mm_struct *mm)
 855 {
 856         smp_call_function_many(mm_cpumask(mm), tsb_sync, mm, 1);
 857 }
 858
 859 extern unsigned long xcall_flush_tlb_mm;
 860 extern unsigned long xcall_flush_tlb_page;
 861 extern unsigned long xcall_flush_tlb_kernel_range;
 862 extern unsigned long xcall_fetch_glob_regs;
 863 extern unsigned long xcall_fetch_glob_pmu;
 864 extern unsigned long xcall_fetch_glob_pmu_n4;
 865 extern unsigned long xcall_receive_signal;
 866 extern unsigned long xcall_new_mmu_context_version;
 867 #ifdef CONFIG_KGDB
 868 extern unsigned long xcall_kgdb_capture;
 869 #endif
 870
 871 #ifdef DCACHE_ALIASING_POSSIBLE
 872 extern unsigned long xcall_flush_dcache_page_cheetah;
 873 #endif
 874 extern unsigned long xcall_flush_dcache_page_spitfire;
 875
 876 #ifdef CONFIG_DEBUG_DCFLUSH
 877 extern atomic_t dcpage_flushes;
 878 extern atomic_t dcpage_flushes_xcall;
 879 #endif
 880
 881 static inline void __local_flush_dcache_page(struct page *page)
 882 {
 883 #ifdef DCACHE_ALIASING_POSSIBLE
 884         __flush_dcache_page(page_address(page),
 885                             ((tlb_type == spitfire) &&
 886                              page_mapping(page) != NULL));
 887 #else
 888         if (page_mapping(page) != NULL &&
 889             tlb_type == spitfire)
 890                 __flush_icache_page(__pa(page_address(page)));
 891 #endif
 892 }
 893
 894 void smp_flush_dcache_page_impl(struct page *page, int cpu)
 895 {
 896         int this_cpu;
 897
 898         if (tlb_type == hypervisor)
 899                 return;
 900
 901 #ifdef CONFIG_DEBUG_DCFLUSH
 902         atomic_inc(&dcpage_flushes);
 903 #endif
 904
 905         this_cpu = get_cpu();
 906
 907         if (cpu == this_cpu) {
 908                 __local_flush_dcache_page(page);
 909         } else if (cpu_online(cpu)) {
 910                 void *pg_addr = page_address(page);
 911                 u64 data0 = 0;
 912
 913                 if (tlb_type == spitfire) {
 914                         data0 = ((u64)&xcall_flush_dcache_page_spitfire);
 915                         if (page_mapping(page) != NULL)
 916                                 data0 |= ((u64)1 << 32);
 917                 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 918 #ifdef DCACHE_ALIASING_POSSIBLE
 919                         data0 = ((u64)&xcall_flush_dcache_page_cheetah);
 920 #endif
 921                 }
 922                 if (data0) {
 923                         xcall_deliver(data0, __pa(pg_addr),
 924                                       (u64) pg_addr, cpumask_of(cpu));
 925 #ifdef CONFIG_DEBUG_DCFLUSH
 926                         atomic_inc(&dcpage_flushes_xcall);
 927 #endif
 928                 }
 929         }
 930
 931         put_cpu();
 932 }
 933
 934 void flush_dcache_page_all(struct mm_struct *mm, struct page *page)
 935 {
 936         void *pg_addr;
 937         u64 data0;
 938
 939         if (tlb_type == hypervisor)
 940                 return;
 941
 942         preempt_disable();
 943
 944 #ifdef CONFIG_DEBUG_DCFLUSH
 945         atomic_inc(&dcpage_flushes);
 946 #endif
 947         data0 = 0;
 948         pg_addr = page_address(page);
 949         if (tlb_type == spitfire) {
 950                 data0 = ((u64)&xcall_flush_dcache_page_spitfire);
 951                 if (page_mapping(page) != NULL)
 952                         data0 |= ((u64)1 << 32);
 953         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 954 #ifdef DCACHE_ALIASING_POSSIBLE
 955                 data0 = ((u64)&xcall_flush_dcache_page_cheetah);
 956 #endif
 957         }
 958         if (data0) {
 959                 xcall_deliver(data0, __pa(pg_addr),
 960                               (u64) pg_addr, cpu_online_mask);
 961 #ifdef CONFIG_DEBUG_DCFLUSH
 962                 atomic_inc(&dcpage_flushes_xcall);
 963 #endif
 964         }
 965         __local_flush_dcache_page(page);
 966
 967         preempt_enable();
 968 }
 969
 970 void __irq_entry smp_new_mmu_context_version_client(int irq, struct pt_regs *regs)
 971 {
 972         struct mm_struct *mm;
 973         unsigned long flags;
 974
 975         clear_softint(1 << irq);
 976
 977         /* See if we need to allocate a new TLB context because
 978          * the version of the one we are using is now out of date.
 979          */
 980         mm = current->active_mm;
 981         if (unlikely(!mm || (mm == &init_mm)))
 982                 return;
 983
 984         spin_lock_irqsave(&mm->context.lock, flags);
 985
 986         if (unlikely(!CTX_VALID(mm->context)))
 987                 get_new_mmu_context(mm);
 988
 989         spin_unlock_irqrestore(&mm->context.lock, flags);
 990
 991         load_secondary_context(mm);
 992         __flush_tlb_mm(CTX_HWBITS(mm->context),
 993                        SECONDARY_CONTEXT);
 994 }
 995
 996 void smp_new_mmu_context_version(void)
 997 {
 998         smp_cross_call(&xcall_new_mmu_context_version, 0, 0, 0);
 999 }
1000
1001 #ifdef CONFIG_KGDB
1002 void kgdb_roundup_cpus(unsigned long flags)
1003 {
1004         smp_cross_call(&xcall_kgdb_capture, 0, 0, 0);
1005 }
1006 #endif
1007
1008 void smp_fetch_global_regs(void)
1009 {
1010         smp_cross_call(&xcall_fetch_glob_regs, 0, 0, 0);
1011 }
1012
1013 void smp_fetch_global_pmu(void)
1014 {
1015         if (tlb_type == hypervisor &&
1016             sun4v_chip_type >= SUN4V_CHIP_NIAGARA4)
1017                 smp_cross_call(&xcall_fetch_glob_pmu_n4, 0, 0, 0);
1018         else
1019                 smp_cross_call(&xcall_fetch_glob_pmu, 0, 0, 0);
1020 }
1021
1022 /* We know that the window frames of the user have been flushed
1023  * to the stack before we get here because all callers of us
1024  * are flush_tlb_*() routines, and these run after flush_cache_*()
1025  * which performs the flushw.
1026  *
1027  * The SMP TLB coherency scheme we use works as follows:
1028  *
1029  * 1) mm->cpu_vm_mask is a bit mask of which cpus an address
1030  *    space has (potentially) executed on, this is the heuristic
1031  *    we use to avoid doing cross calls.
1032  *
1033  *    Also, for flushing from kswapd and also for clones, we
1034  *    use cpu_vm_mask as the list of cpus to make run the TLB.
1035  *
1036  * 2) TLB context numbers are shared globally across all processors
1037  *    in the system, this allows us to play several games to avoid
1038  *    cross calls.
1039  *
1040  *    One invariant is that when a cpu switches to a process, and
1041  *    that processes tsk->active_mm->cpu_vm_mask does not have the
1042  *    current cpu's bit set, that tlb context is flushed locally.
1043  *
1044  *    If the address space is non-shared (ie. mm->count == 1) we avoid
1045  *    cross calls when we want to flush the currently running process's
1046  *    tlb state.  This is done by clearing all cpu bits except the current
1047  *    processor's in current->mm->cpu_vm_mask and performing the
1048  *    flush locally only.  This will force any subsequent cpus which run
1049  *    this task to flush the context from the local tlb if the process
1050  *    migrates to another cpu (again).
1051  *
1052  * 3) For shared address spaces (threads) and swapping we bite the
1053  *    bullet for most cases and perform the cross call (but only to
1054  *    the cpus listed in cpu_vm_mask).
1055  *
1056  *    The performance gain from "optimizing" away the cross call for threads is
1057  *    questionable (in theory the big win for threads is the massive sharing of
1058  *    address space state across processors).
1059  */
1060
1061 /* This currently is only used by the hugetlb arch pre-fault
1062  * hook on UltraSPARC-III+ and later when changing the pagesize
1063  * bits of the context register for an address space.
1064  */
1065 void smp_flush_tlb_mm(struct mm_struct *mm)
1066 {
1067         u32 ctx = CTX_HWBITS(mm->context);
1068         int cpu = get_cpu();
1069
1070         if (atomic_read(&mm->mm_users) == 1) {
1071                 cpumask_copy(mm_cpumask(mm), cpumask_of(cpu));
1072                 goto local_flush_and_out;
1073         }
1074
1075         smp_cross_call_masked(&xcall_flush_tlb_mm,
1076                               ctx, 0, 0,
1077                               mm_cpumask(mm));
1078
1079 local_flush_and_out:
1080         __flush_tlb_mm(ctx, SECONDARY_CONTEXT);
1081
1082         put_cpu();
1083 }
1084
1085 struct tlb_pending_info {
1086         unsigned long ctx;
1087         unsigned long nr;
1088         unsigned long *vaddrs;
1089 };
1090
1091 static void tlb_pending_func(void *info)
1092 {
1093         struct tlb_pending_info *t = info;
1094
1095         __flush_tlb_pending(t->ctx, t->nr, t->vaddrs);
1096 }
1097
1098 void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs)
1099 {
1100         u32 ctx = CTX_HWBITS(mm->context);
1101         struct tlb_pending_info info;
1102         int cpu = get_cpu();
1103
1104         info.ctx = ctx;
1105         info.nr = nr;
1106         info.vaddrs = vaddrs;
1107
1108         if (mm == current->mm && atomic_read(&mm->mm_users) == 1)
1109                 cpumask_copy(mm_cpumask(mm), cpumask_of(cpu));
1110         else
1111                 smp_call_function_many(mm_cpumask(mm), tlb_pending_func,
1112                                        &info, 1);
1113
1114         __flush_tlb_pending(ctx, nr, vaddrs);
1115
1116         put_cpu();
1117 }
1118
1119 void smp_flush_tlb_page(struct mm_struct *mm, unsigned long vaddr)
1120 {
1121         unsigned long context = CTX_HWBITS(mm->context);
1122         int cpu = get_cpu();
1123
1124         if (mm == current->mm && atomic_read(&mm->mm_users) == 1)
1125                 cpumask_copy(mm_cpumask(mm), cpumask_of(cpu));
1126         else
1127                 smp_cross_call_masked(&xcall_flush_tlb_page,
1128                                       context, vaddr, 0,
1129                                       mm_cpumask(mm));
1130         __flush_tlb_page(context, vaddr);
1131
1132         put_cpu();
1133 }
1134
1135 void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end)
1136 {
1137         start &= PAGE_MASK;
1138         end    = PAGE_ALIGN(end);
1139         if (start != end) {
1140                 smp_cross_call(&xcall_flush_tlb_kernel_range,
1141                                0, start, end);
1142
1143                 __flush_tlb_kernel_range(start, end);
1144         }
1145 }
1146
1147 /* CPU capture. */
1148 /* #define CAPTURE_DEBUG */
1149 extern unsigned long xcall_capture;
1150
1151 static atomic_t smp_capture_depth = ATOMIC_INIT(0);
1152 static atomic_t smp_capture_registry = ATOMIC_INIT(0);
1153 static unsigned long penguins_are_doing_time;
1154
1155 void smp_capture(void)
1156 {
1157         int result = atomic_add_ret(1, &smp_capture_depth);
1158
1159         if (result == 1) {
1160                 int ncpus = num_online_cpus();
1161
1162 #ifdef CAPTURE_DEBUG
1163                 printk("CPU[%d]: Sending penguins to jail...",
1164                        smp_processor_id());
1165 #endif
1166                 penguins_are_doing_time = 1;
1167                 atomic_inc(&smp_capture_registry);
1168                 smp_cross_call(&xcall_capture, 0, 0, 0);
1169                 while (atomic_read(&smp_capture_registry) != ncpus)
1170                         rmb();
1171 #ifdef CAPTURE_DEBUG
1172                 printk("done\n");
1173 #endif
1174         }
1175 }
1176
1177 void smp_release(void)
1178 {
1179         if (atomic_dec_and_test(&smp_capture_depth)) {
1180 #ifdef CAPTURE_DEBUG
1181                 printk("CPU[%d]: Giving pardon to "
1182                        "imprisoned penguins\n",
1183                        smp_processor_id());
1184 #endif
1185                 penguins_are_doing_time = 0;
1186                 membar_safe("#StoreLoad");
1187                 atomic_dec(&smp_capture_registry);
1188         }
1189 }
1190
1191 /* Imprisoned penguins run with %pil == PIL_NORMAL_MAX, but PSTATE_IE
1192  * set, so they can service tlb flush xcalls...
1193  */
1194 extern void prom_world(int);
1195
1196 void __irq_entry smp_penguin_jailcell(int irq, struct pt_regs *regs)
1197 {
1198         clear_softint(1 << irq);
1199
1200         preempt_disable();
1201
1202         __asm__ __volatile__("flushw");
1203         prom_world(1);
1204         atomic_inc(&smp_capture_registry);
1205         membar_safe("#StoreLoad");
1206         while (penguins_are_doing_time)
1207                 rmb();
1208         atomic_dec(&smp_capture_registry);
1209         prom_world(0);
1210
1211         preempt_enable();
1212 }
1213
1214 /* /proc/profile writes can call this, don't __init it please. */
1215 int setup_profiling_timer(unsigned int multiplier)
1216 {
1217         return -EINVAL;
1218 }
1219
1220 void __init smp_prepare_cpus(unsigned int max_cpus)
1221 {
1222 }
1223
1224 void smp_prepare_boot_cpu(void)
1225 {
1226 }
1227
1228 void __init smp_setup_processor_id(void)
1229 {
1230         if (tlb_type == spitfire)
1231                 xcall_deliver_impl = spitfire_xcall_deliver;
1232         else if (tlb_type == cheetah || tlb_type == cheetah_plus)
1233                 xcall_deliver_impl = cheetah_xcall_deliver;
1234         else
1235                 xcall_deliver_impl = hypervisor_xcall_deliver;
1236 }
1237
1238 void smp_fill_in_sib_core_maps(void)
1239 {
1240         unsigned int i;
1241
1242         for_each_present_cpu(i) {
1243                 unsigned int j;
1244
1245                 cpumask_clear(&cpu_core_map[i]);
1246                 if (cpu_data(i).core_id == 0) {
1247                         cpumask_set_cpu(i, &cpu_core_map[i]);
1248                         continue;
1249                 }
1250
1251                 for_each_present_cpu(j) {
1252                         if (cpu_data(i).core_id ==
1253                             cpu_data(j).core_id)
1254                                 cpumask_set_cpu(j, &cpu_core_map[i]);
1255                 }
1256         }
1257
1258         for_each_present_cpu(i) {
1259                 unsigned int j;
1260
1261                 cpumask_clear(&per_cpu(cpu_sibling_map, i));
1262                 if (cpu_data(i).proc_id == -1) {
1263                         cpumask_set_cpu(i, &per_cpu(cpu_sibling_map, i));
1264                         continue;
1265                 }
1266
1267                 for_each_present_cpu(j) {
1268                         if (cpu_data(i).proc_id ==
1269                             cpu_data(j).proc_id)
1270                                 cpumask_set_cpu(j, &per_cpu(cpu_sibling_map, i));
1271                 }
1272         }
1273 }
1274
1275 int __cpu_up(unsigned int cpu, struct task_struct *tidle)
1276 {
1277         int ret = smp_boot_one_cpu(cpu, tidle);
1278
1279         if (!ret) {
1280                 cpumask_set_cpu(cpu, &smp_commenced_mask);
1281                 while (!cpu_online(cpu))
1282                         mb();
1283                 if (!cpu_online(cpu)) {
1284                         ret = -ENODEV;
1285                 } else {
1286                         /* On SUN4V, writes to %tick and %stick are
1287                          * not allowed.
1288                          */
1289                         if (tlb_type != hypervisor)
1290                                 smp_synchronize_one_tick(cpu);
1291                 }
1292         }
1293         return ret;
1294 }
1295
1296 #ifdef CONFIG_HOTPLUG_CPU
1297 void cpu_play_dead(void)
1298 {
1299         int cpu = smp_processor_id();
1300         unsigned long pstate;
1301
1302         idle_task_exit();
1303
1304         if (tlb_type == hypervisor) {
1305                 struct trap_per_cpu *tb = &trap_block[cpu];
1306
1307                 sun4v_cpu_qconf(HV_CPU_QUEUE_CPU_MONDO,
1308                                 tb->cpu_mondo_pa, 0);
1309                 sun4v_cpu_qconf(HV_CPU_QUEUE_DEVICE_MONDO,
1310                                 tb->dev_mondo_pa, 0);
1311                 sun4v_cpu_qconf(HV_CPU_QUEUE_RES_ERROR,
1312                                 tb->resum_mondo_pa, 0);
1313                 sun4v_cpu_qconf(HV_CPU_QUEUE_NONRES_ERROR,
1314                                 tb->nonresum_mondo_pa, 0);
1315         }
1316
1317         cpumask_clear_cpu(cpu, &smp_commenced_mask);
1318         membar_safe("#Sync");
1319
1320         local_irq_disable();
1321
1322         __asm__ __volatile__(
1323                 "rdpr   %%pstate, %0\n\t"
1324                 "wrpr   %0, %1, %%pstate"
1325                 : "=r" (pstate)
1326                 : "i" (PSTATE_IE));
1327
1328         while (1)
1329                 barrier();
1330 }
1331
1332 int __cpu_disable(void)
1333 {
1334         int cpu = smp_processor_id();
1335         cpuinfo_sparc *c;
1336         int i;
1337
1338         for_each_cpu(i, &cpu_core_map[cpu])
1339                 cpumask_clear_cpu(cpu, &cpu_core_map[i]);
1340         cpumask_clear(&cpu_core_map[cpu]);
1341
1342         for_each_cpu(i, &per_cpu(cpu_sibling_map, cpu))
1343                 cpumask_clear_cpu(cpu, &per_cpu(cpu_sibling_map, i));
1344         cpumask_clear(&per_cpu(cpu_sibling_map, cpu));
1345
1346         c = &cpu_data(cpu);
1347
1348         c->core_id = 0;
1349         c->proc_id = -1;
1350
1351         smp_wmb();
1352
1353         /* Make sure no interrupts point to this cpu.  */
1354         fixup_irqs();
1355
1356         local_irq_enable();
1357         mdelay(1);
1358         local_irq_disable();
1359
1360         set_cpu_online(cpu, false);
1361
1362         cpu_map_rebuild();
1363
1364         return 0;
1365 }
1366
1367 void __cpu_die(unsigned int cpu)
1368 {
1369         int i;
1370
1371         for (i = 0; i < 100; i++) {
1372                 smp_rmb();
1373                 if (!cpumask_test_cpu(cpu, &smp_commenced_mask))
1374                         break;
1375                 msleep(100);
1376         }
1377         if (cpumask_test_cpu(cpu, &smp_commenced_mask)) {
1378                 printk(KERN_ERR "CPU %u didn't die...\n", cpu);
1379         } else {
1380 #if defined(CONFIG_SUN_LDOMS)
1381                 unsigned long hv_err;
1382                 int limit = 100;
1383
1384                 do {
1385                         hv_err = sun4v_cpu_stop(cpu);
1386                         if (hv_err == HV_EOK) {
1387                                 set_cpu_present(cpu, false);
1388                                 break;
1389                         }
1390                 } while (--limit > 0);
1391                 if (limit <= 0) {
1392                         printk(KERN_ERR "sun4v_cpu_stop() fails err=%lu\n",
1393                                hv_err);
1394                 }
1395 #endif
1396         }
1397 }
1398 #endif
1399
1400 void __init smp_cpus_done(unsigned int max_cpus)
1401 {
1402 }
1403
1404 void smp_send_reschedule(int cpu)
1405 {
1406         if (cpu == smp_processor_id()) {
1407                 WARN_ON_ONCE(preemptible());
1408                 set_softint(1 << PIL_SMP_RECEIVE_SIGNAL);
1409         } else {
1410                 xcall_deliver((u64) &xcall_receive_signal,
1411                               0, 0, cpumask_of(cpu));
1412         }
1413 }
1414
1415 void __irq_entry smp_receive_signal_client(int irq, struct pt_regs *regs)
1416 {
1417         clear_softint(1 << irq);
1418         scheduler_ipi();
1419 }
1420
1421 /* This is a nop because we capture all other cpus
1422  * anyways when making the PROM active.
1423  */
1424 void smp_send_stop(void)
1425 {
1426 }
1427
1428 /**
1429  * pcpu_alloc_bootmem - NUMA friendly alloc_bootmem wrapper for percpu
1430  * @cpu: cpu to allocate for
1431  * @size: size allocation in bytes
1432  * @align: alignment
1433  *
1434  * Allocate @size bytes aligned at @align for cpu @cpu.  This wrapper
1435  * does the right thing for NUMA regardless of the current
1436  * configuration.
1437  *
1438  * RETURNS:
1439  * Pointer to the allocated area on success, NULL on failure.
1440  */
1441 static void * __init pcpu_alloc_bootmem(unsigned int cpu, size_t size,
1442                                         size_t align)
1443 {
1444         const unsigned long goal = __pa(MAX_DMA_ADDRESS);
1445 #ifdef CONFIG_NEED_MULTIPLE_NODES
1446         int node = cpu_to_node(cpu);
1447         void *ptr;
1448
1449         if (!node_online(node) || !NODE_DATA(node)) {
1450                 ptr = __alloc_bootmem(size, align, goal);
1451                 pr_info("cpu %d has no node %d or node-local memory\n",
1452                         cpu, node);
1453                 pr_debug("per cpu data for cpu%d %lu bytes at %016lx\n",
1454                          cpu, size, __pa(ptr));
1455         } else {
1456                 ptr = __alloc_bootmem_node(NODE_DATA(node),
1457                                            size, align, goal);
1458                 pr_debug("per cpu data for cpu%d %lu bytes on node%d at "
1459                          "%016lx\n", cpu, size, node, __pa(ptr));
1460         }
1461         return ptr;
1462 #else
1463         return __alloc_bootmem(size, align, goal);
1464 #endif
1465 }
1466
1467 static void __init pcpu_free_bootmem(void *ptr, size_t size)
1468 {
1469         free_bootmem(__pa(ptr), size);
1470 }
1471
1472 static int __init pcpu_cpu_distance(unsigned int from, unsigned int to)
1473 {
1474         if (cpu_to_node(from) == cpu_to_node(to))
1475                 return LOCAL_DISTANCE;
1476         else
1477                 return REMOTE_DISTANCE;
1478 }
1479
1480 static void __init pcpu_populate_pte(unsigned long addr)
1481 {
1482         pgd_t *pgd = pgd_offset_k(addr);
1483         pud_t *pud;
1484         pmd_t *pmd;
1485
1486         if (pgd_none(*pgd)) {
1487                 pud_t *new;
1488
1489                 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1490                 pgd_populate(&init_mm, pgd, new);
1491         }
1492
1493         pud = pud_offset(pgd, addr);
1494         if (pud_none(*pud)) {
1495                 pmd_t *new;
1496
1497                 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1498                 pud_populate(&init_mm, pud, new);
1499         }
1500
1501         pmd = pmd_offset(pud, addr);
1502         if (!pmd_present(*pmd)) {
1503                 pte_t *new;
1504
1505                 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1506                 pmd_populate_kernel(&init_mm, pmd, new);
1507         }
1508 }
1509
1510 void __init setup_per_cpu_areas(void)
1511 {
1512         unsigned long delta;
1513         unsigned int cpu;
1514         int rc = -EINVAL;
1515
1516         if (pcpu_chosen_fc != PCPU_FC_PAGE) {
1517                 rc = pcpu_embed_first_chunk(PERCPU_MODULE_RESERVE,
1518                                             PERCPU_DYNAMIC_RESERVE, 4 << 20,
1519                                             pcpu_cpu_distance,
1520                                             pcpu_alloc_bootmem,
1521                                             pcpu_free_bootmem);
1522                 if (rc)
1523                         pr_warning("PERCPU: %s allocator failed (%d), "
1524                                    "falling back to page size\n",
1525                                    pcpu_fc_names[pcpu_chosen_fc], rc);
1526         }
1527         if (rc < 0)
1528                 rc = pcpu_page_first_chunk(PERCPU_MODULE_RESERVE,
1529                                            pcpu_alloc_bootmem,
1530                                            pcpu_free_bootmem,
1531                                            pcpu_populate_pte);
1532         if (rc < 0)
1533                 panic("cannot initialize percpu area (err=%d)", rc);
1534
1535         delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
1536         for_each_possible_cpu(cpu)
1537                 __per_cpu_offset(cpu) = delta + pcpu_unit_offsets[cpu];
1538
1539         /* Setup %g5 for the boot cpu.  */
1540         __local_per_cpu_offset = __per_cpu_offset(smp_processor_id());
1541
1542         of_fill_in_cpu_data();
1543         if (tlb_type == hypervisor)
1544                 mdesc_fill_in_cpu_data(cpu_all_mask);
1545 }