2 * Performance event support framework for SuperH hardware counters.
4 * Copyright (C) 2009 Paul Mundt
6 * Heavily based on the x86 and PowerPC implementations.
9 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
10 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
11 * Copyright (C) 2009 Jaswinder Singh Rajput
12 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
13 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
14 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
17 * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
19 * This file is subject to the terms and conditions of the GNU General Public
20 * License. See the file "COPYING" in the main directory of this archive
23 #include <linux/kernel.h>
24 #include <linux/init.h>
26 #include <linux/irq.h>
27 #include <linux/perf_event.h>
28 #include <asm/processor.h>
30 struct cpu_hw_events {
31 struct perf_event *events[MAX_HWEVENTS];
32 unsigned long used_mask[BITS_TO_LONGS(MAX_HWEVENTS)];
33 unsigned long active_mask[BITS_TO_LONGS(MAX_HWEVENTS)];
36 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
38 static struct sh_pmu *sh_pmu __read_mostly;
40 /* Number of perf_events counting hardware events */
41 static atomic_t num_events;
42 /* Used to avoid races in calling reserve/release_pmc_hardware */
43 static DEFINE_MUTEX(pmc_reserve_mutex);
46 * Stub these out for now, do something more profound later.
48 int reserve_pmc_hardware(void)
53 void release_pmc_hardware(void)
57 static inline int sh_pmu_initialized(void)
63 * Release the PMU if this is the last perf_event.
65 static void hw_perf_event_destroy(struct perf_event *event)
67 if (!atomic_add_unless(&num_events, -1, 1)) {
68 mutex_lock(&pmc_reserve_mutex);
69 if (atomic_dec_return(&num_events) == 0)
70 release_pmc_hardware();
71 mutex_unlock(&pmc_reserve_mutex);
75 static int hw_perf_cache_event(int config, int *evp)
77 unsigned long type, op, result;
80 if (!sh_pmu->cache_events)
85 op = (config >> 8) & 0xff;
86 result = (config >> 16) & 0xff;
88 if (type >= PERF_COUNT_HW_CACHE_MAX ||
89 op >= PERF_COUNT_HW_CACHE_OP_MAX ||
90 result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
93 ev = (*sh_pmu->cache_events)[type][op][result];
102 static int __hw_perf_event_init(struct perf_event *event)
104 struct perf_event_attr *attr = &event->attr;
105 struct hw_perf_event *hwc = &event->hw;
109 if (!sh_pmu_initialized())
113 * All of the on-chip counters are "limited", in that they have
114 * no interrupts, and are therefore unable to do sampling without
115 * further work and timer assistance.
117 if (hwc->sample_period)
121 * See if we need to reserve the counter.
123 * If no events are currently in use, then we have to take a
124 * mutex to ensure that we don't race with another task doing
125 * reserve_pmc_hardware or release_pmc_hardware.
128 if (!atomic_inc_not_zero(&num_events)) {
129 mutex_lock(&pmc_reserve_mutex);
130 if (atomic_read(&num_events) == 0 &&
131 reserve_pmc_hardware())
134 atomic_inc(&num_events);
135 mutex_unlock(&pmc_reserve_mutex);
141 event->destroy = hw_perf_event_destroy;
143 switch (attr->type) {
145 config = attr->config & sh_pmu->raw_event_mask;
147 case PERF_TYPE_HW_CACHE:
148 err = hw_perf_cache_event(attr->config, &config);
152 case PERF_TYPE_HARDWARE:
153 if (attr->config >= sh_pmu->max_events)
156 config = sh_pmu->event_map(attr->config);
163 hwc->config |= config;
168 static void sh_perf_event_update(struct perf_event *event,
169 struct hw_perf_event *hwc, int idx)
171 u64 prev_raw_count, new_raw_count;
176 * Depending on the counter configuration, they may or may not
177 * be chained, in which case the previous counter value can be
178 * updated underneath us if the lower-half overflows.
180 * Our tactic to handle this is to first atomically read and
181 * exchange a new raw count - then add that new-prev delta
182 * count to the generic counter atomically.
184 * As there is no interrupt associated with the overflow events,
185 * this is the simplest approach for maintaining consistency.
188 prev_raw_count = local64_read(&hwc->prev_count);
189 new_raw_count = sh_pmu->read(idx);
191 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
192 new_raw_count) != prev_raw_count)
196 * Now we have the new raw value and have updated the prev
197 * timestamp already. We can now calculate the elapsed delta
198 * (counter-)time and add that to the generic counter.
200 * Careful, not all hw sign-extends above the physical width
203 delta = (new_raw_count << shift) - (prev_raw_count << shift);
206 local64_add(delta, &event->count);
209 static void sh_pmu_disable(struct perf_event *event)
211 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
212 struct hw_perf_event *hwc = &event->hw;
215 clear_bit(idx, cpuc->active_mask);
216 sh_pmu->disable(hwc, idx);
220 sh_perf_event_update(event, &event->hw, idx);
222 cpuc->events[idx] = NULL;
223 clear_bit(idx, cpuc->used_mask);
225 perf_event_update_userpage(event);
228 static int sh_pmu_enable(struct perf_event *event)
230 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
231 struct hw_perf_event *hwc = &event->hw;
235 perf_pmu_disable(event->pmu);
237 if (test_and_set_bit(idx, cpuc->used_mask)) {
238 idx = find_first_zero_bit(cpuc->used_mask, sh_pmu->num_events);
239 if (idx == sh_pmu->num_events)
242 set_bit(idx, cpuc->used_mask);
246 sh_pmu->disable(hwc, idx);
248 cpuc->events[idx] = event;
249 set_bit(idx, cpuc->active_mask);
251 sh_pmu->enable(hwc, idx);
253 perf_event_update_userpage(event);
256 perf_pmu_enable(event->pmu);
260 static void sh_pmu_read(struct perf_event *event)
262 sh_perf_event_update(event, &event->hw, event->hw.idx);
265 static int sh_pmu_event_init(struct perf_event *event)
269 switch (event->attr.type) {
271 case PERF_TYPE_HW_CACHE:
272 case PERF_TYPE_HARDWARE:
273 err = __hw_perf_event_init(event);
282 event->destroy(event);
288 static void sh_pmu_pmu_enable(struct pmu *pmu)
290 if (!sh_pmu_initialized())
293 sh_pmu->enable_all();
296 static void sh_pmu_pmu_disable(struct pmu *pmu)
298 if (!sh_pmu_initialized())
301 sh_pmu->disable_all();
304 static struct pmu pmu = {
305 .pmu_enable = sh_pmu_pmu_enable,
306 .pmu_disable = sh_pmu_pmu_disable,
307 .event_init = sh_pmu_event_init,
308 .enable = sh_pmu_enable,
309 .disable = sh_pmu_disable,
313 static void sh_pmu_setup(int cpu)
315 struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu);
317 memset(cpuhw, 0, sizeof(struct cpu_hw_events));
321 sh_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
323 unsigned int cpu = (long)hcpu;
325 switch (action & ~CPU_TASKS_FROZEN) {
337 int __cpuinit register_sh_pmu(struct sh_pmu *pmu)
343 pr_info("Performance Events: %s support registered\n", pmu->name);
345 WARN_ON(pmu->num_events > MAX_HWEVENTS);
347 perf_pmu_register(&pmu);
348 perf_cpu_notifier(sh_pmu_notifier);