1 // SPDX-License-Identifier: GPL-2.0
3 * Disassemble SuperH instructions.
5 * Copyright (C) 1999 kaz Kojima
6 * Copyright (C) 2008 Paul Mundt
8 #include <linux/kernel.h>
9 #include <linux/string.h>
10 #include <linux/uaccess.h>
12 #include <asm/ptrace.h>
15 * Format of an instruction in memory.
18 HEX_0, HEX_1, HEX_2, HEX_3, HEX_4, HEX_5, HEX_6, HEX_7,
19 HEX_8, HEX_9, HEX_A, HEX_B, HEX_C, HEX_D, HEX_E, HEX_F,
20 REG_N, REG_M, REG_NM, REG_B,
23 IMM_4, IMM_4BY2, IMM_4BY4, PCRELIMM_8BY2, PCRELIMM_8BY4,
24 IMM_8, IMM_8BY2, IMM_8BY4,
28 A_END, A_BDISP12, A_BDISP8,
30 A_DISP_GBR, A_DISP_PC, A_DISP_REG_M, A_DISP_REG_N,
34 A_IND_M, A_IND_N, A_IND_R0_REG_M, A_IND_R0_REG_N,
36 A_PR, A_R0, A_R0_GBR, A_REG_M, A_REG_N, A_REG_B,
37 A_SR, A_VBR, A_SSR, A_SPC, A_SGR, A_DBR,
38 F_REG_N, F_REG_M, D_REG_N, D_REG_M,
39 X_REG_N, /* Only used for argument parsing */
40 X_REG_M, /* Only used for argument parsing */
41 DX_REG_N, DX_REG_M, V_REG_N, V_REG_M,
45 FPUL_N, FPUL_M, FPSCR_N, FPSCR_M,
48 static struct sh_opcode_info {
51 sh_nibble_type nibbles[4];
53 {"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM_8}},
54 {"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}},
55 {"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}},
56 {"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}},
57 {"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM_8}},
58 {"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}},
59 {"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM_8}},
60 {"bra",{A_BDISP12},{HEX_A,BRANCH_12}},
61 {"bsr",{A_BDISP12},{HEX_B,BRANCH_12}},
62 {"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}},
63 {"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}},
64 {"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}},
65 {"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}},
66 {"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}},
67 {"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}},
68 {"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}},
69 {"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}},
70 {"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}},
71 {"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM_8}},
72 {"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}},
73 {"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}},
74 {"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}},
75 {"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}},
76 {"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}},
77 {"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}},
78 {"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}},
79 {"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}},
80 {"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}},
81 {"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}},
82 {"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}},
83 {"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}},
84 {"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}},
85 {"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}},
86 {"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}},
87 {"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}},
88 {"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}},
89 {"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}},
90 {"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}},
91 {"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}},
92 {"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}},
93 {"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}},
94 {"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_7,HEX_E}},
95 {"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}},
96 {"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}},
97 {"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}},
98 {"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}},
99 {"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}},
100 {"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}},
101 {"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_7,HEX_7}},
102 {"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}},
103 {"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}},
104 {"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}},
105 {"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}},
106 {"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}},
107 {"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}},
108 {"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}},
109 {"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}},
110 {"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}},
111 {"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}},
112 {"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}},
113 {"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}},
114 {"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}},
115 {"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM_8}},
116 {"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}},
117 {"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}},
118 {"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}},
119 {"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}},
120 {"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM_4}},
121 {"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM_8}},
122 {"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}},
123 {"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}},
124 {"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}},
125 {"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM_4}},
126 {"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM_8}},
127 {"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM_4BY4}},
128 {"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}},
129 {"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}},
130 {"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}},
131 {"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM_4BY4}},
132 {"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM_8BY4}},
133 {"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}},
134 {"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}},
135 {"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}},
136 {"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}},
137 {"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM_8BY4}},
138 {"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}},
139 {"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}},
140 {"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}},
141 {"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM_4BY2}},
142 {"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM_8BY2}},
143 {"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}},
144 {"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}},
145 {"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}},
146 {"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}},
147 {"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM_4BY2}},
148 {"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM_8BY2}},
149 {"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}},
150 {"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}},
151 {"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}},
152 {"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}},
153 {"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}},
154 {"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}},
155 {"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}},
156 {"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}},
157 {"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}},
158 {"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}},
159 {"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}},
160 {"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}},
161 {"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}},
162 {"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM_8}},
163 {"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}},
164 {"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM_8}},
165 {"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}},
166 {"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}},
167 {"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}},
168 {"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}},
169 {"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}},
170 {"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}},
171 {"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}},
172 {"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}},
173 {"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}},
174 {"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}},
175 {"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}},
176 {"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}},
177 {"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}},
178 {"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}},
179 {"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}},
180 {"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}},
181 {"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}},
182 {"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}},
183 {"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}},
184 {"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}},
185 {"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}},
186 {"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}},
187 {"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}},
188 {"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}},
189 {"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}},
190 {"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}},
191 {"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}},
192 {"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_2}},
193 {"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_2}},
194 {"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}},
195 {"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}},
196 {"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}},
197 {"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}},
198 {"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}},
199 {"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}},
200 {"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_3}},
201 {"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_3}},
202 {"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}},
203 {"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}},
204 {"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}},
205 {"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}},
206 {"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}},
207 {"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}},
208 {"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}},
209 {"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}},
210 {"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}},
211 {"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}},
212 {"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}},
213 {"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}},
214 {"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}},
215 {"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}},
216 {"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}},
217 {"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}},
218 {"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}},
219 {"trapa",{A_IMM},{HEX_C,HEX_3,IMM_8}},
220 {"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM_8}},
221 {"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}},
222 {"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM_8}},
223 {"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM_8}},
224 {"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}},
225 {"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM_8}},
226 {"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}},
227 {"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}},
228 {"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}},
229 {"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}},
230 {"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}},
231 {"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}},
232 {"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}},
233 {"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}},
234 {"fabs",{FD_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}},
235 {"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}},
236 {"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}},
237 {"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}},
238 {"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}},
239 {"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}},
240 {"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}},
241 {"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_B,HEX_D}},
242 {"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_A,HEX_D}},
243 {"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}},
244 {"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}},
245 {"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}},
246 {"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}},
247 {"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}},
248 {"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}},
249 {"float",{FPUL_M,FD_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}},
250 {"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}},
251 {"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}},
252 {"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}},
253 {"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}},
254 {"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}},
255 {"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}},
256 {"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}},
257 {"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}},
258 {"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}},
259 {"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}},
260 {"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}},
261 {"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}},
262 {"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}},
263 {"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}},
264 {"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}},
265 {"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}},
266 {"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}},
267 {"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}},
268 {"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}},
269 {"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}},
270 {"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}},
271 {"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}},
272 {"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}},
273 {"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}},
274 {"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}},
275 {"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}},
276 {"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}},
277 {"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}},
278 {"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}},
279 {"fneg",{FD_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}},
280 {"frchg",{0},{HEX_F,HEX_B,HEX_F,HEX_D}},
281 {"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}},
282 {"fsqrt",{FD_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}},
283 {"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}},
284 {"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}},
285 {"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}},
286 {"ftrc",{FD_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}},
287 {"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_NM,HEX_F,HEX_D}},
291 static void print_sh_insn(u32 memaddr, u16 insn)
294 int nibs[4] = { (insn >> 12) & 0xf, (insn >> 8) & 0xf, (insn >> 4) & 0xf, insn & 0xf};
296 struct sh_opcode_info *op = sh_table;
298 for (; op->name; op++) {
305 int disp_pc_addr = 0;
307 for (n = 0; n < 4; n++) {
308 int i = op->nibbles[n];
317 imm = (nibs[2] << 4) | (nibs[3]);
320 imm = ((char)imm) * 2 + 4 ;
323 imm = ((nibs[1]) << 8) | (nibs[2] << 4) | (nibs[3]);
338 imm = (nibs[2] << 4) | nibs[3];
341 imm = ((nibs[2] << 4) | nibs[3]) <<1;
345 imm = ((nibs[2] << 4) | nibs[3]) <<2;
349 imm = ((nibs[2] << 4) | nibs[3]) <<1;
352 imm = ((nibs[2] << 4) | nibs[3]) <<2;
355 imm = (nibs[2] << 4) | (nibs[3]);
367 rn = (nibs[n] & 0xc) >> 2;
368 rm = (nibs[n] & 0x3);
379 printk("%-8s ", op->name);
380 lastsp = (op->arg[0] == A_END);
382 for (n = 0; n < 6 && op->arg[n] != A_END; n++) {
383 if (n && op->arg[1] != A_END)
385 switch (op->arg[n]) {
387 printk("#%d", (char)(imm));
405 printk("@(%d,r%d)", imm, rn);
420 printk("@(%d,r%d)", imm, rm);
423 printk("r%d_bank", rb);
427 disp_pc_addr = imm + 4 + (memaddr & relmask);
428 printk("%08x <%pS>", disp_pc_addr,
429 (void *)disp_pc_addr);
432 printk("@(r0,r%d)", rn);
435 printk("@(r0,r%d)", rm);
438 printk("@(%d,gbr)",imm);
445 printk("%08x", imm + memaddr);
486 printk("xd%d", rn & ~1);
489 /* else, fall through */
495 printk("xd%d", rm & ~1);
498 /* else, fall through */
514 printk("fv%d", rn*4);
517 printk("fv%d", rm*4);
527 if (disp_pc && strcmp(op->name, "mova") != 0) {
531 __get_user(val, (u16 *)disp_pc_addr);
533 __get_user(val, (u32 *)disp_pc_addr);
535 printk(" ! %08x <%pS>", val, (void *)val);
544 printk(".word 0x%x%x%x%x", nibs[0], nibs[1], nibs[2], nibs[3]);
547 void show_code(struct pt_regs *regs)
549 unsigned short *pc = (unsigned short *)regs->pc;
557 for (i = -3 ; i < 6 ; i++) {
560 if (__get_user(insn, pc + i)) {
561 printk(" (Bad address in pc)\n");
565 printk("%s%08lx: ", (i ? " ": "->"), (unsigned long)(pc + i));
566 print_sh_insn((unsigned long)(pc + i), insn);