2 * SH5-101/SH5-103 CPU Setup
4 * Copyright (C) 2009 Paul Mundt
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/serial.h>
13 #include <linux/serial_sci.h>
16 #include <linux/sh_timer.h>
17 #include <asm/addrspace.h>
19 static struct plat_sci_port scif0_platform_data = {
20 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
21 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
25 static struct resource scif0_resources[] = {
26 DEFINE_RES_MEM(PHYS_PERIPHERAL_BLOCK + 0x01030000, 0x100),
32 static struct platform_device scif0_device = {
35 .resource = scif0_resources,
36 .num_resources = ARRAY_SIZE(scif0_resources),
38 .platform_data = &scif0_platform_data,
42 static struct resource rtc_resources[] = {
44 .start = PHYS_PERIPHERAL_BLOCK + 0x01040000,
45 .end = PHYS_PERIPHERAL_BLOCK + 0x01040000 + 0x58 - 1,
46 .flags = IORESOURCE_IO,
51 .flags = IORESOURCE_IRQ,
56 .flags = IORESOURCE_IRQ,
61 .flags = IORESOURCE_IRQ,
65 static struct platform_device rtc_device = {
68 .num_resources = ARRAY_SIZE(rtc_resources),
69 .resource = rtc_resources,
72 #define TMU_BLOCK_OFF 0x01020000
73 #define TMU_BASE PHYS_PERIPHERAL_BLOCK + TMU_BLOCK_OFF
74 #define TMU0_BASE (TMU_BASE + 0x8 + (0xc * 0x0))
75 #define TMU1_BASE (TMU_BASE + 0x8 + (0xc * 0x1))
76 #define TMU2_BASE (TMU_BASE + 0x8 + (0xc * 0x2))
78 static struct sh_timer_config tmu0_platform_data = {
79 .channel_offset = 0x04,
81 .clockevent_rating = 200,
84 static struct resource tmu0_resources[] = {
87 .end = TMU0_BASE + 0xc - 1,
88 .flags = IORESOURCE_MEM,
92 .flags = IORESOURCE_IRQ,
96 static struct platform_device tmu0_device = {
100 .platform_data = &tmu0_platform_data,
102 .resource = tmu0_resources,
103 .num_resources = ARRAY_SIZE(tmu0_resources),
106 static struct sh_timer_config tmu1_platform_data = {
107 .channel_offset = 0x10,
109 .clocksource_rating = 200,
112 static struct resource tmu1_resources[] = {
115 .end = TMU1_BASE + 0xc - 1,
116 .flags = IORESOURCE_MEM,
120 .flags = IORESOURCE_IRQ,
124 static struct platform_device tmu1_device = {
128 .platform_data = &tmu1_platform_data,
130 .resource = tmu1_resources,
131 .num_resources = ARRAY_SIZE(tmu1_resources),
134 static struct sh_timer_config tmu2_platform_data = {
135 .channel_offset = 0x1c,
139 static struct resource tmu2_resources[] = {
142 .end = TMU2_BASE + 0xc - 1,
143 .flags = IORESOURCE_MEM,
147 .flags = IORESOURCE_IRQ,
151 static struct platform_device tmu2_device = {
155 .platform_data = &tmu2_platform_data,
157 .resource = tmu2_resources,
158 .num_resources = ARRAY_SIZE(tmu2_resources),
161 static struct platform_device *sh5_early_devices[] __initdata = {
168 static struct platform_device *sh5_devices[] __initdata = {
172 static int __init sh5_devices_setup(void)
176 ret = platform_add_devices(sh5_early_devices,
177 ARRAY_SIZE(sh5_early_devices));
178 if (unlikely(ret != 0))
181 return platform_add_devices(sh5_devices,
182 ARRAY_SIZE(sh5_devices));
184 arch_initcall(sh5_devices_setup);
186 void __init plat_early_device_setup(void)
188 early_platform_add_devices(sh5_early_devices,
189 ARRAY_SIZE(sh5_early_devices));