4 * Copyright (C) 2009 - 2011 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 * Paul Mundt <paul.mundt@renesas.com>
8 * Based on SH7785 Setup
10 * Copyright (C) 2007 Paul Mundt
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file "COPYING" in the main directory of this archive
16 #include <linux/platform_device.h>
17 #include <linux/init.h>
18 #include <linux/serial.h>
19 #include <linux/serial_sci.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/sh_timer.h>
24 #include <linux/sh_dma.h>
25 #include <linux/sh_intc.h>
26 #include <linux/usb/ohci_pdriver.h>
27 #include <cpu/dma-register.h>
28 #include <asm/mmzone.h>
30 static struct plat_sci_port scif0_platform_data = {
31 .flags = UPF_BOOT_AUTOCONF,
32 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
34 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
37 static struct resource scif0_resources[] = {
38 DEFINE_RES_MEM(0xffea0000, 0x100),
39 DEFINE_RES_IRQ(evt2irq(0x700)),
40 DEFINE_RES_IRQ(evt2irq(0x720)),
41 DEFINE_RES_IRQ(evt2irq(0x760)),
42 DEFINE_RES_IRQ(evt2irq(0x740)),
45 static struct platform_device scif0_device = {
48 .resource = scif0_resources,
49 .num_resources = ARRAY_SIZE(scif0_resources),
51 .platform_data = &scif0_platform_data,
56 * The rest of these all have multiplexed IRQs
58 static struct plat_sci_port scif1_platform_data = {
59 .flags = UPF_BOOT_AUTOCONF,
60 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
62 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
65 static struct resource scif1_resources[] = {
66 DEFINE_RES_MEM(0xffeb0000, 0x100),
67 DEFINE_RES_IRQ(evt2irq(0x780)),
70 static struct resource scif1_demux_resources[] = {
71 DEFINE_RES_MEM(0xffeb0000, 0x100),
72 /* Placeholders, see sh7786_devices_setup() */
79 static struct platform_device scif1_device = {
82 .resource = scif1_resources,
83 .num_resources = ARRAY_SIZE(scif1_resources),
85 .platform_data = &scif1_platform_data,
89 static struct plat_sci_port scif2_platform_data = {
90 .flags = UPF_BOOT_AUTOCONF,
91 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
93 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
96 static struct resource scif2_resources[] = {
97 DEFINE_RES_MEM(0xffec0000, 0x100),
98 DEFINE_RES_IRQ(evt2irq(0x840)),
101 static struct platform_device scif2_device = {
104 .resource = scif2_resources,
105 .num_resources = ARRAY_SIZE(scif2_resources),
107 .platform_data = &scif2_platform_data,
111 static struct plat_sci_port scif3_platform_data = {
112 .flags = UPF_BOOT_AUTOCONF,
113 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
115 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
118 static struct resource scif3_resources[] = {
119 DEFINE_RES_MEM(0xffed0000, 0x100),
120 DEFINE_RES_IRQ(evt2irq(0x860)),
123 static struct platform_device scif3_device = {
126 .resource = scif3_resources,
127 .num_resources = ARRAY_SIZE(scif3_resources),
129 .platform_data = &scif3_platform_data,
133 static struct plat_sci_port scif4_platform_data = {
134 .flags = UPF_BOOT_AUTOCONF,
135 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
137 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
140 static struct resource scif4_resources[] = {
141 DEFINE_RES_MEM(0xffee0000, 0x100),
142 DEFINE_RES_IRQ(evt2irq(0x880)),
145 static struct platform_device scif4_device = {
148 .resource = scif4_resources,
149 .num_resources = ARRAY_SIZE(scif4_resources),
151 .platform_data = &scif4_platform_data,
155 static struct plat_sci_port scif5_platform_data = {
156 .flags = UPF_BOOT_AUTOCONF,
157 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
159 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
162 static struct resource scif5_resources[] = {
163 DEFINE_RES_MEM(0xffef0000, 0x100),
164 DEFINE_RES_IRQ(evt2irq(0x8a0)),
167 static struct platform_device scif5_device = {
170 .resource = scif5_resources,
171 .num_resources = ARRAY_SIZE(scif5_resources),
173 .platform_data = &scif5_platform_data,
177 static struct sh_timer_config tmu0_platform_data = {
178 .channel_offset = 0x04,
180 .clockevent_rating = 200,
183 static struct resource tmu0_resources[] = {
187 .flags = IORESOURCE_MEM,
190 .start = evt2irq(0x400),
191 .flags = IORESOURCE_IRQ,
195 static struct platform_device tmu0_device = {
199 .platform_data = &tmu0_platform_data,
201 .resource = tmu0_resources,
202 .num_resources = ARRAY_SIZE(tmu0_resources),
205 static struct sh_timer_config tmu1_platform_data = {
206 .channel_offset = 0x10,
208 .clocksource_rating = 200,
211 static struct resource tmu1_resources[] = {
215 .flags = IORESOURCE_MEM,
218 .start = evt2irq(0x420),
219 .flags = IORESOURCE_IRQ,
223 static struct platform_device tmu1_device = {
227 .platform_data = &tmu1_platform_data,
229 .resource = tmu1_resources,
230 .num_resources = ARRAY_SIZE(tmu1_resources),
233 static struct sh_timer_config tmu2_platform_data = {
234 .channel_offset = 0x1c,
238 static struct resource tmu2_resources[] = {
242 .flags = IORESOURCE_MEM,
245 .start = evt2irq(0x440),
246 .flags = IORESOURCE_IRQ,
250 static struct platform_device tmu2_device = {
254 .platform_data = &tmu2_platform_data,
256 .resource = tmu2_resources,
257 .num_resources = ARRAY_SIZE(tmu2_resources),
260 static struct sh_timer_config tmu3_platform_data = {
261 .channel_offset = 0x04,
265 static struct resource tmu3_resources[] = {
269 .flags = IORESOURCE_MEM,
272 .start = evt2irq(0x480),
273 .flags = IORESOURCE_IRQ,
277 static struct platform_device tmu3_device = {
281 .platform_data = &tmu3_platform_data,
283 .resource = tmu3_resources,
284 .num_resources = ARRAY_SIZE(tmu3_resources),
287 static struct sh_timer_config tmu4_platform_data = {
288 .channel_offset = 0x10,
292 static struct resource tmu4_resources[] = {
296 .flags = IORESOURCE_MEM,
299 .start = evt2irq(0x4a0),
300 .flags = IORESOURCE_IRQ,
304 static struct platform_device tmu4_device = {
308 .platform_data = &tmu4_platform_data,
310 .resource = tmu4_resources,
311 .num_resources = ARRAY_SIZE(tmu4_resources),
314 static struct sh_timer_config tmu5_platform_data = {
315 .channel_offset = 0x1c,
319 static struct resource tmu5_resources[] = {
323 .flags = IORESOURCE_MEM,
326 .start = evt2irq(0x4c0),
327 .flags = IORESOURCE_IRQ,
331 static struct platform_device tmu5_device = {
335 .platform_data = &tmu5_platform_data,
337 .resource = tmu5_resources,
338 .num_resources = ARRAY_SIZE(tmu5_resources),
341 static struct sh_timer_config tmu6_platform_data = {
342 .channel_offset = 0x04,
346 static struct resource tmu6_resources[] = {
350 .flags = IORESOURCE_MEM,
353 .start = evt2irq(0x7a0),
354 .flags = IORESOURCE_IRQ,
358 static struct platform_device tmu6_device = {
362 .platform_data = &tmu6_platform_data,
364 .resource = tmu6_resources,
365 .num_resources = ARRAY_SIZE(tmu6_resources),
368 static struct sh_timer_config tmu7_platform_data = {
369 .channel_offset = 0x10,
373 static struct resource tmu7_resources[] = {
377 .flags = IORESOURCE_MEM,
380 .start = evt2irq(0x7a0),
381 .flags = IORESOURCE_IRQ,
385 static struct platform_device tmu7_device = {
389 .platform_data = &tmu7_platform_data,
391 .resource = tmu7_resources,
392 .num_resources = ARRAY_SIZE(tmu7_resources),
395 static struct sh_timer_config tmu8_platform_data = {
396 .channel_offset = 0x1c,
400 static struct resource tmu8_resources[] = {
404 .flags = IORESOURCE_MEM,
407 .start = evt2irq(0x7a0),
408 .flags = IORESOURCE_IRQ,
412 static struct platform_device tmu8_device = {
416 .platform_data = &tmu8_platform_data,
418 .resource = tmu8_resources,
419 .num_resources = ARRAY_SIZE(tmu8_resources),
422 static struct sh_timer_config tmu9_platform_data = {
423 .channel_offset = 0x04,
427 static struct resource tmu9_resources[] = {
431 .flags = IORESOURCE_MEM,
434 .start = evt2irq(0x7c0),
435 .flags = IORESOURCE_IRQ,
439 static struct platform_device tmu9_device = {
443 .platform_data = &tmu9_platform_data,
445 .resource = tmu9_resources,
446 .num_resources = ARRAY_SIZE(tmu9_resources),
449 static struct sh_timer_config tmu10_platform_data = {
450 .channel_offset = 0x10,
454 static struct resource tmu10_resources[] = {
458 .flags = IORESOURCE_MEM,
461 .start = evt2irq(0x7c0),
462 .flags = IORESOURCE_IRQ,
466 static struct platform_device tmu10_device = {
470 .platform_data = &tmu10_platform_data,
472 .resource = tmu10_resources,
473 .num_resources = ARRAY_SIZE(tmu10_resources),
476 static struct sh_timer_config tmu11_platform_data = {
477 .channel_offset = 0x1c,
481 static struct resource tmu11_resources[] = {
485 .flags = IORESOURCE_MEM,
488 .start = evt2irq(0x7c0),
489 .flags = IORESOURCE_IRQ,
493 static struct platform_device tmu11_device = {
497 .platform_data = &tmu11_platform_data,
499 .resource = tmu11_resources,
500 .num_resources = ARRAY_SIZE(tmu11_resources),
503 static const struct sh_dmae_channel dmac0_channels[] = {
531 static const unsigned int ts_shift[] = TS_SHIFT;
533 static struct sh_dmae_pdata dma0_platform_data = {
534 .channel = dmac0_channels,
535 .channel_num = ARRAY_SIZE(dmac0_channels),
536 .ts_low_shift = CHCR_TS_LOW_SHIFT,
537 .ts_low_mask = CHCR_TS_LOW_MASK,
538 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
539 .ts_high_mask = CHCR_TS_HIGH_MASK,
540 .ts_shift = ts_shift,
541 .ts_shift_num = ARRAY_SIZE(ts_shift),
542 .dmaor_init = DMAOR_INIT,
545 /* Resource order important! */
546 static struct resource dmac0_resources[] = {
548 /* Channel registers and DMAOR */
551 .flags = IORESOURCE_MEM,
556 .flags = IORESOURCE_MEM,
559 .start = evt2irq(0x5c0),
560 .end = evt2irq(0x5c0),
561 .flags = IORESOURCE_IRQ,
563 /* IRQ for channels 0-5 */
564 .start = evt2irq(0x500),
565 .end = evt2irq(0x5a0),
566 .flags = IORESOURCE_IRQ,
570 static struct platform_device dma0_device = {
571 .name = "sh-dma-engine",
573 .resource = dmac0_resources,
574 .num_resources = ARRAY_SIZE(dmac0_resources),
576 .platform_data = &dma0_platform_data,
580 #define USB_EHCI_START 0xffe70000
581 #define USB_OHCI_START 0xffe70400
583 static struct resource usb_ehci_resources[] = {
585 .start = USB_EHCI_START,
586 .end = USB_EHCI_START + 0x3ff,
587 .flags = IORESOURCE_MEM,
590 .start = evt2irq(0xba0),
591 .end = evt2irq(0xba0),
592 .flags = IORESOURCE_IRQ,
596 static struct platform_device usb_ehci_device = {
600 .dma_mask = &usb_ehci_device.dev.coherent_dma_mask,
601 .coherent_dma_mask = DMA_BIT_MASK(32),
603 .num_resources = ARRAY_SIZE(usb_ehci_resources),
604 .resource = usb_ehci_resources,
607 static struct resource usb_ohci_resources[] = {
609 .start = USB_OHCI_START,
610 .end = USB_OHCI_START + 0x3ff,
611 .flags = IORESOURCE_MEM,
614 .start = evt2irq(0xba0),
615 .end = evt2irq(0xba0),
616 .flags = IORESOURCE_IRQ,
620 static struct usb_ohci_pdata usb_ohci_pdata;
622 static struct platform_device usb_ohci_device = {
623 .name = "ohci-platform",
626 .dma_mask = &usb_ohci_device.dev.coherent_dma_mask,
627 .coherent_dma_mask = DMA_BIT_MASK(32),
628 .platform_data = &usb_ohci_pdata,
630 .num_resources = ARRAY_SIZE(usb_ohci_resources),
631 .resource = usb_ohci_resources,
634 static struct platform_device *sh7786_early_devices[] __initdata = {
655 static struct platform_device *sh7786_devices[] __initdata = {
662 * Please call this function if your platform board
663 * use external clock for USB
665 #define USBCTL0 0xffe70858
666 #define CLOCK_MODE_MASK 0xffffff7f
667 #define EXT_CLOCK_MODE 0x00000080
669 void __init sh7786_usb_use_exclock(void)
671 u32 val = __raw_readl(USBCTL0) & CLOCK_MODE_MASK;
672 __raw_writel(val | EXT_CLOCK_MODE, USBCTL0);
675 #define USBINITREG1 0xffe70094
676 #define USBINITREG2 0xffe7009c
677 #define USBINITVAL1 0x00ff0040
678 #define USBINITVAL2 0x00000001
680 #define USBPCTL1 0xffe70804
681 #define USBST 0xffe70808
682 #define PHY_ENB 0x00000001
683 #define PLL_ENB 0x00000002
684 #define PHY_RST 0x00000004
685 #define ACT_PLL_STATUS 0xc0000000
687 static void __init sh7786_usb_setup(void)
692 * USB initial settings
694 * The following settings are necessary
695 * for using the USB modules.
697 * see "USB Initial Settings" for detail
699 __raw_writel(USBINITVAL1, USBINITREG1);
700 __raw_writel(USBINITVAL2, USBINITREG2);
703 * Set the PHY and PLL enable bit
705 __raw_writel(PHY_ENB | PLL_ENB, USBPCTL1);
707 if (ACT_PLL_STATUS == (__raw_readl(USBST) & ACT_PLL_STATUS)) {
708 /* Set the PHY RST bit */
709 __raw_writel(PHY_ENB | PLL_ENB | PHY_RST, USBPCTL1);
710 printk(KERN_INFO "sh7786 usb setup done\n");
720 /* interrupt sources */
721 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
722 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
723 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
724 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
726 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
727 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
728 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
729 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
731 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
733 TMU0_0, TMU0_1, TMU0_2, TMU0_3,
734 TMU1_0, TMU1_1, TMU1_2,
735 DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
737 DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
739 SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
742 SCIF2, SCIF3, SCIF4, SCIF5,
744 PCIeC0_0, PCIeC0_1, PCIeC0_2,
745 PCIeC1_0, PCIeC1_1, PCIeC1_2,
749 SSI0, SSI1, SSI2, SSI3,
750 PCIeC2_0, PCIeC2_1, PCIeC2_2,
756 INTICI0, INTICI1, INTICI2, INTICI3,
757 INTICI4, INTICI5, INTICI6, INTICI7,
759 /* Muxed sub-events */
760 TXI1, BRI1, RXI1, ERI1,
763 static struct intc_vect sh7786_vectors[] __initdata = {
764 INTC_VECT(WDT, 0x3e0),
765 INTC_VECT(TMU0_0, 0x400), INTC_VECT(TMU0_1, 0x420),
766 INTC_VECT(TMU0_2, 0x440), INTC_VECT(TMU0_3, 0x460),
767 INTC_VECT(TMU1_0, 0x480), INTC_VECT(TMU1_1, 0x4a0),
768 INTC_VECT(TMU1_2, 0x4c0),
769 INTC_VECT(DMAC0_0, 0x500), INTC_VECT(DMAC0_1, 0x520),
770 INTC_VECT(DMAC0_2, 0x540), INTC_VECT(DMAC0_3, 0x560),
771 INTC_VECT(DMAC0_4, 0x580), INTC_VECT(DMAC0_5, 0x5a0),
772 INTC_VECT(DMAC0_6, 0x5c0),
773 INTC_VECT(HUDI1, 0x5e0), INTC_VECT(HUDI0, 0x600),
774 INTC_VECT(DMAC1_0, 0x620), INTC_VECT(DMAC1_1, 0x640),
775 INTC_VECT(DMAC1_2, 0x660), INTC_VECT(DMAC1_3, 0x680),
776 INTC_VECT(HPB_0, 0x6a0), INTC_VECT(HPB_1, 0x6c0),
777 INTC_VECT(HPB_2, 0x6e0),
778 INTC_VECT(SCIF0_0, 0x700), INTC_VECT(SCIF0_1, 0x720),
779 INTC_VECT(SCIF0_2, 0x740), INTC_VECT(SCIF0_3, 0x760),
780 INTC_VECT(SCIF1, 0x780),
781 INTC_VECT(TMU2, 0x7a0), INTC_VECT(TMU3, 0x7c0),
782 INTC_VECT(SCIF2, 0x840), INTC_VECT(SCIF3, 0x860),
783 INTC_VECT(SCIF4, 0x880), INTC_VECT(SCIF5, 0x8a0),
784 INTC_VECT(Eth_0, 0x8c0), INTC_VECT(Eth_1, 0x8e0),
785 INTC_VECT(PCIeC0_0, 0xae0), INTC_VECT(PCIeC0_1, 0xb00),
786 INTC_VECT(PCIeC0_2, 0xb20),
787 INTC_VECT(PCIeC1_0, 0xb40), INTC_VECT(PCIeC1_1, 0xb60),
788 INTC_VECT(PCIeC1_2, 0xb80),
789 INTC_VECT(USB, 0xba0),
790 INTC_VECT(I2C0, 0xcc0), INTC_VECT(I2C1, 0xce0),
791 INTC_VECT(DU, 0xd00),
792 INTC_VECT(SSI0, 0xd20), INTC_VECT(SSI1, 0xd40),
793 INTC_VECT(SSI2, 0xd60), INTC_VECT(SSI3, 0xd80),
794 INTC_VECT(PCIeC2_0, 0xda0), INTC_VECT(PCIeC2_1, 0xdc0),
795 INTC_VECT(PCIeC2_2, 0xde0),
796 INTC_VECT(HAC0, 0xe00), INTC_VECT(HAC1, 0xe20),
797 INTC_VECT(FLCTL, 0xe40),
798 INTC_VECT(HSPI, 0xe80),
799 INTC_VECT(GPIO0, 0xea0), INTC_VECT(GPIO1, 0xec0),
800 INTC_VECT(Thermal, 0xee0),
801 INTC_VECT(INTICI0, 0xf00), INTC_VECT(INTICI1, 0xf20),
802 INTC_VECT(INTICI2, 0xf40), INTC_VECT(INTICI3, 0xf60),
803 INTC_VECT(INTICI4, 0xf80), INTC_VECT(INTICI5, 0xfa0),
804 INTC_VECT(INTICI6, 0xfc0), INTC_VECT(INTICI7, 0xfe0),
807 #define CnINTMSK0 0xfe410030
808 #define CnINTMSK1 0xfe410040
809 #define CnINTMSKCLR0 0xfe410050
810 #define CnINTMSKCLR1 0xfe410060
811 #define CnINT2MSKR0 0xfe410a20
812 #define CnINT2MSKR1 0xfe410a24
813 #define CnINT2MSKR2 0xfe410a28
814 #define CnINT2MSKR3 0xfe410a2c
815 #define CnINT2MSKCR0 0xfe410a30
816 #define CnINT2MSKCR1 0xfe410a34
817 #define CnINT2MSKCR2 0xfe410a38
818 #define CnINT2MSKCR3 0xfe410a3c
819 #define INTMSK2 0xfe410068
820 #define INTMSKCLR2 0xfe41006c
822 #define INTDISTCR0 0xfe4100b0
823 #define INTDISTCR1 0xfe4100b4
824 #define INT2DISTCR0 0xfe410900
825 #define INT2DISTCR1 0xfe410904
826 #define INT2DISTCR2 0xfe410908
827 #define INT2DISTCR3 0xfe41090c
829 static struct intc_mask_reg sh7786_mask_registers[] __initdata = {
830 { CnINTMSK0, CnINTMSKCLR0, 32,
831 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 },
832 INTC_SMP_BALANCING(INTDISTCR0) },
833 { INTMSK2, INTMSKCLR2, 32,
834 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
835 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
836 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
837 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
838 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
839 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
840 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
841 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
842 { CnINT2MSKR0, CnINT2MSKCR0 , 32,
843 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
844 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, WDT },
845 INTC_SMP_BALANCING(INT2DISTCR0) },
846 { CnINT2MSKR1, CnINT2MSKCR1, 32,
847 { TMU0_0, TMU0_1, TMU0_2, TMU0_3, TMU1_0, TMU1_1, TMU1_2, 0,
848 DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
850 DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
852 SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
854 TMU2, TMU3, 0, }, INTC_SMP_BALANCING(INT2DISTCR1) },
855 { CnINT2MSKR2, CnINT2MSKCR2, 32,
856 { 0, 0, SCIF2, SCIF3, SCIF4, SCIF5,
858 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
859 PCIeC0_0, PCIeC0_1, PCIeC0_2,
860 PCIeC1_0, PCIeC1_1, PCIeC1_2,
861 USB, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR2) },
862 { CnINT2MSKR3, CnINT2MSKCR3, 32,
865 DU, SSI0, SSI1, SSI2, SSI3,
866 PCIeC2_0, PCIeC2_1, PCIeC2_2,
869 HSPI, GPIO0, GPIO1, Thermal,
870 0, 0, 0, 0, 0, 0, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR3) },
873 static struct intc_prio_reg sh7786_prio_registers[] __initdata = {
874 { 0xfe410010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
875 IRQ4, IRQ5, IRQ6, IRQ7 } },
876 { 0xfe410800, 0, 32, 8, /* INT2PRI0 */ { 0, 0, 0, WDT } },
877 { 0xfe410804, 0, 32, 8, /* INT2PRI1 */ { TMU0_0, TMU0_1,
879 { 0xfe410808, 0, 32, 8, /* INT2PRI2 */ { TMU1_0, TMU1_1,
881 { 0xfe41080c, 0, 32, 8, /* INT2PRI3 */ { DMAC0_0, DMAC0_1,
882 DMAC0_2, DMAC0_3 } },
883 { 0xfe410810, 0, 32, 8, /* INT2PRI4 */ { DMAC0_4, DMAC0_5,
885 { 0xfe410814, 0, 32, 8, /* INT2PRI5 */ { HUDI0, DMAC1_0,
886 DMAC1_1, DMAC1_2 } },
887 { 0xfe410818, 0, 32, 8, /* INT2PRI6 */ { DMAC1_3, HPB_0,
889 { 0xfe41081c, 0, 32, 8, /* INT2PRI7 */ { SCIF0_0, SCIF0_1,
890 SCIF0_2, SCIF0_3 } },
891 { 0xfe410820, 0, 32, 8, /* INT2PRI8 */ { SCIF1, TMU2, TMU3, 0 } },
892 { 0xfe410824, 0, 32, 8, /* INT2PRI9 */ { 0, 0, SCIF2, SCIF3 } },
893 { 0xfe410828, 0, 32, 8, /* INT2PRI10 */ { SCIF4, SCIF5,
895 { 0xfe41082c, 0, 32, 8, /* INT2PRI11 */ { 0, 0, 0, 0 } },
896 { 0xfe410830, 0, 32, 8, /* INT2PRI12 */ { 0, 0, 0, 0 } },
897 { 0xfe410834, 0, 32, 8, /* INT2PRI13 */ { 0, 0, 0, 0 } },
898 { 0xfe410838, 0, 32, 8, /* INT2PRI14 */ { 0, 0, 0, PCIeC0_0 } },
899 { 0xfe41083c, 0, 32, 8, /* INT2PRI15 */ { PCIeC0_1, PCIeC0_2,
900 PCIeC1_0, PCIeC1_1 } },
901 { 0xfe410840, 0, 32, 8, /* INT2PRI16 */ { PCIeC1_2, USB, 0, 0 } },
902 { 0xfe410844, 0, 32, 8, /* INT2PRI17 */ { 0, 0, 0, 0 } },
903 { 0xfe410848, 0, 32, 8, /* INT2PRI18 */ { 0, 0, I2C0, I2C1 } },
904 { 0xfe41084c, 0, 32, 8, /* INT2PRI19 */ { DU, SSI0, SSI1, SSI2 } },
905 { 0xfe410850, 0, 32, 8, /* INT2PRI20 */ { SSI3, PCIeC2_0,
906 PCIeC2_1, PCIeC2_2 } },
907 { 0xfe410854, 0, 32, 8, /* INT2PRI21 */ { HAC0, HAC1, FLCTL, 0 } },
908 { 0xfe410858, 0, 32, 8, /* INT2PRI22 */ { HSPI, GPIO0,
910 { 0xfe41085c, 0, 32, 8, /* INT2PRI23 */ { 0, 0, 0, 0 } },
911 { 0xfe410860, 0, 32, 8, /* INT2PRI24 */ { 0, 0, 0, 0 } },
912 { 0xfe410090, 0xfe4100a0, 32, 4, /* CnICIPRI / CnICIPRICLR */
913 { INTICI7, INTICI6, INTICI5, INTICI4,
914 INTICI3, INTICI2, INTICI1, INTICI0 }, INTC_SMP(4, 2) },
917 static struct intc_subgroup sh7786_subgroups[] __initdata = {
918 { 0xfe410c20, 32, SCIF1,
919 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
920 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, TXI1, BRI1, RXI1, ERI1 } },
923 static struct intc_desc sh7786_intc_desc __initdata = {
926 .vectors = sh7786_vectors,
927 .nr_vectors = ARRAY_SIZE(sh7786_vectors),
928 .mask_regs = sh7786_mask_registers,
929 .nr_mask_regs = ARRAY_SIZE(sh7786_mask_registers),
930 .subgroups = sh7786_subgroups,
931 .nr_subgroups = ARRAY_SIZE(sh7786_subgroups),
932 .prio_regs = sh7786_prio_registers,
933 .nr_prio_regs = ARRAY_SIZE(sh7786_prio_registers),
937 /* Support for external interrupt pins in IRQ mode */
938 static struct intc_vect vectors_irq0123[] __initdata = {
939 INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240),
940 INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0),
943 static struct intc_vect vectors_irq4567[] __initdata = {
944 INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340),
945 INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0),
948 static struct intc_sense_reg sh7786_sense_registers[] __initdata = {
949 { 0xfe41001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
950 IRQ4, IRQ5, IRQ6, IRQ7 } },
953 static struct intc_mask_reg sh7786_ack_registers[] __initdata = {
954 { 0xfe410024, 0, 32, /* INTREQ */
955 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
958 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7786-irq0123",
959 vectors_irq0123, NULL, sh7786_mask_registers,
960 sh7786_prio_registers, sh7786_sense_registers,
961 sh7786_ack_registers);
963 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7786-irq4567",
964 vectors_irq4567, NULL, sh7786_mask_registers,
965 sh7786_prio_registers, sh7786_sense_registers,
966 sh7786_ack_registers);
968 /* External interrupt pins in IRL mode */
970 static struct intc_vect vectors_irl0123[] __initdata = {
971 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
972 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
973 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
974 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
975 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
976 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
977 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
978 INTC_VECT(IRL0_HHHL, 0x3c0),
981 static struct intc_vect vectors_irl4567[] __initdata = {
982 INTC_VECT(IRL4_LLLL, 0x900), INTC_VECT(IRL4_LLLH, 0x920),
983 INTC_VECT(IRL4_LLHL, 0x940), INTC_VECT(IRL4_LLHH, 0x960),
984 INTC_VECT(IRL4_LHLL, 0x980), INTC_VECT(IRL4_LHLH, 0x9a0),
985 INTC_VECT(IRL4_LHHL, 0x9c0), INTC_VECT(IRL4_LHHH, 0x9e0),
986 INTC_VECT(IRL4_HLLL, 0xa00), INTC_VECT(IRL4_HLLH, 0xa20),
987 INTC_VECT(IRL4_HLHL, 0xa40), INTC_VECT(IRL4_HLHH, 0xa60),
988 INTC_VECT(IRL4_HHLL, 0xa80), INTC_VECT(IRL4_HHLH, 0xaa0),
989 INTC_VECT(IRL4_HHHL, 0xac0),
992 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7786-irl0123", vectors_irl0123,
993 NULL, sh7786_mask_registers, NULL, NULL);
995 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
996 NULL, sh7786_mask_registers, NULL, NULL);
998 #define INTC_ICR0 0xfe410000
999 #define INTC_INTMSK0 CnINTMSK0
1000 #define INTC_INTMSK1 CnINTMSK1
1001 #define INTC_INTMSK2 INTMSK2
1002 #define INTC_INTMSKCLR1 CnINTMSKCLR1
1003 #define INTC_INTMSKCLR2 INTMSKCLR2
1005 void __init plat_irq_setup(void)
1007 /* disable IRQ3-0 + IRQ7-4 */
1008 __raw_writel(0xff000000, INTC_INTMSK0);
1010 /* disable IRL3-0 + IRL7-4 */
1011 __raw_writel(0xc0000000, INTC_INTMSK1);
1012 __raw_writel(0xfffefffe, INTC_INTMSK2);
1014 /* select IRL mode for IRL3-0 + IRL7-4 */
1015 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
1017 register_intc_controller(&sh7786_intc_desc);
1020 void __init plat_irq_setup_pins(int mode)
1023 case IRQ_MODE_IRQ7654:
1024 /* select IRQ mode for IRL7-4 */
1025 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
1026 register_intc_controller(&intc_desc_irq4567);
1028 case IRQ_MODE_IRQ3210:
1029 /* select IRQ mode for IRL3-0 */
1030 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
1031 register_intc_controller(&intc_desc_irq0123);
1033 case IRQ_MODE_IRL7654:
1034 /* enable IRL7-4 but don't provide any masking */
1035 __raw_writel(0x40000000, INTC_INTMSKCLR1);
1036 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
1038 case IRQ_MODE_IRL3210:
1039 /* enable IRL0-3 but don't provide any masking */
1040 __raw_writel(0x80000000, INTC_INTMSKCLR1);
1041 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
1043 case IRQ_MODE_IRL7654_MASK:
1044 /* enable IRL7-4 and mask using cpu intc controller */
1045 __raw_writel(0x40000000, INTC_INTMSKCLR1);
1046 register_intc_controller(&intc_desc_irl4567);
1048 case IRQ_MODE_IRL3210_MASK:
1049 /* enable IRL0-3 and mask using cpu intc controller */
1050 __raw_writel(0x80000000, INTC_INTMSKCLR1);
1051 register_intc_controller(&intc_desc_irl0123);
1058 void __init plat_mem_setup(void)
1062 static int __init sh7786_devices_setup(void)
1069 * De-mux SCIF1 IRQs if possible
1071 irq = intc_irq_lookup(sh7786_intc_desc.name, TXI1);
1073 scif1_demux_resources[1].start =
1074 intc_irq_lookup(sh7786_intc_desc.name, ERI1);
1075 scif1_demux_resources[2].start =
1076 intc_irq_lookup(sh7786_intc_desc.name, RXI1);
1077 scif1_demux_resources[3].start = irq;
1078 scif1_demux_resources[4].start =
1079 intc_irq_lookup(sh7786_intc_desc.name, BRI1);
1081 scif1_device.resource = scif1_demux_resources;
1082 scif1_device.num_resources = ARRAY_SIZE(scif1_demux_resources);
1085 ret = platform_add_devices(sh7786_early_devices,
1086 ARRAY_SIZE(sh7786_early_devices));
1087 if (unlikely(ret != 0))
1090 return platform_add_devices(sh7786_devices,
1091 ARRAY_SIZE(sh7786_devices));
1093 arch_initcall(sh7786_devices_setup);
1095 void __init plat_early_device_setup(void)
1097 early_platform_add_devices(sh7786_early_devices,
1098 ARRAY_SIZE(sh7786_early_devices));