arch/sh/kernel/cpu/sh4a/setup-sh7785.c

   1 /*
   2  * SH7785 Setup
   3  *
   4  *  Copyright (C) 2007  Paul Mundt
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/platform_device.h>
  11 #include <linux/init.h>
  12 #include <linux/serial.h>
  13 #include <linux/serial_sci.h>
  14 #include <linux/io.h>
  15 #include <linux/mm.h>
  16 #include <linux/sh_dma.h>
  17 #include <linux/sh_timer.h>
  18 #include <linux/sh_intc.h>
  19 #include <asm/mmzone.h>
  20 #include <cpu/dma-register.h>
  21
  22 static struct plat_sci_port scif0_platform_data = {
  23         .flags          = UPF_BOOT_AUTOCONF,
  24         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
  25         .type           = PORT_SCIF,
  26         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
  27 };
  28
  29 static struct resource scif0_resources[] = {
  30         DEFINE_RES_MEM(0xffea0000, 0x100),
  31         DEFINE_RES_IRQ(evt2irq(0x700)),
  32 };
  33
  34 static struct platform_device scif0_device = {
  35         .name           = "sh-sci",
  36         .id             = 0,
  37         .resource       = scif0_resources,
  38         .num_resources  = ARRAY_SIZE(scif0_resources),
  39         .dev            = {
  40                 .platform_data  = &scif0_platform_data,
  41         },
  42 };
  43
  44 static struct plat_sci_port scif1_platform_data = {
  45         .flags          = UPF_BOOT_AUTOCONF,
  46         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
  47         .type           = PORT_SCIF,
  48         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
  49 };
  50
  51 static struct resource scif1_resources[] = {
  52         DEFINE_RES_MEM(0xffeb0000, 0x100),
  53         DEFINE_RES_IRQ(evt2irq(0x780)),
  54 };
  55
  56 static struct platform_device scif1_device = {
  57         .name           = "sh-sci",
  58         .id             = 1,
  59         .resource       = scif1_resources,
  60         .num_resources  = ARRAY_SIZE(scif1_resources),
  61         .dev            = {
  62                 .platform_data  = &scif1_platform_data,
  63         },
  64 };
  65
  66 static struct plat_sci_port scif2_platform_data = {
  67         .flags          = UPF_BOOT_AUTOCONF,
  68         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
  69         .type           = PORT_SCIF,
  70         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
  71 };
  72
  73 static struct resource scif2_resources[] = {
  74         DEFINE_RES_MEM(0xffec0000, 0x100),
  75         DEFINE_RES_IRQ(evt2irq(0x980)),
  76 };
  77
  78 static struct platform_device scif2_device = {
  79         .name           = "sh-sci",
  80         .id             = 2,
  81         .resource       = scif2_resources,
  82         .num_resources  = ARRAY_SIZE(scif2_resources),
  83         .dev            = {
  84                 .platform_data  = &scif2_platform_data,
  85         },
  86 };
  87
  88 static struct plat_sci_port scif3_platform_data = {
  89         .flags          = UPF_BOOT_AUTOCONF,
  90         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
  91         .type           = PORT_SCIF,
  92         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
  93 };
  94
  95 static struct resource scif3_resources[] = {
  96         DEFINE_RES_MEM(0xffed0000, 0x100),
  97         DEFINE_RES_IRQ(evt2irq(0x9a0)),
  98 };
  99
 100 static struct platform_device scif3_device = {
 101         .name           = "sh-sci",
 102         .id             = 3,
 103         .resource       = scif3_resources,
 104         .num_resources  = ARRAY_SIZE(scif3_resources),
 105         .dev            = {
 106                 .platform_data  = &scif3_platform_data,
 107         },
 108 };
 109
 110 static struct plat_sci_port scif4_platform_data = {
 111         .flags          = UPF_BOOT_AUTOCONF,
 112         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
 113         .type           = PORT_SCIF,
 114         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 115 };
 116
 117 static struct resource scif4_resources[] = {
 118         DEFINE_RES_MEM(0xffee0000, 0x100),
 119         DEFINE_RES_IRQ(evt2irq(0x9c0)),
 120 };
 121
 122 static struct platform_device scif4_device = {
 123         .name           = "sh-sci",
 124         .id             = 4,
 125         .resource       = scif4_resources,
 126         .num_resources  = ARRAY_SIZE(scif4_resources),
 127         .dev            = {
 128                 .platform_data  = &scif4_platform_data,
 129         },
 130 };
 131
 132 static struct plat_sci_port scif5_platform_data = {
 133         .flags          = UPF_BOOT_AUTOCONF,
 134         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
 135         .type           = PORT_SCIF,
 136         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
 137 };
 138
 139 static struct resource scif5_resources[] = {
 140         DEFINE_RES_MEM(0xffef0000, 0x100),
 141         DEFINE_RES_IRQ(evt2irq(0x9e0)),
 142 };
 143
 144 static struct platform_device scif5_device = {
 145         .name           = "sh-sci",
 146         .id             = 5,
 147         .resource       = scif5_resources,
 148         .num_resources  = ARRAY_SIZE(scif5_resources),
 149         .dev            = {
 150                 .platform_data  = &scif5_platform_data,
 151         },
 152 };
 153
 154 static struct sh_timer_config tmu0_platform_data = {
 155         .channel_offset = 0x04,
 156         .timer_bit = 0,
 157         .clockevent_rating = 200,
 158 };
 159
 160 static struct resource tmu0_resources[] = {
 161         [0] = {
 162                 .start  = 0xffd80008,
 163                 .end    = 0xffd80013,
 164                 .flags  = IORESOURCE_MEM,
 165         },
 166         [1] = {
 167                 .start  = evt2irq(0x580),
 168                 .flags  = IORESOURCE_IRQ,
 169         },
 170 };
 171
 172 static struct platform_device tmu0_device = {
 173         .name           = "sh_tmu",
 174         .id             = 0,
 175         .dev = {
 176                 .platform_data  = &tmu0_platform_data,
 177         },
 178         .resource       = tmu0_resources,
 179         .num_resources  = ARRAY_SIZE(tmu0_resources),
 180 };
 181
 182 static struct sh_timer_config tmu1_platform_data = {
 183         .channel_offset = 0x10,
 184         .timer_bit = 1,
 185         .clocksource_rating = 200,
 186 };
 187
 188 static struct resource tmu1_resources[] = {
 189         [0] = {
 190                 .start  = 0xffd80014,
 191                 .end    = 0xffd8001f,
 192                 .flags  = IORESOURCE_MEM,
 193         },
 194         [1] = {
 195                 .start  = evt2irq(0x5a0),
 196                 .flags  = IORESOURCE_IRQ,
 197         },
 198 };
 199
 200 static struct platform_device tmu1_device = {
 201         .name           = "sh_tmu",
 202         .id             = 1,
 203         .dev = {
 204                 .platform_data  = &tmu1_platform_data,
 205         },
 206         .resource       = tmu1_resources,
 207         .num_resources  = ARRAY_SIZE(tmu1_resources),
 208 };
 209
 210 static struct sh_timer_config tmu2_platform_data = {
 211         .channel_offset = 0x1c,
 212         .timer_bit = 2,
 213 };
 214
 215 static struct resource tmu2_resources[] = {
 216         [0] = {
 217                 .start  = 0xffd80020,
 218                 .end    = 0xffd8002f,
 219                 .flags  = IORESOURCE_MEM,
 220         },
 221         [1] = {
 222                 .start  = evt2irq(0x5c0),
 223                 .flags  = IORESOURCE_IRQ,
 224         },
 225 };
 226
 227 static struct platform_device tmu2_device = {
 228         .name           = "sh_tmu",
 229         .id             = 2,
 230         .dev = {
 231                 .platform_data  = &tmu2_platform_data,
 232         },
 233         .resource       = tmu2_resources,
 234         .num_resources  = ARRAY_SIZE(tmu2_resources),
 235 };
 236
 237 static struct sh_timer_config tmu3_platform_data = {
 238         .channel_offset = 0x04,
 239         .timer_bit = 0,
 240 };
 241
 242 static struct resource tmu3_resources[] = {
 243         [0] = {
 244                 .start  = 0xffdc0008,
 245                 .end    = 0xffdc0013,
 246                 .flags  = IORESOURCE_MEM,
 247         },
 248         [1] = {
 249                 .start  = evt2irq(0xe00),
 250                 .flags  = IORESOURCE_IRQ,
 251         },
 252 };
 253
 254 static struct platform_device tmu3_device = {
 255         .name           = "sh_tmu",
 256         .id             = 3,
 257         .dev = {
 258                 .platform_data  = &tmu3_platform_data,
 259         },
 260         .resource       = tmu3_resources,
 261         .num_resources  = ARRAY_SIZE(tmu3_resources),
 262 };
 263
 264 static struct sh_timer_config tmu4_platform_data = {
 265         .channel_offset = 0x10,
 266         .timer_bit = 1,
 267 };
 268
 269 static struct resource tmu4_resources[] = {
 270         [0] = {
 271                 .start  = 0xffdc0014,
 272                 .end    = 0xffdc001f,
 273                 .flags  = IORESOURCE_MEM,
 274         },
 275         [1] = {
 276                 .start  = evt2irq(0xe20),
 277                 .flags  = IORESOURCE_IRQ,
 278         },
 279 };
 280
 281 static struct platform_device tmu4_device = {
 282         .name           = "sh_tmu",
 283         .id             = 4,
 284         .dev = {
 285                 .platform_data  = &tmu4_platform_data,
 286         },
 287         .resource       = tmu4_resources,
 288         .num_resources  = ARRAY_SIZE(tmu4_resources),
 289 };
 290
 291 static struct sh_timer_config tmu5_platform_data = {
 292         .channel_offset = 0x1c,
 293         .timer_bit = 2,
 294 };
 295
 296 static struct resource tmu5_resources[] = {
 297         [0] = {
 298                 .start  = 0xffdc0020,
 299                 .end    = 0xffdc002b,
 300                 .flags  = IORESOURCE_MEM,
 301         },
 302         [1] = {
 303                 .start  = evt2irq(0xe40),
 304                 .flags  = IORESOURCE_IRQ,
 305         },
 306 };
 307
 308 static struct platform_device tmu5_device = {
 309         .name           = "sh_tmu",
 310         .id             = 5,
 311         .dev = {
 312                 .platform_data  = &tmu5_platform_data,
 313         },
 314         .resource       = tmu5_resources,
 315         .num_resources  = ARRAY_SIZE(tmu5_resources),
 316 };
 317
 318 /* DMA */
 319 static const struct sh_dmae_channel sh7785_dmae0_channels[] = {
 320         {
 321                 .offset = 0,
 322                 .dmars = 0,
 323                 .dmars_bit = 0,
 324         }, {
 325                 .offset = 0x10,
 326                 .dmars = 0,
 327                 .dmars_bit = 8,
 328         }, {
 329                 .offset = 0x20,
 330                 .dmars = 4,
 331                 .dmars_bit = 0,
 332         }, {
 333                 .offset = 0x30,
 334                 .dmars = 4,
 335                 .dmars_bit = 8,
 336         }, {
 337                 .offset = 0x50,
 338                 .dmars = 8,
 339                 .dmars_bit = 0,
 340         }, {
 341                 .offset = 0x60,
 342                 .dmars = 8,
 343                 .dmars_bit = 8,
 344         }
 345 };
 346
 347 static const struct sh_dmae_channel sh7785_dmae1_channels[] = {
 348         {
 349                 .offset = 0,
 350         }, {
 351                 .offset = 0x10,
 352         }, {
 353                 .offset = 0x20,
 354         }, {
 355                 .offset = 0x30,
 356         }, {
 357                 .offset = 0x50,
 358         }, {
 359                 .offset = 0x60,
 360         }
 361 };
 362
 363 static const unsigned int ts_shift[] = TS_SHIFT;
 364
 365 static struct sh_dmae_pdata dma0_platform_data = {
 366         .channel        = sh7785_dmae0_channels,
 367         .channel_num    = ARRAY_SIZE(sh7785_dmae0_channels),
 368         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
 369         .ts_low_mask    = CHCR_TS_LOW_MASK,
 370         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
 371         .ts_high_mask   = CHCR_TS_HIGH_MASK,
 372         .ts_shift       = ts_shift,
 373         .ts_shift_num   = ARRAY_SIZE(ts_shift),
 374         .dmaor_init     = DMAOR_INIT,
 375 };
 376
 377 static struct sh_dmae_pdata dma1_platform_data = {
 378         .channel        = sh7785_dmae1_channels,
 379         .channel_num    = ARRAY_SIZE(sh7785_dmae1_channels),
 380         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
 381         .ts_low_mask    = CHCR_TS_LOW_MASK,
 382         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
 383         .ts_high_mask   = CHCR_TS_HIGH_MASK,
 384         .ts_shift       = ts_shift,
 385         .ts_shift_num   = ARRAY_SIZE(ts_shift),
 386         .dmaor_init     = DMAOR_INIT,
 387 };
 388
 389 static struct resource sh7785_dmae0_resources[] = {
 390         [0] = {
 391                 /* Channel registers and DMAOR */
 392                 .start  = 0xfc808020,
 393                 .end    = 0xfc80808f,
 394                 .flags  = IORESOURCE_MEM,
 395         },
 396         [1] = {
 397                 /* DMARSx */
 398                 .start  = 0xfc809000,
 399                 .end    = 0xfc80900b,
 400                 .flags  = IORESOURCE_MEM,
 401         },
 402         {
 403                 /*
 404                  * Real DMA error vector is 0x6e0, and channel
 405                  * vectors are 0x620-0x6c0
 406                  */
 407                 .name   = "error_irq",
 408                 .start  = evt2irq(0x620),
 409                 .end    = evt2irq(0x620),
 410                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 411         },
 412 };
 413
 414 static struct resource sh7785_dmae1_resources[] = {
 415         [0] = {
 416                 /* Channel registers and DMAOR */
 417                 .start  = 0xfcc08020,
 418                 .end    = 0xfcc0808f,
 419                 .flags  = IORESOURCE_MEM,
 420         },
 421         /* DMAC1 has no DMARS */
 422         {
 423                 /*
 424                  * Real DMA error vector is 0x940, and channel
 425                  * vectors are 0x880-0x920
 426                  */
 427                 .name   = "error_irq",
 428                 .start  = evt2irq(0x880),
 429                 .end    = evt2irq(0x880),
 430                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 431         },
 432 };
 433
 434 static struct platform_device dma0_device = {
 435         .name           = "sh-dma-engine",
 436         .id             = 0,
 437         .resource       = sh7785_dmae0_resources,
 438         .num_resources  = ARRAY_SIZE(sh7785_dmae0_resources),
 439         .dev            = {
 440                 .platform_data  = &dma0_platform_data,
 441         },
 442 };
 443
 444 static struct platform_device dma1_device = {
 445         .name           = "sh-dma-engine",
 446         .id             = 1,
 447         .resource       = sh7785_dmae1_resources,
 448         .num_resources  = ARRAY_SIZE(sh7785_dmae1_resources),
 449         .dev            = {
 450                 .platform_data  = &dma1_platform_data,
 451         },
 452 };
 453
 454 static struct platform_device *sh7785_devices[] __initdata = {
 455         &scif0_device,
 456         &scif1_device,
 457         &scif2_device,
 458         &scif3_device,
 459         &scif4_device,
 460         &scif5_device,
 461         &tmu0_device,
 462         &tmu1_device,
 463         &tmu2_device,
 464         &tmu3_device,
 465         &tmu4_device,
 466         &tmu5_device,
 467         &dma0_device,
 468         &dma1_device,
 469 };
 470
 471 static int __init sh7785_devices_setup(void)
 472 {
 473         return platform_add_devices(sh7785_devices,
 474                                     ARRAY_SIZE(sh7785_devices));
 475 }
 476 arch_initcall(sh7785_devices_setup);
 477
 478 static struct platform_device *sh7785_early_devices[] __initdata = {
 479         &scif0_device,
 480         &scif1_device,
 481         &scif2_device,
 482         &scif3_device,
 483         &scif4_device,
 484         &scif5_device,
 485         &tmu0_device,
 486         &tmu1_device,
 487         &tmu2_device,
 488         &tmu3_device,
 489         &tmu4_device,
 490         &tmu5_device,
 491 };
 492
 493 void __init plat_early_device_setup(void)
 494 {
 495         early_platform_add_devices(sh7785_early_devices,
 496                                    ARRAY_SIZE(sh7785_early_devices));
 497 }
 498
 499 enum {
 500         UNUSED = 0,
 501
 502         /* interrupt sources */
 503
 504         IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 505         IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 506         IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 507         IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
 508
 509         IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
 510         IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
 511         IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
 512         IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
 513
 514         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 515         WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
 516         HUDI, DMAC0, SCIF0, SCIF1, DMAC1, HSPI,
 517         SCIF2, SCIF3, SCIF4, SCIF5,
 518         PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
 519         SIOF, MMCIF, DU, GDTA,
 520         TMU3, TMU4, TMU5,
 521         SSI0, SSI1,
 522         HAC0, HAC1,
 523         FLCTL, GPIO,
 524
 525         /* interrupt groups */
 526
 527         TMU012, TMU345
 528 };
 529
 530 static struct intc_vect vectors[] __initdata = {
 531         INTC_VECT(WDT, 0x560),
 532         INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
 533         INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
 534         INTC_VECT(HUDI, 0x600),
 535         INTC_VECT(DMAC0, 0x620), INTC_VECT(DMAC0, 0x640),
 536         INTC_VECT(DMAC0, 0x660), INTC_VECT(DMAC0, 0x680),
 537         INTC_VECT(DMAC0, 0x6a0), INTC_VECT(DMAC0, 0x6c0),
 538         INTC_VECT(DMAC0, 0x6e0),
 539         INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
 540         INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
 541         INTC_VECT(SCIF1, 0x780), INTC_VECT(SCIF1, 0x7a0),
 542         INTC_VECT(SCIF1, 0x7c0), INTC_VECT(SCIF1, 0x7e0),
 543         INTC_VECT(DMAC1, 0x880), INTC_VECT(DMAC1, 0x8a0),
 544         INTC_VECT(DMAC1, 0x8c0), INTC_VECT(DMAC1, 0x8e0),
 545         INTC_VECT(DMAC1, 0x900), INTC_VECT(DMAC1, 0x920),
 546         INTC_VECT(DMAC1, 0x940),
 547         INTC_VECT(HSPI, 0x960),
 548         INTC_VECT(SCIF2, 0x980), INTC_VECT(SCIF3, 0x9a0),
 549         INTC_VECT(SCIF4, 0x9c0), INTC_VECT(SCIF5, 0x9e0),
 550         INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
 551         INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
 552         INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
 553         INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
 554         INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
 555         INTC_VECT(SIOF, 0xc00),
 556         INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
 557         INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
 558         INTC_VECT(DU, 0xd80),
 559         INTC_VECT(GDTA, 0xda0), INTC_VECT(GDTA, 0xdc0),
 560         INTC_VECT(GDTA, 0xde0),
 561         INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
 562         INTC_VECT(TMU5, 0xe40),
 563         INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
 564         INTC_VECT(HAC0, 0xec0), INTC_VECT(HAC1, 0xee0),
 565         INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
 566         INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
 567         INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
 568         INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
 569 };
 570
 571 static struct intc_group groups[] __initdata = {
 572         INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
 573         INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
 574 };
 575
 576 static struct intc_mask_reg mask_registers[] __initdata = {
 577         { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
 578           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 579
 580         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 581           { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 582             IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 583             IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 584             IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
 585             IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
 586             IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
 587             IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
 588             IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
 589
 590         { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
 591           { 0, 0, 0, GDTA, DU, SSI0, SSI1, GPIO,
 592             FLCTL, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
 593             PCIINTA, PCISERR, HAC1, HAC0, DMAC1, DMAC0, HUDI, WDT,
 594             SCIF5, SCIF4, SCIF3, SCIF2, SCIF1, SCIF0, TMU345, TMU012 } },
 595 };
 596
 597 static struct intc_prio_reg prio_registers[] __initdata = {
 598         { 0xffd00010, 0, 32, 4, /* INTPRI */   { IRQ0, IRQ1, IRQ2, IRQ3,
 599                                                  IRQ4, IRQ5, IRQ6, IRQ7 } },
 600         { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
 601                                                  TMU2, TMU2_TICPI } },
 602         { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, } },
 603         { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1,
 604                                                  SCIF2, SCIF3 } },
 605         { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { SCIF4, SCIF5, WDT, } },
 606         { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { HUDI, DMAC0, DMAC1, } },
 607         { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { HAC0, HAC1,
 608                                                  PCISERR, PCIINTA } },
 609         { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { PCIINTB, PCIINTC,
 610                                                  PCIINTD, PCIC5 } },
 611         { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SIOF, HSPI, MMCIF, } },
 612         { 0xffd40020, 0, 32, 8, /* INT2PRI8 */ { FLCTL, GPIO, SSI0, SSI1, } },
 613         { 0xffd40024, 0, 32, 8, /* INT2PRI9 */ { DU, GDTA, } },
 614 };
 615
 616 static DECLARE_INTC_DESC(intc_desc, "sh7785", vectors, groups,
 617                          mask_registers, prio_registers, NULL);
 618
 619 /* Support for external interrupt pins in IRQ mode */
 620
 621 static struct intc_vect vectors_irq0123[] __initdata = {
 622         INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
 623         INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
 624 };
 625
 626 static struct intc_vect vectors_irq4567[] __initdata = {
 627         INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
 628         INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
 629 };
 630
 631 static struct intc_sense_reg sense_registers[] __initdata = {
 632         { 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
 633                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
 634 };
 635
 636 static struct intc_mask_reg ack_registers[] __initdata = {
 637         { 0xffd00024, 0, 32, /* INTREQ */
 638           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 639 };
 640
 641 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7785-irq0123",
 642                              vectors_irq0123, NULL, mask_registers,
 643                              prio_registers, sense_registers, ack_registers);
 644
 645 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7785-irq4567",
 646                              vectors_irq4567, NULL, mask_registers,
 647                              prio_registers, sense_registers, ack_registers);
 648
 649 /* External interrupt pins in IRL mode */
 650
 651 static struct intc_vect vectors_irl0123[] __initdata = {
 652         INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
 653         INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
 654         INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
 655         INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
 656         INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
 657         INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
 658         INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
 659         INTC_VECT(IRL0_HHHL, 0x3c0),
 660 };
 661
 662 static struct intc_vect vectors_irl4567[] __initdata = {
 663         INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
 664         INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
 665         INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
 666         INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0),
 667         INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20),
 668         INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60),
 669         INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0),
 670         INTC_VECT(IRL4_HHHL, 0xcc0),
 671 };
 672
 673 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7785-irl0123", vectors_irl0123,
 674                          NULL, mask_registers, NULL, NULL);
 675
 676 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7785-irl4567", vectors_irl4567,
 677                          NULL, mask_registers, NULL, NULL);
 678
 679 #define INTC_ICR0       0xffd00000
 680 #define INTC_INTMSK0    0xffd00044
 681 #define INTC_INTMSK1    0xffd00048
 682 #define INTC_INTMSK2    0xffd40080
 683 #define INTC_INTMSKCLR1 0xffd00068
 684 #define INTC_INTMSKCLR2 0xffd40084
 685
 686 void __init plat_irq_setup(void)
 687 {
 688         /* disable IRQ3-0 + IRQ7-4 */
 689         __raw_writel(0xff000000, INTC_INTMSK0);
 690
 691         /* disable IRL3-0 + IRL7-4 */
 692         __raw_writel(0xc0000000, INTC_INTMSK1);
 693         __raw_writel(0xfffefffe, INTC_INTMSK2);
 694
 695         /* select IRL mode for IRL3-0 + IRL7-4 */
 696         __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 697
 698         /* disable holding function, ie enable "SH-4 Mode" */
 699         __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
 700
 701         register_intc_controller(&intc_desc);
 702 }
 703
 704 void __init plat_irq_setup_pins(int mode)
 705 {
 706         switch (mode) {
 707         case IRQ_MODE_IRQ7654:
 708                 /* select IRQ mode for IRL7-4 */
 709                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
 710                 register_intc_controller(&intc_desc_irq4567);
 711                 break;
 712         case IRQ_MODE_IRQ3210:
 713                 /* select IRQ mode for IRL3-0 */
 714                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
 715                 register_intc_controller(&intc_desc_irq0123);
 716                 break;
 717         case IRQ_MODE_IRL7654:
 718                 /* enable IRL7-4 but don't provide any masking */
 719                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 720                 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
 721                 break;
 722         case IRQ_MODE_IRL3210:
 723                 /* enable IRL0-3 but don't provide any masking */
 724                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 725                 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
 726                 break;
 727         case IRQ_MODE_IRL7654_MASK:
 728                 /* enable IRL7-4 and mask using cpu intc controller */
 729                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 730                 register_intc_controller(&intc_desc_irl4567);
 731                 break;
 732         case IRQ_MODE_IRL3210_MASK:
 733                 /* enable IRL0-3 and mask using cpu intc controller */
 734                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 735                 register_intc_controller(&intc_desc_irl0123);
 736                 break;
 737         default:
 738                 BUG();
 739         }
 740 }
 741
 742 void __init plat_mem_setup(void)
 743 {
 744         /* Register the URAM space as Node 1 */
 745         setup_bootmem_node(1, 0xe55f0000, 0xe5610000);
 746 }