4 * Copyright (C) 2006 Paul Mundt
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/serial.h>
14 #include <linux/serial_sci.h>
15 #include <linux/sh_dma.h>
16 #include <linux/sh_timer.h>
17 #include <linux/sh_intc.h>
18 #include <cpu/dma-register.h>
20 static struct plat_sci_port scif0_platform_data = {
21 .mapbase = 0xffe00000,
22 .flags = UPF_BOOT_AUTOCONF,
23 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
24 .scbrr_algo_id = SCBRR_ALGO_1,
26 .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)),
27 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
30 static struct platform_device scif0_device = {
34 .platform_data = &scif0_platform_data,
38 static struct plat_sci_port scif1_platform_data = {
39 .mapbase = 0xffe10000,
40 .flags = UPF_BOOT_AUTOCONF,
41 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
42 .scbrr_algo_id = SCBRR_ALGO_1,
44 .irqs = SCIx_IRQ_MUXED(evt2irq(0xb80)),
45 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
48 static struct platform_device scif1_device = {
52 .platform_data = &scif1_platform_data,
56 static struct sh_timer_config tmu0_platform_data = {
57 .channel_offset = 0x04,
59 .clockevent_rating = 200,
62 static struct resource tmu0_resources[] = {
66 .flags = IORESOURCE_MEM,
69 .start = evt2irq(0x580),
70 .flags = IORESOURCE_IRQ,
74 static struct platform_device tmu0_device = {
78 .platform_data = &tmu0_platform_data,
80 .resource = tmu0_resources,
81 .num_resources = ARRAY_SIZE(tmu0_resources),
84 static struct sh_timer_config tmu1_platform_data = {
85 .channel_offset = 0x10,
87 .clocksource_rating = 200,
90 static struct resource tmu1_resources[] = {
94 .flags = IORESOURCE_MEM,
97 .start = evt2irq(0x5a0),
98 .flags = IORESOURCE_IRQ,
102 static struct platform_device tmu1_device = {
106 .platform_data = &tmu1_platform_data,
108 .resource = tmu1_resources,
109 .num_resources = ARRAY_SIZE(tmu1_resources),
112 static struct sh_timer_config tmu2_platform_data = {
113 .channel_offset = 0x1c,
117 static struct resource tmu2_resources[] = {
121 .flags = IORESOURCE_MEM,
124 .start = evt2irq(0x5c0),
125 .flags = IORESOURCE_IRQ,
129 static struct platform_device tmu2_device = {
133 .platform_data = &tmu2_platform_data,
135 .resource = tmu2_resources,
136 .num_resources = ARRAY_SIZE(tmu2_resources),
139 static struct sh_timer_config tmu3_platform_data = {
140 .channel_offset = 0x04,
144 static struct resource tmu3_resources[] = {
148 .flags = IORESOURCE_MEM,
151 .start = evt2irq(0xe00),
152 .flags = IORESOURCE_IRQ,
156 static struct platform_device tmu3_device = {
160 .platform_data = &tmu3_platform_data,
162 .resource = tmu3_resources,
163 .num_resources = ARRAY_SIZE(tmu3_resources),
166 static struct sh_timer_config tmu4_platform_data = {
167 .channel_offset = 0x10,
171 static struct resource tmu4_resources[] = {
175 .flags = IORESOURCE_MEM,
178 .start = evt2irq(0xe20),
179 .flags = IORESOURCE_IRQ,
183 static struct platform_device tmu4_device = {
187 .platform_data = &tmu4_platform_data,
189 .resource = tmu4_resources,
190 .num_resources = ARRAY_SIZE(tmu4_resources),
193 static struct sh_timer_config tmu5_platform_data = {
194 .channel_offset = 0x1c,
198 static struct resource tmu5_resources[] = {
202 .flags = IORESOURCE_MEM,
205 .start = evt2irq(0xe40),
206 .flags = IORESOURCE_IRQ,
210 static struct platform_device tmu5_device = {
214 .platform_data = &tmu5_platform_data,
216 .resource = tmu5_resources,
217 .num_resources = ARRAY_SIZE(tmu5_resources),
220 static struct resource rtc_resources[] = {
223 .end = 0xffe80000 + 0x58 - 1,
224 .flags = IORESOURCE_IO,
227 /* Shared Period/Carry/Alarm IRQ */
228 .start = evt2irq(0x480),
229 .flags = IORESOURCE_IRQ,
233 static struct platform_device rtc_device = {
236 .num_resources = ARRAY_SIZE(rtc_resources),
237 .resource = rtc_resources,
241 static const struct sh_dmae_channel sh7780_dmae0_channels[] = {
269 static const struct sh_dmae_channel sh7780_dmae1_channels[] = {
285 static const unsigned int ts_shift[] = TS_SHIFT;
287 static struct sh_dmae_pdata dma0_platform_data = {
288 .channel = sh7780_dmae0_channels,
289 .channel_num = ARRAY_SIZE(sh7780_dmae0_channels),
290 .ts_low_shift = CHCR_TS_LOW_SHIFT,
291 .ts_low_mask = CHCR_TS_LOW_MASK,
292 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
293 .ts_high_mask = CHCR_TS_HIGH_MASK,
294 .ts_shift = ts_shift,
295 .ts_shift_num = ARRAY_SIZE(ts_shift),
296 .dmaor_init = DMAOR_INIT,
299 static struct sh_dmae_pdata dma1_platform_data = {
300 .channel = sh7780_dmae1_channels,
301 .channel_num = ARRAY_SIZE(sh7780_dmae1_channels),
302 .ts_low_shift = CHCR_TS_LOW_SHIFT,
303 .ts_low_mask = CHCR_TS_LOW_MASK,
304 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
305 .ts_high_mask = CHCR_TS_HIGH_MASK,
306 .ts_shift = ts_shift,
307 .ts_shift_num = ARRAY_SIZE(ts_shift),
308 .dmaor_init = DMAOR_INIT,
311 static struct resource sh7780_dmae0_resources[] = {
313 /* Channel registers and DMAOR */
316 .flags = IORESOURCE_MEM,
322 .flags = IORESOURCE_MEM,
326 * Real DMA error vector is 0x6c0, and channel
327 * vectors are 0x640-0x6a0, 0x780-0x7a0
330 .start = evt2irq(0x640),
331 .end = evt2irq(0x640),
332 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
336 static struct resource sh7780_dmae1_resources[] = {
338 /* Channel registers and DMAOR */
341 .flags = IORESOURCE_MEM,
343 /* DMAC1 has no DMARS */
346 * Real DMA error vector is 0x6c0, and channel
347 * vectors are 0x7c0-0x7e0, 0xd80-0xde0
350 .start = evt2irq(0x7c0),
351 .end = evt2irq(0x7c0),
352 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
356 static struct platform_device dma0_device = {
357 .name = "sh-dma-engine",
359 .resource = sh7780_dmae0_resources,
360 .num_resources = ARRAY_SIZE(sh7780_dmae0_resources),
362 .platform_data = &dma0_platform_data,
366 static struct platform_device dma1_device = {
367 .name = "sh-dma-engine",
369 .resource = sh7780_dmae1_resources,
370 .num_resources = ARRAY_SIZE(sh7780_dmae1_resources),
372 .platform_data = &dma1_platform_data,
376 static struct platform_device *sh7780_devices[] __initdata = {
390 static int __init sh7780_devices_setup(void)
392 return platform_add_devices(sh7780_devices,
393 ARRAY_SIZE(sh7780_devices));
395 arch_initcall(sh7780_devices_setup);
397 static struct platform_device *sh7780_early_devices[] __initdata = {
408 void __init plat_early_device_setup(void)
410 if (mach_is_sh2007()) {
411 scif0_platform_data.scscr &= ~SCSCR_CKE1;
412 scif0_platform_data.scbrr_algo_id = SCBRR_ALGO_2;
413 scif1_platform_data.scscr &= ~SCSCR_CKE1;
414 scif1_platform_data.scbrr_algo_id = SCBRR_ALGO_2;
417 early_platform_add_devices(sh7780_early_devices,
418 ARRAY_SIZE(sh7780_early_devices));
424 /* interrupt sources */
426 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
427 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
428 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
429 IRL_HHLL, IRL_HHLH, IRL_HHHL,
431 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
432 RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
433 HUDI, DMAC0, SCIF0, DMAC1, CMT, HAC,
434 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
435 SCIF1, SIOF, HSPI, MMCIF, TMU3, TMU4, TMU5, SSI, FLCTL, GPIO,
437 /* interrupt groups */
442 static struct intc_vect vectors[] __initdata = {
443 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
444 INTC_VECT(RTC, 0x4c0),
445 INTC_VECT(WDT, 0x560),
446 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
447 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
448 INTC_VECT(HUDI, 0x600),
449 INTC_VECT(DMAC0, 0x640), INTC_VECT(DMAC0, 0x660),
450 INTC_VECT(DMAC0, 0x680), INTC_VECT(DMAC0, 0x6a0),
451 INTC_VECT(DMAC0, 0x6c0),
452 INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
453 INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
454 INTC_VECT(DMAC0, 0x780), INTC_VECT(DMAC0, 0x7a0),
455 INTC_VECT(DMAC1, 0x7c0), INTC_VECT(DMAC1, 0x7e0),
456 INTC_VECT(CMT, 0x900), INTC_VECT(HAC, 0x980),
457 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
458 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
459 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
460 INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
461 INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
462 INTC_VECT(SCIF1, 0xb80), INTC_VECT(SCIF1, 0xba0),
463 INTC_VECT(SCIF1, 0xbc0), INTC_VECT(SCIF1, 0xbe0),
464 INTC_VECT(SIOF, 0xc00), INTC_VECT(HSPI, 0xc80),
465 INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
466 INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
467 INTC_VECT(DMAC1, 0xd80), INTC_VECT(DMAC1, 0xda0),
468 INTC_VECT(DMAC1, 0xdc0), INTC_VECT(DMAC1, 0xde0),
469 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
470 INTC_VECT(TMU5, 0xe40),
471 INTC_VECT(SSI, 0xe80),
472 INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
473 INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
474 INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
475 INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
478 static struct intc_group groups[] __initdata = {
479 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
480 INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
483 static struct intc_mask_reg mask_registers[] __initdata = {
484 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
485 { 0, 0, 0, 0, 0, 0, GPIO, FLCTL,
486 SSI, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
487 PCIINTA, PCISERR, HAC, CMT, 0, 0, DMAC1, DMAC0,
488 HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
491 static struct intc_prio_reg prio_registers[] __initdata = {
492 { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
493 TMU2, TMU2_TICPI } },
494 { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } },
495 { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } },
496 { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { HUDI, DMAC0, DMAC1 } },
497 { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { CMT, HAC,
498 PCISERR, PCIINTA, } },
499 { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC,
501 { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { SIOF, HSPI, MMCIF, SSI } },
502 { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { FLCTL, GPIO } },
505 static DECLARE_INTC_DESC(intc_desc, "sh7780", vectors, groups,
506 mask_registers, prio_registers, NULL);
508 /* Support for external interrupt pins in IRQ mode */
510 static struct intc_vect irq_vectors[] __initdata = {
511 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
512 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
513 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
514 INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
517 static struct intc_mask_reg irq_mask_registers[] __initdata = {
518 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
519 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
522 static struct intc_prio_reg irq_prio_registers[] __initdata = {
523 { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
524 IRQ4, IRQ5, IRQ6, IRQ7 } },
527 static struct intc_sense_reg irq_sense_registers[] __initdata = {
528 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
529 IRQ4, IRQ5, IRQ6, IRQ7 } },
532 static struct intc_mask_reg irq_ack_registers[] __initdata = {
533 { 0xffd00024, 0, 32, /* INTREQ */
534 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
537 static DECLARE_INTC_DESC_ACK(intc_irq_desc, "sh7780-irq", irq_vectors,
538 NULL, irq_mask_registers, irq_prio_registers,
539 irq_sense_registers, irq_ack_registers);
541 /* External interrupt pins in IRL mode */
543 static struct intc_vect irl_vectors[] __initdata = {
544 INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
545 INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
546 INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
547 INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
548 INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
549 INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
550 INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
551 INTC_VECT(IRL_HHHL, 0x3c0),
554 static struct intc_mask_reg irl3210_mask_registers[] __initdata = {
555 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
556 { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
557 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
558 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
559 IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
562 static struct intc_mask_reg irl7654_mask_registers[] __initdata = {
563 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
564 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
565 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
566 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
567 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
568 IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
571 static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7780-irl7654", irl_vectors,
572 NULL, irl7654_mask_registers, NULL, NULL);
574 static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
575 NULL, irl3210_mask_registers, NULL, NULL);
577 #define INTC_ICR0 0xffd00000
578 #define INTC_INTMSK0 0xffd00044
579 #define INTC_INTMSK1 0xffd00048
580 #define INTC_INTMSK2 0xffd40080
581 #define INTC_INTMSKCLR1 0xffd00068
582 #define INTC_INTMSKCLR2 0xffd40084
584 void __init plat_irq_setup(void)
587 __raw_writel(0xff000000, INTC_INTMSK0);
589 /* disable IRL3-0 + IRL7-4 */
590 __raw_writel(0xc0000000, INTC_INTMSK1);
591 __raw_writel(0xfffefffe, INTC_INTMSK2);
593 /* select IRL mode for IRL3-0 + IRL7-4 */
594 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
596 /* disable holding function, ie enable "SH-4 Mode" */
597 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
599 register_intc_controller(&intc_desc);
602 void __init plat_irq_setup_pins(int mode)
606 /* select IRQ mode for IRL3-0 + IRL7-4 */
607 __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
608 register_intc_controller(&intc_irq_desc);
610 case IRQ_MODE_IRL7654:
611 /* enable IRL7-4 but don't provide any masking */
612 __raw_writel(0x40000000, INTC_INTMSKCLR1);
613 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
615 case IRQ_MODE_IRL3210:
616 /* enable IRL0-3 but don't provide any masking */
617 __raw_writel(0x80000000, INTC_INTMSKCLR1);
618 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
620 case IRQ_MODE_IRL7654_MASK:
621 /* enable IRL7-4 and mask using cpu intc controller */
622 __raw_writel(0x40000000, INTC_INTMSKCLR1);
623 register_intc_controller(&intc_irl7654_desc);
625 case IRQ_MODE_IRL3210_MASK:
626 /* enable IRL0-3 and mask using cpu intc controller */
627 __raw_writel(0x80000000, INTC_INTMSKCLR1);
628 register_intc_controller(&intc_irl3210_desc);