4 * Copyright (C) 2006 Paul Mundt
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/serial.h>
14 #include <linux/serial_sci.h>
15 #include <linux/sh_dma.h>
16 #include <linux/sh_timer.h>
17 #include <linux/sh_intc.h>
18 #include <cpu/dma-register.h>
20 static struct plat_sci_port scif0_platform_data = {
21 .flags = UPF_BOOT_AUTOCONF,
22 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
24 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
27 static struct resource scif0_resources[] = {
28 DEFINE_RES_MEM(0xffe00000, 0x100),
29 DEFINE_RES_IRQ(evt2irq(0x700)),
32 static struct platform_device scif0_device = {
35 .resource = scif0_resources,
36 .num_resources = ARRAY_SIZE(scif0_resources),
38 .platform_data = &scif0_platform_data,
42 static struct plat_sci_port scif1_platform_data = {
43 .flags = UPF_BOOT_AUTOCONF,
44 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
46 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
49 static struct resource scif1_resources[] = {
50 DEFINE_RES_MEM(0xffe10000, 0x100),
51 DEFINE_RES_IRQ(evt2irq(0xb80)),
54 static struct platform_device scif1_device = {
57 .resource = scif1_resources,
58 .num_resources = ARRAY_SIZE(scif1_resources),
60 .platform_data = &scif1_platform_data,
64 static struct sh_timer_config tmu0_platform_data = {
65 .channel_offset = 0x04,
67 .clockevent_rating = 200,
70 static struct resource tmu0_resources[] = {
74 .flags = IORESOURCE_MEM,
77 .start = evt2irq(0x580),
78 .flags = IORESOURCE_IRQ,
82 static struct platform_device tmu0_device = {
86 .platform_data = &tmu0_platform_data,
88 .resource = tmu0_resources,
89 .num_resources = ARRAY_SIZE(tmu0_resources),
92 static struct sh_timer_config tmu1_platform_data = {
93 .channel_offset = 0x10,
95 .clocksource_rating = 200,
98 static struct resource tmu1_resources[] = {
102 .flags = IORESOURCE_MEM,
105 .start = evt2irq(0x5a0),
106 .flags = IORESOURCE_IRQ,
110 static struct platform_device tmu1_device = {
114 .platform_data = &tmu1_platform_data,
116 .resource = tmu1_resources,
117 .num_resources = ARRAY_SIZE(tmu1_resources),
120 static struct sh_timer_config tmu2_platform_data = {
121 .channel_offset = 0x1c,
125 static struct resource tmu2_resources[] = {
129 .flags = IORESOURCE_MEM,
132 .start = evt2irq(0x5c0),
133 .flags = IORESOURCE_IRQ,
137 static struct platform_device tmu2_device = {
141 .platform_data = &tmu2_platform_data,
143 .resource = tmu2_resources,
144 .num_resources = ARRAY_SIZE(tmu2_resources),
147 static struct sh_timer_config tmu3_platform_data = {
148 .channel_offset = 0x04,
152 static struct resource tmu3_resources[] = {
156 .flags = IORESOURCE_MEM,
159 .start = evt2irq(0xe00),
160 .flags = IORESOURCE_IRQ,
164 static struct platform_device tmu3_device = {
168 .platform_data = &tmu3_platform_data,
170 .resource = tmu3_resources,
171 .num_resources = ARRAY_SIZE(tmu3_resources),
174 static struct sh_timer_config tmu4_platform_data = {
175 .channel_offset = 0x10,
179 static struct resource tmu4_resources[] = {
183 .flags = IORESOURCE_MEM,
186 .start = evt2irq(0xe20),
187 .flags = IORESOURCE_IRQ,
191 static struct platform_device tmu4_device = {
195 .platform_data = &tmu4_platform_data,
197 .resource = tmu4_resources,
198 .num_resources = ARRAY_SIZE(tmu4_resources),
201 static struct sh_timer_config tmu5_platform_data = {
202 .channel_offset = 0x1c,
206 static struct resource tmu5_resources[] = {
210 .flags = IORESOURCE_MEM,
213 .start = evt2irq(0xe40),
214 .flags = IORESOURCE_IRQ,
218 static struct platform_device tmu5_device = {
222 .platform_data = &tmu5_platform_data,
224 .resource = tmu5_resources,
225 .num_resources = ARRAY_SIZE(tmu5_resources),
228 static struct resource rtc_resources[] = {
231 .end = 0xffe80000 + 0x58 - 1,
232 .flags = IORESOURCE_IO,
235 /* Shared Period/Carry/Alarm IRQ */
236 .start = evt2irq(0x480),
237 .flags = IORESOURCE_IRQ,
241 static struct platform_device rtc_device = {
244 .num_resources = ARRAY_SIZE(rtc_resources),
245 .resource = rtc_resources,
249 static const struct sh_dmae_channel sh7780_dmae0_channels[] = {
277 static const struct sh_dmae_channel sh7780_dmae1_channels[] = {
293 static const unsigned int ts_shift[] = TS_SHIFT;
295 static struct sh_dmae_pdata dma0_platform_data = {
296 .channel = sh7780_dmae0_channels,
297 .channel_num = ARRAY_SIZE(sh7780_dmae0_channels),
298 .ts_low_shift = CHCR_TS_LOW_SHIFT,
299 .ts_low_mask = CHCR_TS_LOW_MASK,
300 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
301 .ts_high_mask = CHCR_TS_HIGH_MASK,
302 .ts_shift = ts_shift,
303 .ts_shift_num = ARRAY_SIZE(ts_shift),
304 .dmaor_init = DMAOR_INIT,
307 static struct sh_dmae_pdata dma1_platform_data = {
308 .channel = sh7780_dmae1_channels,
309 .channel_num = ARRAY_SIZE(sh7780_dmae1_channels),
310 .ts_low_shift = CHCR_TS_LOW_SHIFT,
311 .ts_low_mask = CHCR_TS_LOW_MASK,
312 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
313 .ts_high_mask = CHCR_TS_HIGH_MASK,
314 .ts_shift = ts_shift,
315 .ts_shift_num = ARRAY_SIZE(ts_shift),
316 .dmaor_init = DMAOR_INIT,
319 static struct resource sh7780_dmae0_resources[] = {
321 /* Channel registers and DMAOR */
324 .flags = IORESOURCE_MEM,
330 .flags = IORESOURCE_MEM,
334 * Real DMA error vector is 0x6c0, and channel
335 * vectors are 0x640-0x6a0, 0x780-0x7a0
338 .start = evt2irq(0x640),
339 .end = evt2irq(0x640),
340 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
344 static struct resource sh7780_dmae1_resources[] = {
346 /* Channel registers and DMAOR */
349 .flags = IORESOURCE_MEM,
351 /* DMAC1 has no DMARS */
354 * Real DMA error vector is 0x6c0, and channel
355 * vectors are 0x7c0-0x7e0, 0xd80-0xde0
358 .start = evt2irq(0x7c0),
359 .end = evt2irq(0x7c0),
360 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
364 static struct platform_device dma0_device = {
365 .name = "sh-dma-engine",
367 .resource = sh7780_dmae0_resources,
368 .num_resources = ARRAY_SIZE(sh7780_dmae0_resources),
370 .platform_data = &dma0_platform_data,
374 static struct platform_device dma1_device = {
375 .name = "sh-dma-engine",
377 .resource = sh7780_dmae1_resources,
378 .num_resources = ARRAY_SIZE(sh7780_dmae1_resources),
380 .platform_data = &dma1_platform_data,
384 static struct platform_device *sh7780_devices[] __initdata = {
398 static int __init sh7780_devices_setup(void)
400 return platform_add_devices(sh7780_devices,
401 ARRAY_SIZE(sh7780_devices));
403 arch_initcall(sh7780_devices_setup);
405 static struct platform_device *sh7780_early_devices[] __initdata = {
416 void __init plat_early_device_setup(void)
418 if (mach_is_sh2007()) {
419 scif0_platform_data.scscr &= ~SCSCR_CKE1;
420 scif1_platform_data.scscr &= ~SCSCR_CKE1;
423 early_platform_add_devices(sh7780_early_devices,
424 ARRAY_SIZE(sh7780_early_devices));
430 /* interrupt sources */
432 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
433 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
434 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
435 IRL_HHLL, IRL_HHLH, IRL_HHHL,
437 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
438 RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
439 HUDI, DMAC0, SCIF0, DMAC1, CMT, HAC,
440 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
441 SCIF1, SIOF, HSPI, MMCIF, TMU3, TMU4, TMU5, SSI, FLCTL, GPIO,
443 /* interrupt groups */
448 static struct intc_vect vectors[] __initdata = {
449 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
450 INTC_VECT(RTC, 0x4c0),
451 INTC_VECT(WDT, 0x560),
452 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
453 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
454 INTC_VECT(HUDI, 0x600),
455 INTC_VECT(DMAC0, 0x640), INTC_VECT(DMAC0, 0x660),
456 INTC_VECT(DMAC0, 0x680), INTC_VECT(DMAC0, 0x6a0),
457 INTC_VECT(DMAC0, 0x6c0),
458 INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
459 INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
460 INTC_VECT(DMAC0, 0x780), INTC_VECT(DMAC0, 0x7a0),
461 INTC_VECT(DMAC1, 0x7c0), INTC_VECT(DMAC1, 0x7e0),
462 INTC_VECT(CMT, 0x900), INTC_VECT(HAC, 0x980),
463 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
464 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
465 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
466 INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
467 INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
468 INTC_VECT(SCIF1, 0xb80), INTC_VECT(SCIF1, 0xba0),
469 INTC_VECT(SCIF1, 0xbc0), INTC_VECT(SCIF1, 0xbe0),
470 INTC_VECT(SIOF, 0xc00), INTC_VECT(HSPI, 0xc80),
471 INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
472 INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
473 INTC_VECT(DMAC1, 0xd80), INTC_VECT(DMAC1, 0xda0),
474 INTC_VECT(DMAC1, 0xdc0), INTC_VECT(DMAC1, 0xde0),
475 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
476 INTC_VECT(TMU5, 0xe40),
477 INTC_VECT(SSI, 0xe80),
478 INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
479 INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
480 INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
481 INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
484 static struct intc_group groups[] __initdata = {
485 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
486 INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
489 static struct intc_mask_reg mask_registers[] __initdata = {
490 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
491 { 0, 0, 0, 0, 0, 0, GPIO, FLCTL,
492 SSI, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
493 PCIINTA, PCISERR, HAC, CMT, 0, 0, DMAC1, DMAC0,
494 HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
497 static struct intc_prio_reg prio_registers[] __initdata = {
498 { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
499 TMU2, TMU2_TICPI } },
500 { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } },
501 { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } },
502 { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { HUDI, DMAC0, DMAC1 } },
503 { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { CMT, HAC,
504 PCISERR, PCIINTA, } },
505 { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC,
507 { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { SIOF, HSPI, MMCIF, SSI } },
508 { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { FLCTL, GPIO } },
511 static DECLARE_INTC_DESC(intc_desc, "sh7780", vectors, groups,
512 mask_registers, prio_registers, NULL);
514 /* Support for external interrupt pins in IRQ mode */
516 static struct intc_vect irq_vectors[] __initdata = {
517 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
518 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
519 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
520 INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
523 static struct intc_mask_reg irq_mask_registers[] __initdata = {
524 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
525 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
528 static struct intc_prio_reg irq_prio_registers[] __initdata = {
529 { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
530 IRQ4, IRQ5, IRQ6, IRQ7 } },
533 static struct intc_sense_reg irq_sense_registers[] __initdata = {
534 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
535 IRQ4, IRQ5, IRQ6, IRQ7 } },
538 static struct intc_mask_reg irq_ack_registers[] __initdata = {
539 { 0xffd00024, 0, 32, /* INTREQ */
540 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
543 static DECLARE_INTC_DESC_ACK(intc_irq_desc, "sh7780-irq", irq_vectors,
544 NULL, irq_mask_registers, irq_prio_registers,
545 irq_sense_registers, irq_ack_registers);
547 /* External interrupt pins in IRL mode */
549 static struct intc_vect irl_vectors[] __initdata = {
550 INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
551 INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
552 INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
553 INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
554 INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
555 INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
556 INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
557 INTC_VECT(IRL_HHHL, 0x3c0),
560 static struct intc_mask_reg irl3210_mask_registers[] __initdata = {
561 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
562 { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
563 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
564 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
565 IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
568 static struct intc_mask_reg irl7654_mask_registers[] __initdata = {
569 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
570 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
571 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
572 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
573 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
574 IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
577 static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7780-irl7654", irl_vectors,
578 NULL, irl7654_mask_registers, NULL, NULL);
580 static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
581 NULL, irl3210_mask_registers, NULL, NULL);
583 #define INTC_ICR0 0xffd00000
584 #define INTC_INTMSK0 0xffd00044
585 #define INTC_INTMSK1 0xffd00048
586 #define INTC_INTMSK2 0xffd40080
587 #define INTC_INTMSKCLR1 0xffd00068
588 #define INTC_INTMSKCLR2 0xffd40084
590 void __init plat_irq_setup(void)
593 __raw_writel(0xff000000, INTC_INTMSK0);
595 /* disable IRL3-0 + IRL7-4 */
596 __raw_writel(0xc0000000, INTC_INTMSK1);
597 __raw_writel(0xfffefffe, INTC_INTMSK2);
599 /* select IRL mode for IRL3-0 + IRL7-4 */
600 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
602 /* disable holding function, ie enable "SH-4 Mode" */
603 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
605 register_intc_controller(&intc_desc);
608 void __init plat_irq_setup_pins(int mode)
612 /* select IRQ mode for IRL3-0 + IRL7-4 */
613 __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
614 register_intc_controller(&intc_irq_desc);
616 case IRQ_MODE_IRL7654:
617 /* enable IRL7-4 but don't provide any masking */
618 __raw_writel(0x40000000, INTC_INTMSKCLR1);
619 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
621 case IRQ_MODE_IRL3210:
622 /* enable IRL0-3 but don't provide any masking */
623 __raw_writel(0x80000000, INTC_INTMSKCLR1);
624 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
626 case IRQ_MODE_IRL7654_MASK:
627 /* enable IRL7-4 and mask using cpu intc controller */
628 __raw_writel(0x40000000, INTC_INTMSKCLR1);
629 register_intc_controller(&intc_irl7654_desc);
631 case IRQ_MODE_IRL3210_MASK:
632 /* enable IRL0-3 and mask using cpu intc controller */
633 __raw_writel(0x80000000, INTC_INTMSKCLR1);
634 register_intc_controller(&intc_irl3210_desc);