arch/sh/kernel/cpu/sh4a/setup-sh7780.c

   1 /*
   2  * SH7780 Setup
   3  *
   4  *  Copyright (C) 2006  Paul Mundt
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/platform_device.h>
  11 #include <linux/init.h>
  12 #include <linux/serial.h>
  13 #include <linux/io.h>
  14 #include <linux/serial_sci.h>
  15 #include <linux/sh_dma.h>
  16 #include <linux/sh_timer.h>
  17
  18 #include <cpu/dma-register.h>
  19
  20 static struct plat_sci_port scif0_platform_data = {
  21         .mapbase        = 0xffe00000,
  22         .flags          = UPF_BOOT_AUTOCONF,
  23         .type           = PORT_SCIF,
  24         .irqs           = { 40, 40, 40, 40 },
  25 };
  26
  27 static struct platform_device scif0_device = {
  28         .name           = "sh-sci",
  29         .id             = 0,
  30         .dev            = {
  31                 .platform_data  = &scif0_platform_data,
  32         },
  33 };
  34
  35 static struct plat_sci_port scif1_platform_data = {
  36         .mapbase        = 0xffe10000,
  37         .flags          = UPF_BOOT_AUTOCONF,
  38         .type           = PORT_SCIF,
  39         .irqs           = { 76, 76, 76, 76 },
  40 };
  41
  42 static struct platform_device scif1_device = {
  43         .name           = "sh-sci",
  44         .id             = 1,
  45         .dev            = {
  46                 .platform_data  = &scif1_platform_data,
  47         },
  48 };
  49
  50 static struct sh_timer_config tmu0_platform_data = {
  51         .channel_offset = 0x04,
  52         .timer_bit = 0,
  53         .clockevent_rating = 200,
  54 };
  55
  56 static struct resource tmu0_resources[] = {
  57         [0] = {
  58                 .start  = 0xffd80008,
  59                 .end    = 0xffd80013,
  60                 .flags  = IORESOURCE_MEM,
  61         },
  62         [1] = {
  63                 .start  = 28,
  64                 .flags  = IORESOURCE_IRQ,
  65         },
  66 };
  67
  68 static struct platform_device tmu0_device = {
  69         .name           = "sh_tmu",
  70         .id             = 0,
  71         .dev = {
  72                 .platform_data  = &tmu0_platform_data,
  73         },
  74         .resource       = tmu0_resources,
  75         .num_resources  = ARRAY_SIZE(tmu0_resources),
  76 };
  77
  78 static struct sh_timer_config tmu1_platform_data = {
  79         .channel_offset = 0x10,
  80         .timer_bit = 1,
  81         .clocksource_rating = 200,
  82 };
  83
  84 static struct resource tmu1_resources[] = {
  85         [0] = {
  86                 .start  = 0xffd80014,
  87                 .end    = 0xffd8001f,
  88                 .flags  = IORESOURCE_MEM,
  89         },
  90         [1] = {
  91                 .start  = 29,
  92                 .flags  = IORESOURCE_IRQ,
  93         },
  94 };
  95
  96 static struct platform_device tmu1_device = {
  97         .name           = "sh_tmu",
  98         .id             = 1,
  99         .dev = {
 100                 .platform_data  = &tmu1_platform_data,
 101         },
 102         .resource       = tmu1_resources,
 103         .num_resources  = ARRAY_SIZE(tmu1_resources),
 104 };
 105
 106 static struct sh_timer_config tmu2_platform_data = {
 107         .channel_offset = 0x1c,
 108         .timer_bit = 2,
 109 };
 110
 111 static struct resource tmu2_resources[] = {
 112         [0] = {
 113                 .start  = 0xffd80020,
 114                 .end    = 0xffd8002f,
 115                 .flags  = IORESOURCE_MEM,
 116         },
 117         [1] = {
 118                 .start  = 30,
 119                 .flags  = IORESOURCE_IRQ,
 120         },
 121 };
 122
 123 static struct platform_device tmu2_device = {
 124         .name           = "sh_tmu",
 125         .id             = 2,
 126         .dev = {
 127                 .platform_data  = &tmu2_platform_data,
 128         },
 129         .resource       = tmu2_resources,
 130         .num_resources  = ARRAY_SIZE(tmu2_resources),
 131 };
 132
 133 static struct sh_timer_config tmu3_platform_data = {
 134         .channel_offset = 0x04,
 135         .timer_bit = 0,
 136 };
 137
 138 static struct resource tmu3_resources[] = {
 139         [0] = {
 140                 .start  = 0xffdc0008,
 141                 .end    = 0xffdc0013,
 142                 .flags  = IORESOURCE_MEM,
 143         },
 144         [1] = {
 145                 .start  = 96,
 146                 .flags  = IORESOURCE_IRQ,
 147         },
 148 };
 149
 150 static struct platform_device tmu3_device = {
 151         .name           = "sh_tmu",
 152         .id             = 3,
 153         .dev = {
 154                 .platform_data  = &tmu3_platform_data,
 155         },
 156         .resource       = tmu3_resources,
 157         .num_resources  = ARRAY_SIZE(tmu3_resources),
 158 };
 159
 160 static struct sh_timer_config tmu4_platform_data = {
 161         .channel_offset = 0x10,
 162         .timer_bit = 1,
 163 };
 164
 165 static struct resource tmu4_resources[] = {
 166         [0] = {
 167                 .start  = 0xffdc0014,
 168                 .end    = 0xffdc001f,
 169                 .flags  = IORESOURCE_MEM,
 170         },
 171         [1] = {
 172                 .start  = 97,
 173                 .flags  = IORESOURCE_IRQ,
 174         },
 175 };
 176
 177 static struct platform_device tmu4_device = {
 178         .name           = "sh_tmu",
 179         .id             = 4,
 180         .dev = {
 181                 .platform_data  = &tmu4_platform_data,
 182         },
 183         .resource       = tmu4_resources,
 184         .num_resources  = ARRAY_SIZE(tmu4_resources),
 185 };
 186
 187 static struct sh_timer_config tmu5_platform_data = {
 188         .channel_offset = 0x1c,
 189         .timer_bit = 2,
 190 };
 191
 192 static struct resource tmu5_resources[] = {
 193         [0] = {
 194                 .start  = 0xffdc0020,
 195                 .end    = 0xffdc002b,
 196                 .flags  = IORESOURCE_MEM,
 197         },
 198         [1] = {
 199                 .start  = 98,
 200                 .flags  = IORESOURCE_IRQ,
 201         },
 202 };
 203
 204 static struct platform_device tmu5_device = {
 205         .name           = "sh_tmu",
 206         .id             = 5,
 207         .dev = {
 208                 .platform_data  = &tmu5_platform_data,
 209         },
 210         .resource       = tmu5_resources,
 211         .num_resources  = ARRAY_SIZE(tmu5_resources),
 212 };
 213
 214 static struct resource rtc_resources[] = {
 215         [0] = {
 216                 .start  = 0xffe80000,
 217                 .end    = 0xffe80000 + 0x58 - 1,
 218                 .flags  = IORESOURCE_IO,
 219         },
 220         [1] = {
 221                 /* Shared Period/Carry/Alarm IRQ */
 222                 .start  = 20,
 223                 .flags  = IORESOURCE_IRQ,
 224         },
 225 };
 226
 227 static struct platform_device rtc_device = {
 228         .name           = "sh-rtc",
 229         .id             = -1,
 230         .num_resources  = ARRAY_SIZE(rtc_resources),
 231         .resource       = rtc_resources,
 232 };
 233
 234 /* DMA */
 235 static const struct sh_dmae_channel sh7780_dmae0_channels[] = {
 236         {
 237                 .offset = 0,
 238                 .dmars = 0,
 239                 .dmars_bit = 0,
 240         }, {
 241                 .offset = 0x10,
 242                 .dmars = 0,
 243                 .dmars_bit = 8,
 244         }, {
 245                 .offset = 0x20,
 246                 .dmars = 4,
 247                 .dmars_bit = 0,
 248         }, {
 249                 .offset = 0x30,
 250                 .dmars = 4,
 251                 .dmars_bit = 8,
 252         }, {
 253                 .offset = 0x50,
 254                 .dmars = 8,
 255                 .dmars_bit = 0,
 256         }, {
 257                 .offset = 0x60,
 258                 .dmars = 8,
 259                 .dmars_bit = 8,
 260         }
 261 };
 262
 263 static const struct sh_dmae_channel sh7780_dmae1_channels[] = {
 264         {
 265                 .offset = 0,
 266         }, {
 267                 .offset = 0x10,
 268         }, {
 269                 .offset = 0x20,
 270         }, {
 271                 .offset = 0x30,
 272         }, {
 273                 .offset = 0x50,
 274         }, {
 275                 .offset = 0x60,
 276         }
 277 };
 278
 279 static const unsigned int ts_shift[] = TS_SHIFT;
 280
 281 static struct sh_dmae_pdata dma0_platform_data = {
 282         .channel        = sh7780_dmae0_channels,
 283         .channel_num    = ARRAY_SIZE(sh7780_dmae0_channels),
 284         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
 285         .ts_low_mask    = CHCR_TS_LOW_MASK,
 286         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
 287         .ts_high_mask   = CHCR_TS_HIGH_MASK,
 288         .ts_shift       = ts_shift,
 289         .ts_shift_num   = ARRAY_SIZE(ts_shift),
 290         .dmaor_init     = DMAOR_INIT,
 291 };
 292
 293 static struct sh_dmae_pdata dma1_platform_data = {
 294         .channel        = sh7780_dmae1_channels,
 295         .channel_num    = ARRAY_SIZE(sh7780_dmae1_channels),
 296         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
 297         .ts_low_mask    = CHCR_TS_LOW_MASK,
 298         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
 299         .ts_high_mask   = CHCR_TS_HIGH_MASK,
 300         .ts_shift       = ts_shift,
 301         .ts_shift_num   = ARRAY_SIZE(ts_shift),
 302         .dmaor_init     = DMAOR_INIT,
 303 };
 304
 305 static struct resource sh7780_dmae0_resources[] = {
 306         [0] = {
 307                 /* Channel registers and DMAOR */
 308                 .start  = 0xfc808020,
 309                 .end    = 0xfc80808f,
 310                 .flags  = IORESOURCE_MEM,
 311         },
 312         [1] = {
 313                 /* DMARSx */
 314                 .start  = 0xfc809000,
 315                 .end    = 0xfc80900b,
 316                 .flags  = IORESOURCE_MEM,
 317         },
 318         {
 319                 /* Real DMA error IRQ is 38, and channel IRQs are 34-37, 44-45 */
 320                 .start  = 34,
 321                 .end    = 34,
 322                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 323         },
 324 };
 325
 326 static struct resource sh7780_dmae1_resources[] = {
 327         [0] = {
 328                 /* Channel registers and DMAOR */
 329                 .start  = 0xfc818020,
 330                 .end    = 0xfc81808f,
 331                 .flags  = IORESOURCE_MEM,
 332         },
 333         /* DMAC1 has no DMARS */
 334         {
 335                 /* Real DMA error IRQ is 38, and channel IRQs are 46-47, 92-95 */
 336                 .start  = 46,
 337                 .end    = 46,
 338                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 339         },
 340 };
 341
 342 static struct platform_device dma0_device = {
 343         .name           = "sh-dma-engine",
 344         .id             = 0,
 345         .resource       = sh7780_dmae0_resources,
 346         .num_resources  = ARRAY_SIZE(sh7780_dmae0_resources),
 347         .dev            = {
 348                 .platform_data  = &dma0_platform_data,
 349         },
 350 };
 351
 352 static struct platform_device dma1_device = {
 353         .name           = "sh-dma-engine",
 354         .id             = 1,
 355         .resource       = sh7780_dmae1_resources,
 356         .num_resources  = ARRAY_SIZE(sh7780_dmae1_resources),
 357         .dev            = {
 358                 .platform_data  = &dma1_platform_data,
 359         },
 360 };
 361
 362 static struct platform_device *sh7780_devices[] __initdata = {
 363         &scif0_device,
 364         &scif1_device,
 365         &tmu0_device,
 366         &tmu1_device,
 367         &tmu2_device,
 368         &tmu3_device,
 369         &tmu4_device,
 370         &tmu5_device,
 371         &rtc_device,
 372         &dma0_device,
 373         &dma1_device,
 374 };
 375
 376 static int __init sh7780_devices_setup(void)
 377 {
 378         return platform_add_devices(sh7780_devices,
 379                                     ARRAY_SIZE(sh7780_devices));
 380 }
 381 arch_initcall(sh7780_devices_setup);
 382 static struct platform_device *sh7780_early_devices[] __initdata = {
 383         &scif0_device,
 384         &scif1_device,
 385         &tmu0_device,
 386         &tmu1_device,
 387         &tmu2_device,
 388         &tmu3_device,
 389         &tmu4_device,
 390         &tmu5_device,
 391 };
 392
 393 void __init plat_early_device_setup(void)
 394 {
 395         early_platform_add_devices(sh7780_early_devices,
 396                                    ARRAY_SIZE(sh7780_early_devices));
 397 }
 398
 399 enum {
 400         UNUSED = 0,
 401
 402         /* interrupt sources */
 403
 404         IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 405         IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 406         IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 407         IRL_HHLL, IRL_HHLH, IRL_HHHL,
 408
 409         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 410         RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
 411         HUDI, DMAC0, SCIF0, DMAC1, CMT, HAC,
 412         PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
 413         SCIF1, SIOF, HSPI, MMCIF, TMU3, TMU4, TMU5, SSI, FLCTL, GPIO,
 414
 415         /* interrupt groups */
 416
 417         TMU012, TMU345,
 418 };
 419
 420 static struct intc_vect vectors[] __initdata = {
 421         INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
 422         INTC_VECT(RTC, 0x4c0),
 423         INTC_VECT(WDT, 0x560),
 424         INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
 425         INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
 426         INTC_VECT(HUDI, 0x600),
 427         INTC_VECT(DMAC0, 0x640), INTC_VECT(DMAC0, 0x660),
 428         INTC_VECT(DMAC0, 0x680), INTC_VECT(DMAC0, 0x6a0),
 429         INTC_VECT(DMAC0, 0x6c0),
 430         INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
 431         INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
 432         INTC_VECT(DMAC0, 0x780), INTC_VECT(DMAC0, 0x7a0),
 433         INTC_VECT(DMAC1, 0x7c0), INTC_VECT(DMAC1, 0x7e0),
 434         INTC_VECT(CMT, 0x900), INTC_VECT(HAC, 0x980),
 435         INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
 436         INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
 437         INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
 438         INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
 439         INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
 440         INTC_VECT(SCIF1, 0xb80), INTC_VECT(SCIF1, 0xba0),
 441         INTC_VECT(SCIF1, 0xbc0), INTC_VECT(SCIF1, 0xbe0),
 442         INTC_VECT(SIOF, 0xc00), INTC_VECT(HSPI, 0xc80),
 443         INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
 444         INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
 445         INTC_VECT(DMAC1, 0xd80), INTC_VECT(DMAC1, 0xda0),
 446         INTC_VECT(DMAC1, 0xdc0), INTC_VECT(DMAC1, 0xde0),
 447         INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
 448         INTC_VECT(TMU5, 0xe40),
 449         INTC_VECT(SSI, 0xe80),
 450         INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
 451         INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
 452         INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
 453         INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
 454 };
 455
 456 static struct intc_group groups[] __initdata = {
 457         INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
 458         INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
 459 };
 460
 461 static struct intc_mask_reg mask_registers[] __initdata = {
 462         { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
 463           { 0, 0, 0, 0, 0, 0, GPIO, FLCTL,
 464             SSI, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
 465             PCIINTA, PCISERR, HAC, CMT, 0, 0, DMAC1, DMAC0,
 466             HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
 467 };
 468
 469 static struct intc_prio_reg prio_registers[] __initdata = {
 470         { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
 471                                                  TMU2, TMU2_TICPI } },
 472         { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } },
 473         { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } },
 474         { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { HUDI, DMAC0, DMAC1 } },
 475         { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { CMT, HAC,
 476                                                  PCISERR, PCIINTA, } },
 477         { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC,
 478                                                  PCIINTD, PCIC5 } },
 479         { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { SIOF, HSPI, MMCIF, SSI } },
 480         { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { FLCTL, GPIO } },
 481 };
 482
 483 static DECLARE_INTC_DESC(intc_desc, "sh7780", vectors, groups,
 484                          mask_registers, prio_registers, NULL);
 485
 486 /* Support for external interrupt pins in IRQ mode */
 487
 488 static struct intc_vect irq_vectors[] __initdata = {
 489         INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
 490         INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
 491         INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
 492         INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
 493 };
 494
 495 static struct intc_mask_reg irq_mask_registers[] __initdata = {
 496         { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
 497           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 498 };
 499
 500 static struct intc_prio_reg irq_prio_registers[] __initdata = {
 501         { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
 502                                                IRQ4, IRQ5, IRQ6, IRQ7 } },
 503 };
 504
 505 static struct intc_sense_reg irq_sense_registers[] __initdata = {
 506         { 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
 507                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
 508 };
 509
 510 static struct intc_mask_reg irq_ack_registers[] __initdata = {
 511         { 0xffd00024, 0, 32, /* INTREQ */
 512           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 513 };
 514
 515 static DECLARE_INTC_DESC_ACK(intc_irq_desc, "sh7780-irq", irq_vectors,
 516                              NULL, irq_mask_registers, irq_prio_registers,
 517                              irq_sense_registers, irq_ack_registers);
 518
 519 /* External interrupt pins in IRL mode */
 520
 521 static struct intc_vect irl_vectors[] __initdata = {
 522         INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
 523         INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
 524         INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
 525         INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
 526         INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
 527         INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
 528         INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
 529         INTC_VECT(IRL_HHHL, 0x3c0),
 530 };
 531
 532 static struct intc_mask_reg irl3210_mask_registers[] __initdata = {
 533         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 534           { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 535             IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 536             IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 537             IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
 538 };
 539
 540 static struct intc_mask_reg irl7654_mask_registers[] __initdata = {
 541         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 542           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 543             IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 544             IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 545             IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 546             IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
 547 };
 548
 549 static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7780-irl7654", irl_vectors,
 550                          NULL, irl7654_mask_registers, NULL, NULL);
 551
 552 static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
 553                          NULL, irl3210_mask_registers, NULL, NULL);
 554
 555 #define INTC_ICR0       0xffd00000
 556 #define INTC_INTMSK0    0xffd00044
 557 #define INTC_INTMSK1    0xffd00048
 558 #define INTC_INTMSK2    0xffd40080
 559 #define INTC_INTMSKCLR1 0xffd00068
 560 #define INTC_INTMSKCLR2 0xffd40084
 561
 562 void __init plat_irq_setup(void)
 563 {
 564         /* disable IRQ7-0 */
 565         __raw_writel(0xff000000, INTC_INTMSK0);
 566
 567         /* disable IRL3-0 + IRL7-4 */
 568         __raw_writel(0xc0000000, INTC_INTMSK1);
 569         __raw_writel(0xfffefffe, INTC_INTMSK2);
 570
 571         /* select IRL mode for IRL3-0 + IRL7-4 */
 572         __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 573
 574         /* disable holding function, ie enable "SH-4 Mode" */
 575         __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
 576
 577         register_intc_controller(&intc_desc);
 578 }
 579
 580 void __init plat_irq_setup_pins(int mode)
 581 {
 582         switch (mode) {
 583         case IRQ_MODE_IRQ:
 584                 /* select IRQ mode for IRL3-0 + IRL7-4 */
 585                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
 586                 register_intc_controller(&intc_irq_desc);
 587                 break;
 588         case IRQ_MODE_IRL7654:
 589                 /* enable IRL7-4 but don't provide any masking */
 590                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 591                 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
 592                 break;
 593         case IRQ_MODE_IRL3210:
 594                 /* enable IRL0-3 but don't provide any masking */
 595                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 596                 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
 597                 break;
 598         case IRQ_MODE_IRL7654_MASK:
 599                 /* enable IRL7-4 and mask using cpu intc controller */
 600                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 601                 register_intc_controller(&intc_irl7654_desc);
 602                 break;
 603         case IRQ_MODE_IRL3210_MASK:
 604                 /* enable IRL0-3 and mask using cpu intc controller */
 605                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 606                 register_intc_controller(&intc_irl3210_desc);
 607                 break;
 608         default:
 609                 BUG();
 610         }
 611 }