arch/sh/kernel/cpu/sh4a/setup-sh7770.c

   1 /*
   2  * SH7770 Setup
   3  *
   4  *  Copyright (C) 2006 - 2008  Paul Mundt
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/platform_device.h>
  11 #include <linux/init.h>
  12 #include <linux/serial.h>
  13 #include <linux/serial_sci.h>
  14 #include <linux/sh_timer.h>
  15 #include <linux/io.h>
  16
  17 static struct plat_sci_port scif0_platform_data = {
  18         .mapbase        = 0xff923000,
  19         .flags          = UPF_BOOT_AUTOCONF,
  20         .type           = PORT_SCIF,
  21         .irqs           = { 61, 61, 61, 61 },
  22 };
  23
  24 static struct platform_device scif0_device = {
  25         .name           = "sh-sci",
  26         .id             = 0,
  27         .dev            = {
  28                 .platform_data  = &scif0_platform_data,
  29         },
  30 };
  31
  32 static struct plat_sci_port scif1_platform_data = {
  33         .mapbase        = 0xff924000,
  34         .flags          = UPF_BOOT_AUTOCONF,
  35         .type           = PORT_SCIF,
  36         .irqs           = { 62, 62, 62, 62 },
  37 };
  38
  39 static struct platform_device scif1_device = {
  40         .name           = "sh-sci",
  41         .id             = 1,
  42         .dev            = {
  43                 .platform_data  = &scif1_platform_data,
  44         },
  45 };
  46
  47 static struct plat_sci_port scif2_platform_data = {
  48         .mapbase        = 0xff925000,
  49         .flags          = UPF_BOOT_AUTOCONF,
  50         .type           = PORT_SCIF,
  51         .irqs           = { 63, 63, 63, 63 },
  52 };
  53
  54 static struct platform_device scif2_device = {
  55         .name           = "sh-sci",
  56         .id             = 2,
  57         .dev            = {
  58                 .platform_data  = &scif2_platform_data,
  59         },
  60 };
  61
  62 static struct plat_sci_port scif3_platform_data = {
  63         .mapbase        = 0xff926000,
  64         .flags          = UPF_BOOT_AUTOCONF,
  65         .type           = PORT_SCIF,
  66         .irqs           = { 64, 64, 64, 64 },
  67 };
  68
  69 static struct platform_device scif3_device = {
  70         .name           = "sh-sci",
  71         .id             = 3,
  72         .dev            = {
  73                 .platform_data  = &scif3_platform_data,
  74         },
  75 };
  76
  77 static struct plat_sci_port scif4_platform_data = {
  78         .mapbase        = 0xff927000,
  79         .flags          = UPF_BOOT_AUTOCONF,
  80         .type           = PORT_SCIF,
  81         .irqs           = { 65, 65, 65, 65 },
  82 };
  83
  84 static struct platform_device scif4_device = {
  85         .name           = "sh-sci",
  86         .id             = 4,
  87         .dev            = {
  88                 .platform_data  = &scif4_platform_data,
  89         },
  90 };
  91
  92 static struct plat_sci_port scif5_platform_data = {
  93         .mapbase        = 0xff928000,
  94         .flags          = UPF_BOOT_AUTOCONF,
  95         .type           = PORT_SCIF,
  96         .irqs           = { 66, 66, 66, 66 },
  97 };
  98
  99 static struct platform_device scif5_device = {
 100         .name           = "sh-sci",
 101         .id             = 5,
 102         .dev            = {
 103                 .platform_data  = &scif5_platform_data,
 104         },
 105 };
 106
 107 static struct plat_sci_port scif6_platform_data = {
 108         .mapbase        = 0xff929000,
 109         .flags          = UPF_BOOT_AUTOCONF,
 110         .type           = PORT_SCIF,
 111         .irqs           = { 67, 67, 67, 67 },
 112 };
 113
 114 static struct platform_device scif6_device = {
 115         .name           = "sh-sci",
 116         .id             = 6,
 117         .dev            = {
 118                 .platform_data  = &scif6_platform_data,
 119         },
 120 };
 121
 122 static struct plat_sci_port scif7_platform_data = {
 123         .mapbase        = 0xff92a000,
 124         .flags          = UPF_BOOT_AUTOCONF,
 125         .type           = PORT_SCIF,
 126         .irqs           = { 68, 68, 68, 68 },
 127 };
 128
 129 static struct platform_device scif7_device = {
 130         .name           = "sh-sci",
 131         .id             = 7,
 132         .dev            = {
 133                 .platform_data  = &scif7_platform_data,
 134         },
 135 };
 136
 137 static struct plat_sci_port scif8_platform_data = {
 138         .mapbase        = 0xff92b000,
 139         .flags          = UPF_BOOT_AUTOCONF,
 140         .type           = PORT_SCIF,
 141         .irqs           = { 69, 69, 69, 69 },
 142 };
 143
 144 static struct platform_device scif8_device = {
 145         .name           = "sh-sci",
 146         .id             = 8,
 147         .dev            = {
 148                 .platform_data  = &scif8_platform_data,
 149         },
 150 };
 151
 152 static struct plat_sci_port scif9_platform_data = {
 153         .mapbase        = 0xff92c000,
 154         .flags          = UPF_BOOT_AUTOCONF,
 155         .type           = PORT_SCIF,
 156         .irqs           = { 70, 70, 70, 70 },
 157 };
 158
 159 static struct platform_device scif9_device = {
 160         .name           = "sh-sci",
 161         .id             = 9,
 162         .dev            = {
 163                 .platform_data  = &scif9_platform_data,
 164         },
 165 };
 166
 167 static struct sh_timer_config tmu0_platform_data = {
 168         .channel_offset = 0x04,
 169         .timer_bit = 0,
 170         .clockevent_rating = 200,
 171 };
 172
 173 static struct resource tmu0_resources[] = {
 174         [0] = {
 175                 .start  = 0xffd80008,
 176                 .end    = 0xffd80013,
 177                 .flags  = IORESOURCE_MEM,
 178         },
 179         [1] = {
 180                 .start  = 16,
 181                 .flags  = IORESOURCE_IRQ,
 182         },
 183 };
 184
 185 static struct platform_device tmu0_device = {
 186         .name           = "sh_tmu",
 187         .id             = 0,
 188         .dev = {
 189                 .platform_data  = &tmu0_platform_data,
 190         },
 191         .resource       = tmu0_resources,
 192         .num_resources  = ARRAY_SIZE(tmu0_resources),
 193 };
 194
 195 static struct sh_timer_config tmu1_platform_data = {
 196         .channel_offset = 0x10,
 197         .timer_bit = 1,
 198         .clocksource_rating = 200,
 199 };
 200
 201 static struct resource tmu1_resources[] = {
 202         [0] = {
 203                 .start  = 0xffd80014,
 204                 .end    = 0xffd8001f,
 205                 .flags  = IORESOURCE_MEM,
 206         },
 207         [1] = {
 208                 .start  = 17,
 209                 .flags  = IORESOURCE_IRQ,
 210         },
 211 };
 212
 213 static struct platform_device tmu1_device = {
 214         .name           = "sh_tmu",
 215         .id             = 1,
 216         .dev = {
 217                 .platform_data  = &tmu1_platform_data,
 218         },
 219         .resource       = tmu1_resources,
 220         .num_resources  = ARRAY_SIZE(tmu1_resources),
 221 };
 222
 223 static struct sh_timer_config tmu2_platform_data = {
 224         .channel_offset = 0x1c,
 225         .timer_bit = 2,
 226 };
 227
 228 static struct resource tmu2_resources[] = {
 229         [0] = {
 230                 .start  = 0xffd80020,
 231                 .end    = 0xffd8002f,
 232                 .flags  = IORESOURCE_MEM,
 233         },
 234         [1] = {
 235                 .start  = 18,
 236                 .flags  = IORESOURCE_IRQ,
 237         },
 238 };
 239
 240 static struct platform_device tmu2_device = {
 241         .name           = "sh_tmu",
 242         .id             = 2,
 243         .dev = {
 244                 .platform_data  = &tmu2_platform_data,
 245         },
 246         .resource       = tmu2_resources,
 247         .num_resources  = ARRAY_SIZE(tmu2_resources),
 248 };
 249
 250 static struct sh_timer_config tmu3_platform_data = {
 251         .channel_offset = 0x04,
 252         .timer_bit = 0,
 253 };
 254
 255 static struct resource tmu3_resources[] = {
 256         [0] = {
 257                 .start  = 0xffd81008,
 258                 .end    = 0xffd81013,
 259                 .flags  = IORESOURCE_MEM,
 260         },
 261         [1] = {
 262                 .start  = 19,
 263                 .flags  = IORESOURCE_IRQ,
 264         },
 265 };
 266
 267 static struct platform_device tmu3_device = {
 268         .name           = "sh_tmu",
 269         .id             = 3,
 270         .dev = {
 271                 .platform_data  = &tmu3_platform_data,
 272         },
 273         .resource       = tmu3_resources,
 274         .num_resources  = ARRAY_SIZE(tmu3_resources),
 275 };
 276
 277 static struct sh_timer_config tmu4_platform_data = {
 278         .channel_offset = 0x10,
 279         .timer_bit = 1,
 280 };
 281
 282 static struct resource tmu4_resources[] = {
 283         [0] = {
 284                 .start  = 0xffd81014,
 285                 .end    = 0xffd8101f,
 286                 .flags  = IORESOURCE_MEM,
 287         },
 288         [1] = {
 289                 .start  = 20,
 290                 .flags  = IORESOURCE_IRQ,
 291         },
 292 };
 293
 294 static struct platform_device tmu4_device = {
 295         .name           = "sh_tmu",
 296         .id             = 4,
 297         .dev = {
 298                 .platform_data  = &tmu4_platform_data,
 299         },
 300         .resource       = tmu4_resources,
 301         .num_resources  = ARRAY_SIZE(tmu4_resources),
 302 };
 303
 304 static struct sh_timer_config tmu5_platform_data = {
 305         .channel_offset = 0x1c,
 306         .timer_bit = 2,
 307 };
 308
 309 static struct resource tmu5_resources[] = {
 310         [0] = {
 311                 .start  = 0xffd81020,
 312                 .end    = 0xffd8102f,
 313                 .flags  = IORESOURCE_MEM,
 314         },
 315         [1] = {
 316                 .start  = 21,
 317                 .flags  = IORESOURCE_IRQ,
 318         },
 319 };
 320
 321 static struct platform_device tmu5_device = {
 322         .name           = "sh_tmu",
 323         .id             = 5,
 324         .dev = {
 325                 .platform_data  = &tmu5_platform_data,
 326         },
 327         .resource       = tmu5_resources,
 328         .num_resources  = ARRAY_SIZE(tmu5_resources),
 329 };
 330
 331 static struct sh_timer_config tmu6_platform_data = {
 332         .channel_offset = 0x04,
 333         .timer_bit = 0,
 334 };
 335
 336 static struct resource tmu6_resources[] = {
 337         [0] = {
 338                 .start  = 0xffd82008,
 339                 .end    = 0xffd82013,
 340                 .flags  = IORESOURCE_MEM,
 341         },
 342         [1] = {
 343                 .start  = 22,
 344                 .flags  = IORESOURCE_IRQ,
 345         },
 346 };
 347
 348 static struct platform_device tmu6_device = {
 349         .name           = "sh_tmu",
 350         .id             = 6,
 351         .dev = {
 352                 .platform_data  = &tmu6_platform_data,
 353         },
 354         .resource       = tmu6_resources,
 355         .num_resources  = ARRAY_SIZE(tmu6_resources),
 356 };
 357
 358 static struct sh_timer_config tmu7_platform_data = {
 359         .channel_offset = 0x10,
 360         .timer_bit = 1,
 361 };
 362
 363 static struct resource tmu7_resources[] = {
 364         [0] = {
 365                 .start  = 0xffd82014,
 366                 .end    = 0xffd8201f,
 367                 .flags  = IORESOURCE_MEM,
 368         },
 369         [1] = {
 370                 .start  = 23,
 371                 .flags  = IORESOURCE_IRQ,
 372         },
 373 };
 374
 375 static struct platform_device tmu7_device = {
 376         .name           = "sh_tmu",
 377         .id             = 7,
 378         .dev = {
 379                 .platform_data  = &tmu7_platform_data,
 380         },
 381         .resource       = tmu7_resources,
 382         .num_resources  = ARRAY_SIZE(tmu7_resources),
 383 };
 384
 385 static struct sh_timer_config tmu8_platform_data = {
 386         .channel_offset = 0x1c,
 387         .timer_bit = 2,
 388 };
 389
 390 static struct resource tmu8_resources[] = {
 391         [0] = {
 392                 .start  = 0xffd82020,
 393                 .end    = 0xffd8202b,
 394                 .flags  = IORESOURCE_MEM,
 395         },
 396         [1] = {
 397                 .start  = 24,
 398                 .flags  = IORESOURCE_IRQ,
 399         },
 400 };
 401
 402 static struct platform_device tmu8_device = {
 403         .name           = "sh_tmu",
 404         .id             = 8,
 405         .dev = {
 406                 .platform_data  = &tmu8_platform_data,
 407         },
 408         .resource       = tmu8_resources,
 409         .num_resources  = ARRAY_SIZE(tmu8_resources),
 410 };
 411
 412 static struct platform_device *sh7770_devices[] __initdata = {
 413         &scif0_device,
 414         &scif1_device,
 415         &scif2_device,
 416         &scif3_device,
 417         &scif4_device,
 418         &scif5_device,
 419         &scif6_device,
 420         &scif7_device,
 421         &scif8_device,
 422         &scif9_device,
 423         &tmu0_device,
 424         &tmu1_device,
 425         &tmu2_device,
 426         &tmu3_device,
 427         &tmu4_device,
 428         &tmu5_device,
 429         &tmu6_device,
 430         &tmu7_device,
 431         &tmu8_device,
 432 };
 433
 434 static int __init sh7770_devices_setup(void)
 435 {
 436         return platform_add_devices(sh7770_devices,
 437                                     ARRAY_SIZE(sh7770_devices));
 438 }
 439 arch_initcall(sh7770_devices_setup);
 440
 441 static struct platform_device *sh7770_early_devices[] __initdata = {
 442         &scif0_device,
 443         &scif1_device,
 444         &scif2_device,
 445         &scif3_device,
 446         &scif4_device,
 447         &scif5_device,
 448         &scif6_device,
 449         &scif7_device,
 450         &scif8_device,
 451         &scif9_device,
 452         &tmu0_device,
 453         &tmu1_device,
 454         &tmu2_device,
 455         &tmu3_device,
 456         &tmu4_device,
 457         &tmu5_device,
 458         &tmu6_device,
 459         &tmu7_device,
 460         &tmu8_device,
 461 };
 462
 463 void __init plat_early_device_setup(void)
 464 {
 465         early_platform_add_devices(sh7770_early_devices,
 466                                    ARRAY_SIZE(sh7770_early_devices));
 467 }
 468
 469 enum {
 470         UNUSED = 0,
 471
 472         /* interrupt sources */
 473         IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 474         IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 475         IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 476         IRL_HHLL, IRL_HHLH, IRL_HHHL,
 477
 478         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
 479
 480         GPIO,
 481         TMU0, TMU1, TMU2, TMU2_TICPI,
 482         TMU3, TMU4, TMU5, TMU5_TICPI,
 483         TMU6, TMU7, TMU8,
 484         HAC, IPI, SPDIF, HUDI, I2C,
 485         DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
 486         I2S0, I2S1, I2S2, I2S3,
 487         SRC_RX, SRC_TX, SRC_SPDIF,
 488         DU, VIDEO_IN, REMOTE, YUV, USB, ATAPI, CAN, GPS, GFX2D,
 489         GFX3D_MBX, GFX3D_DMAC,
 490         EXBUS_ATA,
 491         SPI0, SPI1,
 492         SCIF089, SCIF1234, SCIF567,
 493         ADC,
 494         BBDMAC_0_3, BBDMAC_4_7, BBDMAC_8_10, BBDMAC_11_14,
 495         BBDMAC_15_18, BBDMAC_19_22, BBDMAC_23_26, BBDMAC_27,
 496         BBDMAC_28, BBDMAC_29, BBDMAC_30, BBDMAC_31,
 497
 498         /* interrupt groups */
 499         TMU, DMAC, I2S, SRC, GFX3D, SPI, SCIF, BBDMAC,
 500 };
 501
 502 static struct intc_vect vectors[] __initdata = {
 503         INTC_VECT(GPIO, 0x3e0),
 504         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
 505         INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
 506         INTC_VECT(TMU3, 0x480), INTC_VECT(TMU4, 0x4a0),
 507         INTC_VECT(TMU5, 0x4c0), INTC_VECT(TMU5_TICPI, 0x4e0),
 508         INTC_VECT(TMU6, 0x500), INTC_VECT(TMU7, 0x520),
 509         INTC_VECT(TMU8, 0x540),
 510         INTC_VECT(HAC, 0x580), INTC_VECT(IPI, 0x5c0),
 511         INTC_VECT(SPDIF, 0x5e0),
 512         INTC_VECT(HUDI, 0x600), INTC_VECT(I2C, 0x620),
 513         INTC_VECT(DMAC0_DMINT0, 0x640), INTC_VECT(DMAC0_DMINT1, 0x660),
 514         INTC_VECT(DMAC0_DMINT2, 0x680),
 515         INTC_VECT(I2S0, 0x6a0), INTC_VECT(I2S1, 0x6c0),
 516         INTC_VECT(I2S2, 0x6e0), INTC_VECT(I2S3, 0x700),
 517         INTC_VECT(SRC_RX, 0x720), INTC_VECT(SRC_TX, 0x740),
 518         INTC_VECT(SRC_SPDIF, 0x760),
 519         INTC_VECT(DU, 0x780), INTC_VECT(VIDEO_IN, 0x7a0),
 520         INTC_VECT(REMOTE, 0x7c0), INTC_VECT(YUV, 0x7e0),
 521         INTC_VECT(USB, 0x840), INTC_VECT(ATAPI, 0x860),
 522         INTC_VECT(CAN, 0x880), INTC_VECT(GPS, 0x8a0),
 523         INTC_VECT(GFX2D, 0x8c0),
 524         INTC_VECT(GFX3D_MBX, 0x900), INTC_VECT(GFX3D_DMAC, 0x920),
 525         INTC_VECT(EXBUS_ATA, 0x940),
 526         INTC_VECT(SPI0, 0x960), INTC_VECT(SPI1, 0x980),
 527         INTC_VECT(SCIF089, 0x9a0), INTC_VECT(SCIF1234, 0x9c0),
 528         INTC_VECT(SCIF1234, 0x9e0), INTC_VECT(SCIF1234, 0xa00),
 529         INTC_VECT(SCIF1234, 0xa20), INTC_VECT(SCIF567, 0xa40),
 530         INTC_VECT(SCIF567, 0xa60), INTC_VECT(SCIF567, 0xa80),
 531         INTC_VECT(SCIF089, 0xaa0), INTC_VECT(SCIF089, 0xac0),
 532         INTC_VECT(ADC, 0xb20),
 533         INTC_VECT(BBDMAC_0_3, 0xba0), INTC_VECT(BBDMAC_0_3, 0xbc0),
 534         INTC_VECT(BBDMAC_0_3, 0xbe0), INTC_VECT(BBDMAC_0_3, 0xc00),
 535         INTC_VECT(BBDMAC_4_7, 0xc20), INTC_VECT(BBDMAC_4_7, 0xc40),
 536         INTC_VECT(BBDMAC_4_7, 0xc60), INTC_VECT(BBDMAC_4_7, 0xc80),
 537         INTC_VECT(BBDMAC_8_10, 0xca0), INTC_VECT(BBDMAC_8_10, 0xcc0),
 538         INTC_VECT(BBDMAC_8_10, 0xce0), INTC_VECT(BBDMAC_11_14, 0xd00),
 539         INTC_VECT(BBDMAC_11_14, 0xd20), INTC_VECT(BBDMAC_11_14, 0xd40),
 540         INTC_VECT(BBDMAC_11_14, 0xd60), INTC_VECT(BBDMAC_15_18, 0xd80),
 541         INTC_VECT(BBDMAC_15_18, 0xda0), INTC_VECT(BBDMAC_15_18, 0xdc0),
 542         INTC_VECT(BBDMAC_15_18, 0xde0), INTC_VECT(BBDMAC_19_22, 0xe00),
 543         INTC_VECT(BBDMAC_19_22, 0xe20), INTC_VECT(BBDMAC_19_22, 0xe40),
 544         INTC_VECT(BBDMAC_19_22, 0xe60), INTC_VECT(BBDMAC_23_26, 0xe80),
 545         INTC_VECT(BBDMAC_23_26, 0xea0), INTC_VECT(BBDMAC_23_26, 0xec0),
 546         INTC_VECT(BBDMAC_23_26, 0xee0), INTC_VECT(BBDMAC_27, 0xf00),
 547         INTC_VECT(BBDMAC_28, 0xf20), INTC_VECT(BBDMAC_29, 0xf40),
 548         INTC_VECT(BBDMAC_30, 0xf60), INTC_VECT(BBDMAC_31, 0xf80),
 549 };
 550
 551 static struct intc_group groups[] __initdata = {
 552         INTC_GROUP(TMU, TMU0, TMU1, TMU2, TMU2_TICPI, TMU3, TMU4, TMU5,
 553                    TMU5_TICPI, TMU6, TMU7, TMU8),
 554         INTC_GROUP(DMAC, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2),
 555         INTC_GROUP(I2S, I2S0, I2S1, I2S2, I2S3),
 556         INTC_GROUP(SRC, SRC_RX, SRC_TX, SRC_SPDIF),
 557         INTC_GROUP(GFX3D, GFX3D_MBX, GFX3D_DMAC),
 558         INTC_GROUP(SPI, SPI0, SPI1),
 559         INTC_GROUP(SCIF, SCIF089, SCIF1234, SCIF567),
 560         INTC_GROUP(BBDMAC,
 561                    BBDMAC_0_3, BBDMAC_4_7, BBDMAC_8_10, BBDMAC_11_14,
 562                    BBDMAC_15_18, BBDMAC_19_22, BBDMAC_23_26, BBDMAC_27,
 563                    BBDMAC_28, BBDMAC_29, BBDMAC_30, BBDMAC_31),
 564 };
 565
 566 static struct intc_mask_reg mask_registers[] __initdata = {
 567         { 0xffe00040, 0xffe00044, 32, /* INT2MSKR / INT2MSKCR */
 568           { 0, BBDMAC, ADC, SCIF, SPI, EXBUS_ATA, GFX3D, GFX2D,
 569             GPS, CAN, ATAPI, USB, YUV, REMOTE, VIDEO_IN, DU, SRC, I2S,
 570             DMAC, I2C, HUDI, SPDIF, IPI, HAC, TMU, GPIO } },
 571 };
 572
 573 static struct intc_prio_reg prio_registers[] __initdata = {
 574         { 0xffe00000, 0, 32, 8, /* INT2PRI0 */ { GPIO, TMU0, 0, HAC } },
 575         { 0xffe00004, 0, 32, 8, /* INT2PRI1 */ { IPI, SPDIF, HUDI, I2C } },
 576         { 0xffe00008, 0, 32, 8, /* INT2PRI2 */ { DMAC, I2S, SRC, DU } },
 577         { 0xffe0000c, 0, 32, 8, /* INT2PRI3 */ { VIDEO_IN, REMOTE, YUV, USB } },
 578         { 0xffe00010, 0, 32, 8, /* INT2PRI4 */ { ATAPI, CAN, GPS, GFX2D } },
 579         { 0xffe00014, 0, 32, 8, /* INT2PRI5 */ { 0, GFX3D, EXBUS_ATA, SPI } },
 580         { 0xffe00018, 0, 32, 8, /* INT2PRI6 */ { SCIF1234, SCIF567, SCIF089 } },
 581         { 0xffe0001c, 0, 32, 8, /* INT2PRI7 */ { ADC, 0, 0, BBDMAC_0_3 } },
 582         { 0xffe00020, 0, 32, 8, /* INT2PRI8 */
 583           { BBDMAC_4_7, BBDMAC_8_10, BBDMAC_11_14, BBDMAC_15_18 } },
 584         { 0xffe00024, 0, 32, 8, /* INT2PRI9 */
 585           { BBDMAC_19_22, BBDMAC_23_26, BBDMAC_27, BBDMAC_28 } },
 586         { 0xffe00028, 0, 32, 8, /* INT2PRI10 */
 587           { BBDMAC_29, BBDMAC_30, BBDMAC_31 } },
 588         { 0xffe0002c, 0, 32, 8, /* INT2PRI11 */
 589           { TMU1, TMU2, TMU2_TICPI, TMU3 } },
 590         { 0xffe00030, 0, 32, 8, /* INT2PRI12 */
 591           { TMU4, TMU5, TMU5_TICPI, TMU6 } },
 592         { 0xffe00034, 0, 32, 8, /* INT2PRI13 */
 593           { TMU7, TMU8 } },
 594 };
 595
 596 static DECLARE_INTC_DESC(intc_desc, "sh7770", vectors, groups,
 597                          mask_registers, prio_registers, NULL);
 598
 599 /* Support for external interrupt pins in IRQ mode */
 600 static struct intc_vect irq_vectors[] __initdata = {
 601         INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
 602         INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
 603         INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
 604 };
 605
 606 static struct intc_mask_reg irq_mask_registers[] __initdata = {
 607         { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
 608           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, } },
 609 };
 610
 611 static struct intc_prio_reg irq_prio_registers[] __initdata = {
 612         { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
 613                                                IRQ4, IRQ5, } },
 614 };
 615
 616 static struct intc_sense_reg irq_sense_registers[] __initdata = {
 617         { 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
 618                                             IRQ4, IRQ5, } },
 619 };
 620
 621 static DECLARE_INTC_DESC(intc_irq_desc, "sh7770-irq", irq_vectors,
 622                          NULL, irq_mask_registers, irq_prio_registers,
 623                          irq_sense_registers);
 624
 625 /* External interrupt pins in IRL mode */
 626 static struct intc_vect irl_vectors[] __initdata = {
 627         INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
 628         INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
 629         INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
 630         INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
 631         INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
 632         INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
 633         INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
 634         INTC_VECT(IRL_HHHL, 0x3c0),
 635 };
 636
 637 static struct intc_mask_reg irl3210_mask_registers[] __initdata = {
 638         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 639           { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 640             IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 641             IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 642             IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
 643 };
 644
 645 static struct intc_mask_reg irl7654_mask_registers[] __initdata = {
 646         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 647           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 648             IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 649             IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 650             IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 651             IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
 652 };
 653
 654 static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7780-irl7654", irl_vectors,
 655                          NULL, irl7654_mask_registers, NULL, NULL);
 656
 657 static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
 658                          NULL, irl3210_mask_registers, NULL, NULL);
 659
 660 #define INTC_ICR0       0xffd00000
 661 #define INTC_INTMSK0    0xffd00044
 662 #define INTC_INTMSK1    0xffd00048
 663 #define INTC_INTMSK2    0xffd40080
 664 #define INTC_INTMSKCLR1 0xffd00068
 665 #define INTC_INTMSKCLR2 0xffd40084
 666
 667 void __init plat_irq_setup(void)
 668 {
 669         /* disable IRQ7-0 */
 670         __raw_writel(0xff000000, INTC_INTMSK0);
 671
 672         /* disable IRL3-0 + IRL7-4 */
 673         __raw_writel(0xc0000000, INTC_INTMSK1);
 674         __raw_writel(0xfffefffe, INTC_INTMSK2);
 675
 676         /* select IRL mode for IRL3-0 + IRL7-4 */
 677         __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 678
 679         /* disable holding function, ie enable "SH-4 Mode" */
 680         __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
 681
 682         register_intc_controller(&intc_desc);
 683 }
 684
 685 void __init plat_irq_setup_pins(int mode)
 686 {
 687         switch (mode) {
 688         case IRQ_MODE_IRQ:
 689                 /* select IRQ mode for IRL3-0 + IRL7-4 */
 690                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
 691                 register_intc_controller(&intc_irq_desc);
 692                 break;
 693         case IRQ_MODE_IRL7654:
 694                 /* enable IRL7-4 but don't provide any masking */
 695                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 696                 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
 697                 break;
 698         case IRQ_MODE_IRL3210:
 699                 /* enable IRL0-3 but don't provide any masking */
 700                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 701                 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
 702                 break;
 703         case IRQ_MODE_IRL7654_MASK:
 704                 /* enable IRL7-4 and mask using cpu intc controller */
 705                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 706                 register_intc_controller(&intc_irl7654_desc);
 707                 break;
 708         case IRQ_MODE_IRL3210_MASK:
 709                 /* enable IRL0-3 and mask using cpu intc controller */
 710                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 711                 register_intc_controller(&intc_irl3210_desc);
 712                 break;
 713         default:
 714                 BUG();
 715         }
 716 }