arch/sh/kernel/cpu/sh4a/setup-sh7763.c

   1 /*
   2  * SH7763 Setup
   3  *
   4  *  Copyright (C) 2006  Paul Mundt
   5  *  Copyright (C) 2007  Yoshihiro Shimoda
   6  *  Copyright (C) 2008, 2009  Nobuhiro Iwamatsu
   7  *
   8  * This file is subject to the terms and conditions of the GNU General Public
   9  * License.  See the file "COPYING" in the main directory of this archive
  10  * for more details.
  11  */
  12 #include <linux/platform_device.h>
  13 #include <linux/init.h>
  14 #include <linux/serial.h>
  15 #include <linux/sh_timer.h>
  16 #include <linux/sh_intc.h>
  17 #include <linux/io.h>
  18 #include <linux/serial_sci.h>
  19 #include <linux/usb/ohci_pdriver.h>
  20
  21 static struct plat_sci_port scif0_platform_data = {
  22         .flags          = UPF_BOOT_AUTOCONF,
  23         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
  24         .scbrr_algo_id  = SCBRR_ALGO_2,
  25         .type           = PORT_SCIF,
  26         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
  27 };
  28
  29 static struct resource scif0_resources[] = {
  30         DEFINE_RES_MEM(0xffe00000, 0x100),
  31         DEFINE_RES_IRQ(evt2irq(0x700)),
  32 };
  33
  34 static struct platform_device scif0_device = {
  35         .name           = "sh-sci",
  36         .id             = 0,
  37         .resource       = scif0_resources,
  38         .num_resources  = ARRAY_SIZE(scif0_resources),
  39         .dev            = {
  40                 .platform_data  = &scif0_platform_data,
  41         },
  42 };
  43
  44 static struct plat_sci_port scif1_platform_data = {
  45         .flags          = UPF_BOOT_AUTOCONF,
  46         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
  47         .scbrr_algo_id  = SCBRR_ALGO_2,
  48         .type           = PORT_SCIF,
  49         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
  50 };
  51
  52 static struct resource scif1_resources[] = {
  53         DEFINE_RES_MEM(0xffe08000, 0x100),
  54         DEFINE_RES_IRQ(evt2irq(0xb80)),
  55 };
  56
  57 static struct platform_device scif1_device = {
  58         .name           = "sh-sci",
  59         .id             = 1,
  60         .resource       = scif1_resources,
  61         .num_resources  = ARRAY_SIZE(scif1_resources),
  62         .dev            = {
  63                 .platform_data  = &scif1_platform_data,
  64         },
  65 };
  66
  67 static struct plat_sci_port scif2_platform_data = {
  68         .flags          = UPF_BOOT_AUTOCONF,
  69         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
  70         .scbrr_algo_id  = SCBRR_ALGO_2,
  71         .type           = PORT_SCIF,
  72         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
  73 };
  74
  75 static struct resource scif2_resources[] = {
  76         DEFINE_RES_MEM(0xffe10000, 0x100),
  77         DEFINE_RES_IRQ(evt2irq(0xf00)),
  78 };
  79
  80 static struct platform_device scif2_device = {
  81         .name           = "sh-sci",
  82         .id             = 2,
  83         .resource       = scif2_resources,
  84         .num_resources  = ARRAY_SIZE(scif2_resources),
  85         .dev            = {
  86                 .platform_data  = &scif2_platform_data,
  87         },
  88 };
  89
  90 static struct resource rtc_resources[] = {
  91         [0] = {
  92                 .start  = 0xffe80000,
  93                 .end    = 0xffe80000 + 0x58 - 1,
  94                 .flags  = IORESOURCE_IO,
  95         },
  96         [1] = {
  97                 /* Shared Period/Carry/Alarm IRQ */
  98                 .start  = evt2irq(0x480),
  99                 .flags  = IORESOURCE_IRQ,
 100         },
 101 };
 102
 103 static struct platform_device rtc_device = {
 104         .name           = "sh-rtc",
 105         .id             = -1,
 106         .num_resources  = ARRAY_SIZE(rtc_resources),
 107         .resource       = rtc_resources,
 108 };
 109
 110 static struct resource usb_ohci_resources[] = {
 111         [0] = {
 112                 .start  = 0xffec8000,
 113                 .end    = 0xffec80ff,
 114                 .flags  = IORESOURCE_MEM,
 115         },
 116         [1] = {
 117                 .start  = evt2irq(0xc60),
 118                 .end    = evt2irq(0xc60),
 119                 .flags  = IORESOURCE_IRQ,
 120         },
 121 };
 122
 123 static u64 usb_ohci_dma_mask = 0xffffffffUL;
 124
 125 static struct usb_ohci_pdata usb_ohci_pdata;
 126
 127 static struct platform_device usb_ohci_device = {
 128         .name           = "ohci-platform",
 129         .id             = -1,
 130         .dev = {
 131                 .dma_mask               = &usb_ohci_dma_mask,
 132                 .coherent_dma_mask      = 0xffffffff,
 133                 .platform_data          = &usb_ohci_pdata,
 134         },
 135         .num_resources  = ARRAY_SIZE(usb_ohci_resources),
 136         .resource       = usb_ohci_resources,
 137 };
 138
 139 static struct resource usbf_resources[] = {
 140         [0] = {
 141                 .start  = 0xffec0000,
 142                 .end    = 0xffec00ff,
 143                 .flags  = IORESOURCE_MEM,
 144         },
 145         [1] = {
 146                 .start  = evt2irq(0xc80),
 147                 .end    = evt2irq(0xc80),
 148                 .flags  = IORESOURCE_IRQ,
 149         },
 150 };
 151
 152 static struct platform_device usbf_device = {
 153         .name           = "sh_udc",
 154         .id             = -1,
 155         .dev = {
 156                 .dma_mask               = NULL,
 157                 .coherent_dma_mask      = 0xffffffff,
 158         },
 159         .num_resources  = ARRAY_SIZE(usbf_resources),
 160         .resource       = usbf_resources,
 161 };
 162
 163 static struct sh_timer_config tmu0_platform_data = {
 164         .channel_offset = 0x04,
 165         .timer_bit = 0,
 166         .clockevent_rating = 200,
 167 };
 168
 169 static struct resource tmu0_resources[] = {
 170         [0] = {
 171                 .start  = 0xffd80008,
 172                 .end    = 0xffd80013,
 173                 .flags  = IORESOURCE_MEM,
 174         },
 175         [1] = {
 176                 .start  = evt2irq(0x580),
 177                 .flags  = IORESOURCE_IRQ,
 178         },
 179 };
 180
 181 static struct platform_device tmu0_device = {
 182         .name           = "sh_tmu",
 183         .id             = 0,
 184         .dev = {
 185                 .platform_data  = &tmu0_platform_data,
 186         },
 187         .resource       = tmu0_resources,
 188         .num_resources  = ARRAY_SIZE(tmu0_resources),
 189 };
 190
 191 static struct sh_timer_config tmu1_platform_data = {
 192         .channel_offset = 0x10,
 193         .timer_bit = 1,
 194         .clocksource_rating = 200,
 195 };
 196
 197 static struct resource tmu1_resources[] = {
 198         [0] = {
 199                 .start  = 0xffd80014,
 200                 .end    = 0xffd8001f,
 201                 .flags  = IORESOURCE_MEM,
 202         },
 203         [1] = {
 204                 .start  = evt2irq(0x5a0),
 205                 .flags  = IORESOURCE_IRQ,
 206         },
 207 };
 208
 209 static struct platform_device tmu1_device = {
 210         .name           = "sh_tmu",
 211         .id             = 1,
 212         .dev = {
 213                 .platform_data  = &tmu1_platform_data,
 214         },
 215         .resource       = tmu1_resources,
 216         .num_resources  = ARRAY_SIZE(tmu1_resources),
 217 };
 218
 219 static struct sh_timer_config tmu2_platform_data = {
 220         .channel_offset = 0x1c,
 221         .timer_bit = 2,
 222 };
 223
 224 static struct resource tmu2_resources[] = {
 225         [0] = {
 226                 .start  = 0xffd80020,
 227                 .end    = 0xffd8002f,
 228                 .flags  = IORESOURCE_MEM,
 229         },
 230         [1] = {
 231                 .start  = evt2irq(0x5c0),
 232                 .flags  = IORESOURCE_IRQ,
 233         },
 234 };
 235
 236 static struct platform_device tmu2_device = {
 237         .name           = "sh_tmu",
 238         .id             = 2,
 239         .dev = {
 240                 .platform_data  = &tmu2_platform_data,
 241         },
 242         .resource       = tmu2_resources,
 243         .num_resources  = ARRAY_SIZE(tmu2_resources),
 244 };
 245
 246 static struct sh_timer_config tmu3_platform_data = {
 247         .channel_offset = 0x04,
 248         .timer_bit = 0,
 249 };
 250
 251 static struct resource tmu3_resources[] = {
 252         [0] = {
 253                 .start  = 0xffd88008,
 254                 .end    = 0xffd88013,
 255                 .flags  = IORESOURCE_MEM,
 256         },
 257         [1] = {
 258                 .start  = evt2irq(0xe00),
 259                 .flags  = IORESOURCE_IRQ,
 260         },
 261 };
 262
 263 static struct platform_device tmu3_device = {
 264         .name           = "sh_tmu",
 265         .id             = 3,
 266         .dev = {
 267                 .platform_data  = &tmu3_platform_data,
 268         },
 269         .resource       = tmu3_resources,
 270         .num_resources  = ARRAY_SIZE(tmu3_resources),
 271 };
 272
 273 static struct sh_timer_config tmu4_platform_data = {
 274         .channel_offset = 0x10,
 275         .timer_bit = 1,
 276 };
 277
 278 static struct resource tmu4_resources[] = {
 279         [0] = {
 280                 .start  = 0xffd88014,
 281                 .end    = 0xffd8801f,
 282                 .flags  = IORESOURCE_MEM,
 283         },
 284         [1] = {
 285                 .start  = evt2irq(0xe20),
 286                 .flags  = IORESOURCE_IRQ,
 287         },
 288 };
 289
 290 static struct platform_device tmu4_device = {
 291         .name           = "sh_tmu",
 292         .id             = 4,
 293         .dev = {
 294                 .platform_data  = &tmu4_platform_data,
 295         },
 296         .resource       = tmu4_resources,
 297         .num_resources  = ARRAY_SIZE(tmu4_resources),
 298 };
 299
 300 static struct sh_timer_config tmu5_platform_data = {
 301         .channel_offset = 0x1c,
 302         .timer_bit = 2,
 303 };
 304
 305 static struct resource tmu5_resources[] = {
 306         [0] = {
 307                 .start  = 0xffd88020,
 308                 .end    = 0xffd8802b,
 309                 .flags  = IORESOURCE_MEM,
 310         },
 311         [1] = {
 312                 .start  = evt2irq(0xe40),
 313                 .flags  = IORESOURCE_IRQ,
 314         },
 315 };
 316
 317 static struct platform_device tmu5_device = {
 318         .name           = "sh_tmu",
 319         .id             = 5,
 320         .dev = {
 321                 .platform_data  = &tmu5_platform_data,
 322         },
 323         .resource       = tmu5_resources,
 324         .num_resources  = ARRAY_SIZE(tmu5_resources),
 325 };
 326
 327 static struct platform_device *sh7763_devices[] __initdata = {
 328         &scif0_device,
 329         &scif1_device,
 330         &scif2_device,
 331         &tmu0_device,
 332         &tmu1_device,
 333         &tmu2_device,
 334         &tmu3_device,
 335         &tmu4_device,
 336         &tmu5_device,
 337         &rtc_device,
 338         &usb_ohci_device,
 339         &usbf_device,
 340 };
 341
 342 static int __init sh7763_devices_setup(void)
 343 {
 344         return platform_add_devices(sh7763_devices,
 345                                     ARRAY_SIZE(sh7763_devices));
 346 }
 347 arch_initcall(sh7763_devices_setup);
 348
 349 static struct platform_device *sh7763_early_devices[] __initdata = {
 350         &scif0_device,
 351         &scif1_device,
 352         &scif2_device,
 353         &tmu0_device,
 354         &tmu1_device,
 355         &tmu2_device,
 356         &tmu3_device,
 357         &tmu4_device,
 358         &tmu5_device,
 359 };
 360
 361 void __init plat_early_device_setup(void)
 362 {
 363         early_platform_add_devices(sh7763_early_devices,
 364                                    ARRAY_SIZE(sh7763_early_devices));
 365 }
 366
 367 enum {
 368         UNUSED = 0,
 369
 370         /* interrupt sources */
 371
 372         IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 373         IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 374         IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 375         IRL_HHLL, IRL_HHLH, IRL_HHHL,
 376
 377         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 378         RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
 379         HUDI, LCDC, DMAC, SCIF0, IIC0, IIC1, CMT, GETHER, HAC,
 380         PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
 381         STIF0, STIF1, SCIF1, SIOF0, SIOF1, SIOF2,
 382         USBH, USBF, TPU, PCC, MMCIF, SIM,
 383         TMU3, TMU4, TMU5, ADC, SSI0, SSI1, SSI2, SSI3,
 384         SCIF2, GPIO,
 385
 386         /* interrupt groups */
 387
 388         TMU012, TMU345,
 389 };
 390
 391 static struct intc_vect vectors[] __initdata = {
 392         INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
 393         INTC_VECT(RTC, 0x4c0),
 394         INTC_VECT(WDT, 0x560), INTC_VECT(TMU0, 0x580),
 395         INTC_VECT(TMU1, 0x5a0), INTC_VECT(TMU2, 0x5c0),
 396         INTC_VECT(TMU2_TICPI, 0x5e0), INTC_VECT(HUDI, 0x600),
 397         INTC_VECT(LCDC, 0x620),
 398         INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
 399         INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
 400         INTC_VECT(DMAC, 0x6c0),
 401         INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
 402         INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
 403         INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
 404         INTC_VECT(IIC0, 0x8A0), INTC_VECT(IIC1, 0x8C0),
 405         INTC_VECT(CMT, 0x900), INTC_VECT(GETHER, 0x920),
 406         INTC_VECT(GETHER, 0x940), INTC_VECT(GETHER, 0x960),
 407         INTC_VECT(HAC, 0x980),
 408         INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
 409         INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
 410         INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
 411         INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
 412         INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
 413         INTC_VECT(STIF0, 0xb40), INTC_VECT(STIF1, 0xb60),
 414         INTC_VECT(SCIF1, 0xb80), INTC_VECT(SCIF1, 0xba0),
 415         INTC_VECT(SCIF1, 0xbc0), INTC_VECT(SCIF1, 0xbe0),
 416         INTC_VECT(SIOF0, 0xc00), INTC_VECT(SIOF1, 0xc20),
 417         INTC_VECT(USBH, 0xc60), INTC_VECT(USBF, 0xc80),
 418         INTC_VECT(USBF, 0xca0),
 419         INTC_VECT(TPU, 0xcc0), INTC_VECT(PCC, 0xce0),
 420         INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
 421         INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
 422         INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0),
 423         INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0),
 424         INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
 425         INTC_VECT(TMU5, 0xe40), INTC_VECT(ADC, 0xe60),
 426         INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
 427         INTC_VECT(SSI2, 0xec0), INTC_VECT(SSI3, 0xee0),
 428         INTC_VECT(SCIF2, 0xf00), INTC_VECT(SCIF2, 0xf20),
 429         INTC_VECT(SCIF2, 0xf40), INTC_VECT(SCIF2, 0xf60),
 430         INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
 431         INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
 432 };
 433
 434 static struct intc_group groups[] __initdata = {
 435         INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
 436         INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
 437 };
 438
 439 static struct intc_mask_reg mask_registers[] __initdata = {
 440         { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
 441           { 0, 0, 0, 0, 0, 0, GPIO, 0,
 442             SSI0, MMCIF, 0, SIOF0, PCIC5, PCIINTD, PCIINTC, PCIINTB,
 443             PCIINTA, PCISERR, HAC, CMT, 0, 0, 0, DMAC,
 444             HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
 445         { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */
 446           { 0, 0, 0, 0, 0, 0, SCIF2, USBF,
 447             0, 0, STIF1, STIF0, 0, 0, USBH, GETHER,
 448             PCC, 0, 0, ADC, TPU, SIM, SIOF2, SIOF1,
 449             LCDC, 0, IIC1, IIC0, SSI3, SSI2, SSI1, 0 } },
 450 };
 451
 452 static struct intc_prio_reg prio_registers[] __initdata = {
 453         { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
 454                                                  TMU2, TMU2_TICPI } },
 455         { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } },
 456         { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } },
 457         { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { HUDI, DMAC, ADC } },
 458         { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { CMT, HAC,
 459                                                  PCISERR, PCIINTA } },
 460         { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC,
 461                                                  PCIINTD, PCIC5 } },
 462         { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { SIOF0, USBF, MMCIF, SSI0 } },
 463         { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SCIF2, GPIO } },
 464         { 0xffd400a0, 0, 32, 8, /* INT2PRI8 */ { SSI3, SSI2, SSI1, 0 } },
 465         { 0xffd400a4, 0, 32, 8, /* INT2PRI9 */ { LCDC, 0, IIC1, IIC0 } },
 466         { 0xffd400a8, 0, 32, 8, /* INT2PRI10 */ { TPU, SIM, SIOF2, SIOF1 } },
 467         { 0xffd400ac, 0, 32, 8, /* INT2PRI11 */ { PCC } },
 468         { 0xffd400b0, 0, 32, 8, /* INT2PRI12 */ { 0, 0, USBH, GETHER } },
 469         { 0xffd400b4, 0, 32, 8, /* INT2PRI13 */ { 0, 0, STIF1, STIF0 } },
 470 };
 471
 472 static DECLARE_INTC_DESC(intc_desc, "sh7763", vectors, groups,
 473                          mask_registers, prio_registers, NULL);
 474
 475 /* Support for external interrupt pins in IRQ mode */
 476 static struct intc_vect irq_vectors[] __initdata = {
 477         INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
 478         INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
 479         INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
 480         INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
 481 };
 482
 483 static struct intc_mask_reg irq_mask_registers[] __initdata = {
 484         { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
 485           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 486 };
 487
 488 static struct intc_prio_reg irq_prio_registers[] __initdata = {
 489         { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
 490                                                IRQ4, IRQ5, IRQ6, IRQ7 } },
 491 };
 492
 493 static struct intc_sense_reg irq_sense_registers[] __initdata = {
 494         { 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
 495                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
 496 };
 497
 498 static struct intc_mask_reg irq_ack_registers[] __initdata = {
 499         { 0xffd00024, 0, 32, /* INTREQ */
 500           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 501 };
 502
 503 static DECLARE_INTC_DESC_ACK(intc_irq_desc, "sh7763-irq", irq_vectors,
 504                              NULL, irq_mask_registers, irq_prio_registers,
 505                              irq_sense_registers, irq_ack_registers);
 506
 507
 508 /* External interrupt pins in IRL mode */
 509 static struct intc_vect irl_vectors[] __initdata = {
 510         INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
 511         INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
 512         INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
 513         INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
 514         INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
 515         INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
 516         INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
 517         INTC_VECT(IRL_HHHL, 0x3c0),
 518 };
 519
 520 static struct intc_mask_reg irl3210_mask_registers[] __initdata = {
 521         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 522           { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 523             IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 524             IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 525             IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
 526 };
 527
 528 static struct intc_mask_reg irl7654_mask_registers[] __initdata = {
 529         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 530           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 531             IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 532             IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 533             IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 534             IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
 535 };
 536
 537 static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7763-irl7654", irl_vectors,
 538                         NULL, irl7654_mask_registers, NULL, NULL);
 539
 540 static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7763-irl3210", irl_vectors,
 541                         NULL, irl3210_mask_registers, NULL, NULL);
 542
 543 #define INTC_ICR0       0xffd00000
 544 #define INTC_INTMSK0    0xffd00044
 545 #define INTC_INTMSK1    0xffd00048
 546 #define INTC_INTMSK2    0xffd40080
 547 #define INTC_INTMSKCLR1 0xffd00068
 548 #define INTC_INTMSKCLR2 0xffd40084
 549
 550 void __init plat_irq_setup(void)
 551 {
 552         /* disable IRQ7-0 */
 553         __raw_writel(0xff000000, INTC_INTMSK0);
 554
 555         /* disable IRL3-0 + IRL7-4 */
 556         __raw_writel(0xc0000000, INTC_INTMSK1);
 557         __raw_writel(0xfffefffe, INTC_INTMSK2);
 558
 559         register_intc_controller(&intc_desc);
 560 }
 561
 562 void __init plat_irq_setup_pins(int mode)
 563 {
 564         switch (mode) {
 565         case IRQ_MODE_IRQ:
 566                 /* select IRQ mode for IRL3-0 + IRL7-4 */
 567                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
 568                 register_intc_controller(&intc_irq_desc);
 569                 break;
 570         case IRQ_MODE_IRL7654:
 571                 /* enable IRL7-4 but don't provide any masking */
 572                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 573                 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
 574                 break;
 575         case IRQ_MODE_IRL3210:
 576                 /* enable IRL0-3 but don't provide any masking */
 577                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 578                 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
 579                 break;
 580         case IRQ_MODE_IRL7654_MASK:
 581                 /* enable IRL7-4 and mask using cpu intc controller */
 582                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 583                 register_intc_controller(&intc_irl7654_desc);
 584                 break;
 585         case IRQ_MODE_IRL3210_MASK:
 586                 /* enable IRL0-3 and mask using cpu intc controller */
 587                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 588                 register_intc_controller(&intc_irl3210_desc);
 589                 break;
 590         default:
 591                 BUG();
 592         }
 593 }