4 * Copyright (C) 2006 Paul Mundt
5 * Copyright (C) 2007 Yoshihiro Shimoda
6 * Copyright (C) 2008, 2009 Nobuhiro Iwamatsu
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
12 #include <linux/platform_device.h>
13 #include <linux/init.h>
14 #include <linux/serial.h>
15 #include <linux/sh_timer.h>
16 #include <linux/sh_intc.h>
18 #include <linux/serial_sci.h>
19 #include <linux/usb/ohci_pdriver.h>
21 static struct plat_sci_port scif0_platform_data = {
22 .flags = UPF_BOOT_AUTOCONF,
23 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
24 .scbrr_algo_id = SCBRR_ALGO_2,
26 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
29 static struct resource scif0_resources[] = {
30 DEFINE_RES_MEM(0xffe00000, 0x100),
31 DEFINE_RES_IRQ(evt2irq(0x700)),
34 static struct platform_device scif0_device = {
37 .resource = scif0_resources,
38 .num_resources = ARRAY_SIZE(scif0_resources),
40 .platform_data = &scif0_platform_data,
44 static struct plat_sci_port scif1_platform_data = {
45 .flags = UPF_BOOT_AUTOCONF,
46 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
47 .scbrr_algo_id = SCBRR_ALGO_2,
49 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
52 static struct resource scif1_resources[] = {
53 DEFINE_RES_MEM(0xffe08000, 0x100),
54 DEFINE_RES_IRQ(evt2irq(0xb80)),
57 static struct platform_device scif1_device = {
60 .resource = scif1_resources,
61 .num_resources = ARRAY_SIZE(scif1_resources),
63 .platform_data = &scif1_platform_data,
67 static struct plat_sci_port scif2_platform_data = {
68 .flags = UPF_BOOT_AUTOCONF,
69 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
70 .scbrr_algo_id = SCBRR_ALGO_2,
72 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
75 static struct resource scif2_resources[] = {
76 DEFINE_RES_MEM(0xffe10000, 0x100),
77 DEFINE_RES_IRQ(evt2irq(0xf00)),
80 static struct platform_device scif2_device = {
83 .resource = scif2_resources,
84 .num_resources = ARRAY_SIZE(scif2_resources),
86 .platform_data = &scif2_platform_data,
90 static struct resource rtc_resources[] = {
93 .end = 0xffe80000 + 0x58 - 1,
94 .flags = IORESOURCE_IO,
97 /* Shared Period/Carry/Alarm IRQ */
98 .start = evt2irq(0x480),
99 .flags = IORESOURCE_IRQ,
103 static struct platform_device rtc_device = {
106 .num_resources = ARRAY_SIZE(rtc_resources),
107 .resource = rtc_resources,
110 static struct resource usb_ohci_resources[] = {
114 .flags = IORESOURCE_MEM,
117 .start = evt2irq(0xc60),
118 .end = evt2irq(0xc60),
119 .flags = IORESOURCE_IRQ,
123 static u64 usb_ohci_dma_mask = 0xffffffffUL;
125 static struct usb_ohci_pdata usb_ohci_pdata;
127 static struct platform_device usb_ohci_device = {
128 .name = "ohci-platform",
131 .dma_mask = &usb_ohci_dma_mask,
132 .coherent_dma_mask = 0xffffffff,
133 .platform_data = &usb_ohci_pdata,
135 .num_resources = ARRAY_SIZE(usb_ohci_resources),
136 .resource = usb_ohci_resources,
139 static struct resource usbf_resources[] = {
143 .flags = IORESOURCE_MEM,
146 .start = evt2irq(0xc80),
147 .end = evt2irq(0xc80),
148 .flags = IORESOURCE_IRQ,
152 static struct platform_device usbf_device = {
157 .coherent_dma_mask = 0xffffffff,
159 .num_resources = ARRAY_SIZE(usbf_resources),
160 .resource = usbf_resources,
163 static struct sh_timer_config tmu0_platform_data = {
164 .channel_offset = 0x04,
166 .clockevent_rating = 200,
169 static struct resource tmu0_resources[] = {
173 .flags = IORESOURCE_MEM,
176 .start = evt2irq(0x580),
177 .flags = IORESOURCE_IRQ,
181 static struct platform_device tmu0_device = {
185 .platform_data = &tmu0_platform_data,
187 .resource = tmu0_resources,
188 .num_resources = ARRAY_SIZE(tmu0_resources),
191 static struct sh_timer_config tmu1_platform_data = {
192 .channel_offset = 0x10,
194 .clocksource_rating = 200,
197 static struct resource tmu1_resources[] = {
201 .flags = IORESOURCE_MEM,
204 .start = evt2irq(0x5a0),
205 .flags = IORESOURCE_IRQ,
209 static struct platform_device tmu1_device = {
213 .platform_data = &tmu1_platform_data,
215 .resource = tmu1_resources,
216 .num_resources = ARRAY_SIZE(tmu1_resources),
219 static struct sh_timer_config tmu2_platform_data = {
220 .channel_offset = 0x1c,
224 static struct resource tmu2_resources[] = {
228 .flags = IORESOURCE_MEM,
231 .start = evt2irq(0x5c0),
232 .flags = IORESOURCE_IRQ,
236 static struct platform_device tmu2_device = {
240 .platform_data = &tmu2_platform_data,
242 .resource = tmu2_resources,
243 .num_resources = ARRAY_SIZE(tmu2_resources),
246 static struct sh_timer_config tmu3_platform_data = {
247 .channel_offset = 0x04,
251 static struct resource tmu3_resources[] = {
255 .flags = IORESOURCE_MEM,
258 .start = evt2irq(0xe00),
259 .flags = IORESOURCE_IRQ,
263 static struct platform_device tmu3_device = {
267 .platform_data = &tmu3_platform_data,
269 .resource = tmu3_resources,
270 .num_resources = ARRAY_SIZE(tmu3_resources),
273 static struct sh_timer_config tmu4_platform_data = {
274 .channel_offset = 0x10,
278 static struct resource tmu4_resources[] = {
282 .flags = IORESOURCE_MEM,
285 .start = evt2irq(0xe20),
286 .flags = IORESOURCE_IRQ,
290 static struct platform_device tmu4_device = {
294 .platform_data = &tmu4_platform_data,
296 .resource = tmu4_resources,
297 .num_resources = ARRAY_SIZE(tmu4_resources),
300 static struct sh_timer_config tmu5_platform_data = {
301 .channel_offset = 0x1c,
305 static struct resource tmu5_resources[] = {
309 .flags = IORESOURCE_MEM,
312 .start = evt2irq(0xe40),
313 .flags = IORESOURCE_IRQ,
317 static struct platform_device tmu5_device = {
321 .platform_data = &tmu5_platform_data,
323 .resource = tmu5_resources,
324 .num_resources = ARRAY_SIZE(tmu5_resources),
327 static struct platform_device *sh7763_devices[] __initdata = {
342 static int __init sh7763_devices_setup(void)
344 return platform_add_devices(sh7763_devices,
345 ARRAY_SIZE(sh7763_devices));
347 arch_initcall(sh7763_devices_setup);
349 static struct platform_device *sh7763_early_devices[] __initdata = {
361 void __init plat_early_device_setup(void)
363 early_platform_add_devices(sh7763_early_devices,
364 ARRAY_SIZE(sh7763_early_devices));
370 /* interrupt sources */
372 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
373 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
374 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
375 IRL_HHLL, IRL_HHLH, IRL_HHHL,
377 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
378 RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
379 HUDI, LCDC, DMAC, SCIF0, IIC0, IIC1, CMT, GETHER, HAC,
380 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
381 STIF0, STIF1, SCIF1, SIOF0, SIOF1, SIOF2,
382 USBH, USBF, TPU, PCC, MMCIF, SIM,
383 TMU3, TMU4, TMU5, ADC, SSI0, SSI1, SSI2, SSI3,
386 /* interrupt groups */
391 static struct intc_vect vectors[] __initdata = {
392 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
393 INTC_VECT(RTC, 0x4c0),
394 INTC_VECT(WDT, 0x560), INTC_VECT(TMU0, 0x580),
395 INTC_VECT(TMU1, 0x5a0), INTC_VECT(TMU2, 0x5c0),
396 INTC_VECT(TMU2_TICPI, 0x5e0), INTC_VECT(HUDI, 0x600),
397 INTC_VECT(LCDC, 0x620),
398 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
399 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
400 INTC_VECT(DMAC, 0x6c0),
401 INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
402 INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
403 INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
404 INTC_VECT(IIC0, 0x8A0), INTC_VECT(IIC1, 0x8C0),
405 INTC_VECT(CMT, 0x900), INTC_VECT(GETHER, 0x920),
406 INTC_VECT(GETHER, 0x940), INTC_VECT(GETHER, 0x960),
407 INTC_VECT(HAC, 0x980),
408 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
409 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
410 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
411 INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
412 INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
413 INTC_VECT(STIF0, 0xb40), INTC_VECT(STIF1, 0xb60),
414 INTC_VECT(SCIF1, 0xb80), INTC_VECT(SCIF1, 0xba0),
415 INTC_VECT(SCIF1, 0xbc0), INTC_VECT(SCIF1, 0xbe0),
416 INTC_VECT(SIOF0, 0xc00), INTC_VECT(SIOF1, 0xc20),
417 INTC_VECT(USBH, 0xc60), INTC_VECT(USBF, 0xc80),
418 INTC_VECT(USBF, 0xca0),
419 INTC_VECT(TPU, 0xcc0), INTC_VECT(PCC, 0xce0),
420 INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
421 INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
422 INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0),
423 INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0),
424 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
425 INTC_VECT(TMU5, 0xe40), INTC_VECT(ADC, 0xe60),
426 INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
427 INTC_VECT(SSI2, 0xec0), INTC_VECT(SSI3, 0xee0),
428 INTC_VECT(SCIF2, 0xf00), INTC_VECT(SCIF2, 0xf20),
429 INTC_VECT(SCIF2, 0xf40), INTC_VECT(SCIF2, 0xf60),
430 INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
431 INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
434 static struct intc_group groups[] __initdata = {
435 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
436 INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
439 static struct intc_mask_reg mask_registers[] __initdata = {
440 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
441 { 0, 0, 0, 0, 0, 0, GPIO, 0,
442 SSI0, MMCIF, 0, SIOF0, PCIC5, PCIINTD, PCIINTC, PCIINTB,
443 PCIINTA, PCISERR, HAC, CMT, 0, 0, 0, DMAC,
444 HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
445 { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */
446 { 0, 0, 0, 0, 0, 0, SCIF2, USBF,
447 0, 0, STIF1, STIF0, 0, 0, USBH, GETHER,
448 PCC, 0, 0, ADC, TPU, SIM, SIOF2, SIOF1,
449 LCDC, 0, IIC1, IIC0, SSI3, SSI2, SSI1, 0 } },
452 static struct intc_prio_reg prio_registers[] __initdata = {
453 { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
454 TMU2, TMU2_TICPI } },
455 { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } },
456 { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } },
457 { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { HUDI, DMAC, ADC } },
458 { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { CMT, HAC,
459 PCISERR, PCIINTA } },
460 { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC,
462 { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { SIOF0, USBF, MMCIF, SSI0 } },
463 { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SCIF2, GPIO } },
464 { 0xffd400a0, 0, 32, 8, /* INT2PRI8 */ { SSI3, SSI2, SSI1, 0 } },
465 { 0xffd400a4, 0, 32, 8, /* INT2PRI9 */ { LCDC, 0, IIC1, IIC0 } },
466 { 0xffd400a8, 0, 32, 8, /* INT2PRI10 */ { TPU, SIM, SIOF2, SIOF1 } },
467 { 0xffd400ac, 0, 32, 8, /* INT2PRI11 */ { PCC } },
468 { 0xffd400b0, 0, 32, 8, /* INT2PRI12 */ { 0, 0, USBH, GETHER } },
469 { 0xffd400b4, 0, 32, 8, /* INT2PRI13 */ { 0, 0, STIF1, STIF0 } },
472 static DECLARE_INTC_DESC(intc_desc, "sh7763", vectors, groups,
473 mask_registers, prio_registers, NULL);
475 /* Support for external interrupt pins in IRQ mode */
476 static struct intc_vect irq_vectors[] __initdata = {
477 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
478 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
479 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
480 INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
483 static struct intc_mask_reg irq_mask_registers[] __initdata = {
484 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
485 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
488 static struct intc_prio_reg irq_prio_registers[] __initdata = {
489 { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
490 IRQ4, IRQ5, IRQ6, IRQ7 } },
493 static struct intc_sense_reg irq_sense_registers[] __initdata = {
494 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
495 IRQ4, IRQ5, IRQ6, IRQ7 } },
498 static struct intc_mask_reg irq_ack_registers[] __initdata = {
499 { 0xffd00024, 0, 32, /* INTREQ */
500 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
503 static DECLARE_INTC_DESC_ACK(intc_irq_desc, "sh7763-irq", irq_vectors,
504 NULL, irq_mask_registers, irq_prio_registers,
505 irq_sense_registers, irq_ack_registers);
508 /* External interrupt pins in IRL mode */
509 static struct intc_vect irl_vectors[] __initdata = {
510 INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
511 INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
512 INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
513 INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
514 INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
515 INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
516 INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
517 INTC_VECT(IRL_HHHL, 0x3c0),
520 static struct intc_mask_reg irl3210_mask_registers[] __initdata = {
521 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
522 { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
523 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
524 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
525 IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
528 static struct intc_mask_reg irl7654_mask_registers[] __initdata = {
529 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
530 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
531 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
532 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
533 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
534 IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
537 static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7763-irl7654", irl_vectors,
538 NULL, irl7654_mask_registers, NULL, NULL);
540 static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7763-irl3210", irl_vectors,
541 NULL, irl3210_mask_registers, NULL, NULL);
543 #define INTC_ICR0 0xffd00000
544 #define INTC_INTMSK0 0xffd00044
545 #define INTC_INTMSK1 0xffd00048
546 #define INTC_INTMSK2 0xffd40080
547 #define INTC_INTMSKCLR1 0xffd00068
548 #define INTC_INTMSKCLR2 0xffd40084
550 void __init plat_irq_setup(void)
553 __raw_writel(0xff000000, INTC_INTMSK0);
555 /* disable IRL3-0 + IRL7-4 */
556 __raw_writel(0xc0000000, INTC_INTMSK1);
557 __raw_writel(0xfffefffe, INTC_INTMSK2);
559 register_intc_controller(&intc_desc);
562 void __init plat_irq_setup_pins(int mode)
566 /* select IRQ mode for IRL3-0 + IRL7-4 */
567 __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
568 register_intc_controller(&intc_irq_desc);
570 case IRQ_MODE_IRL7654:
571 /* enable IRL7-4 but don't provide any masking */
572 __raw_writel(0x40000000, INTC_INTMSKCLR1);
573 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
575 case IRQ_MODE_IRL3210:
576 /* enable IRL0-3 but don't provide any masking */
577 __raw_writel(0x80000000, INTC_INTMSKCLR1);
578 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
580 case IRQ_MODE_IRL7654_MASK:
581 /* enable IRL7-4 and mask using cpu intc controller */
582 __raw_writel(0x40000000, INTC_INTMSKCLR1);
583 register_intc_controller(&intc_irl7654_desc);
585 case IRQ_MODE_IRL3210_MASK:
586 /* enable IRL0-3 and mask using cpu intc controller */
587 __raw_writel(0x80000000, INTC_INTMSKCLR1);
588 register_intc_controller(&intc_irl3210_desc);