arch/sh/kernel/cpu/sh4a/setup-sh7763.c

   1 /*
   2  * SH7763 Setup
   3  *
   4  *  Copyright (C) 2006  Paul Mundt
   5  *  Copyright (C) 2007  Yoshihiro Shimoda
   6  *  Copyright (C) 2008, 2009  Nobuhiro Iwamatsu
   7  *
   8  * This file is subject to the terms and conditions of the GNU General Public
   9  * License.  See the file "COPYING" in the main directory of this archive
  10  * for more details.
  11  */
  12 #include <linux/platform_device.h>
  13 #include <linux/init.h>
  14 #include <linux/serial.h>
  15 #include <linux/sh_timer.h>
  16 #include <linux/sh_intc.h>
  17 #include <linux/io.h>
  18 #include <linux/serial_sci.h>
  19 #include <linux/usb/ohci_pdriver.h>
  20
  21 static struct plat_sci_port scif0_platform_data = {
  22         .mapbase        = 0xffe00000,
  23         .flags          = UPF_BOOT_AUTOCONF,
  24         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
  25         .scbrr_algo_id  = SCBRR_ALGO_2,
  26         .type           = PORT_SCIF,
  27         .irqs           = SCIx_IRQ_MUXED(evt2irq(0x700)),
  28         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
  29 };
  30
  31 static struct platform_device scif0_device = {
  32         .name           = "sh-sci",
  33         .id             = 0,
  34         .dev            = {
  35                 .platform_data  = &scif0_platform_data,
  36         },
  37 };
  38
  39 static struct plat_sci_port scif1_platform_data = {
  40         .mapbase        = 0xffe08000,
  41         .flags          = UPF_BOOT_AUTOCONF,
  42         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
  43         .scbrr_algo_id  = SCBRR_ALGO_2,
  44         .type           = PORT_SCIF,
  45         .irqs           = SCIx_IRQ_MUXED(evt2irq(0xb80)),
  46         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
  47 };
  48
  49 static struct platform_device scif1_device = {
  50         .name           = "sh-sci",
  51         .id             = 1,
  52         .dev            = {
  53                 .platform_data  = &scif1_platform_data,
  54         },
  55 };
  56
  57 static struct plat_sci_port scif2_platform_data = {
  58         .mapbase        = 0xffe10000,
  59         .flags          = UPF_BOOT_AUTOCONF,
  60         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
  61         .scbrr_algo_id  = SCBRR_ALGO_2,
  62         .type           = PORT_SCIF,
  63         .irqs           = SCIx_IRQ_MUXED(evt2irq(0xf00)),
  64         .regtype        = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
  65 };
  66
  67 static struct platform_device scif2_device = {
  68         .name           = "sh-sci",
  69         .id             = 2,
  70         .dev            = {
  71                 .platform_data  = &scif2_platform_data,
  72         },
  73 };
  74
  75 static struct resource rtc_resources[] = {
  76         [0] = {
  77                 .start  = 0xffe80000,
  78                 .end    = 0xffe80000 + 0x58 - 1,
  79                 .flags  = IORESOURCE_IO,
  80         },
  81         [1] = {
  82                 /* Shared Period/Carry/Alarm IRQ */
  83                 .start  = evt2irq(0x480),
  84                 .flags  = IORESOURCE_IRQ,
  85         },
  86 };
  87
  88 static struct platform_device rtc_device = {
  89         .name           = "sh-rtc",
  90         .id             = -1,
  91         .num_resources  = ARRAY_SIZE(rtc_resources),
  92         .resource       = rtc_resources,
  93 };
  94
  95 static struct resource usb_ohci_resources[] = {
  96         [0] = {
  97                 .start  = 0xffec8000,
  98                 .end    = 0xffec80ff,
  99                 .flags  = IORESOURCE_MEM,
 100         },
 101         [1] = {
 102                 .start  = evt2irq(0xc60),
 103                 .end    = evt2irq(0xc60),
 104                 .flags  = IORESOURCE_IRQ,
 105         },
 106 };
 107
 108 static u64 usb_ohci_dma_mask = 0xffffffffUL;
 109
 110 static struct usb_ohci_pdata usb_ohci_pdata;
 111
 112 static struct platform_device usb_ohci_device = {
 113         .name           = "ohci-platform",
 114         .id             = -1,
 115         .dev = {
 116                 .dma_mask               = &usb_ohci_dma_mask,
 117                 .coherent_dma_mask      = 0xffffffff,
 118                 .platform_data          = &usb_ohci_pdata,
 119         },
 120         .num_resources  = ARRAY_SIZE(usb_ohci_resources),
 121         .resource       = usb_ohci_resources,
 122 };
 123
 124 static struct resource usbf_resources[] = {
 125         [0] = {
 126                 .start  = 0xffec0000,
 127                 .end    = 0xffec00ff,
 128                 .flags  = IORESOURCE_MEM,
 129         },
 130         [1] = {
 131                 .start  = evt2irq(0xc80),
 132                 .end    = evt2irq(0xc80),
 133                 .flags  = IORESOURCE_IRQ,
 134         },
 135 };
 136
 137 static struct platform_device usbf_device = {
 138         .name           = "sh_udc",
 139         .id             = -1,
 140         .dev = {
 141                 .dma_mask               = NULL,
 142                 .coherent_dma_mask      = 0xffffffff,
 143         },
 144         .num_resources  = ARRAY_SIZE(usbf_resources),
 145         .resource       = usbf_resources,
 146 };
 147
 148 static struct sh_timer_config tmu0_platform_data = {
 149         .channel_offset = 0x04,
 150         .timer_bit = 0,
 151         .clockevent_rating = 200,
 152 };
 153
 154 static struct resource tmu0_resources[] = {
 155         [0] = {
 156                 .start  = 0xffd80008,
 157                 .end    = 0xffd80013,
 158                 .flags  = IORESOURCE_MEM,
 159         },
 160         [1] = {
 161                 .start  = evt2irq(0x580),
 162                 .flags  = IORESOURCE_IRQ,
 163         },
 164 };
 165
 166 static struct platform_device tmu0_device = {
 167         .name           = "sh_tmu",
 168         .id             = 0,
 169         .dev = {
 170                 .platform_data  = &tmu0_platform_data,
 171         },
 172         .resource       = tmu0_resources,
 173         .num_resources  = ARRAY_SIZE(tmu0_resources),
 174 };
 175
 176 static struct sh_timer_config tmu1_platform_data = {
 177         .channel_offset = 0x10,
 178         .timer_bit = 1,
 179         .clocksource_rating = 200,
 180 };
 181
 182 static struct resource tmu1_resources[] = {
 183         [0] = {
 184                 .start  = 0xffd80014,
 185                 .end    = 0xffd8001f,
 186                 .flags  = IORESOURCE_MEM,
 187         },
 188         [1] = {
 189                 .start  = evt2irq(0x5a0),
 190                 .flags  = IORESOURCE_IRQ,
 191         },
 192 };
 193
 194 static struct platform_device tmu1_device = {
 195         .name           = "sh_tmu",
 196         .id             = 1,
 197         .dev = {
 198                 .platform_data  = &tmu1_platform_data,
 199         },
 200         .resource       = tmu1_resources,
 201         .num_resources  = ARRAY_SIZE(tmu1_resources),
 202 };
 203
 204 static struct sh_timer_config tmu2_platform_data = {
 205         .channel_offset = 0x1c,
 206         .timer_bit = 2,
 207 };
 208
 209 static struct resource tmu2_resources[] = {
 210         [0] = {
 211                 .start  = 0xffd80020,
 212                 .end    = 0xffd8002f,
 213                 .flags  = IORESOURCE_MEM,
 214         },
 215         [1] = {
 216                 .start  = evt2irq(0x5c0),
 217                 .flags  = IORESOURCE_IRQ,
 218         },
 219 };
 220
 221 static struct platform_device tmu2_device = {
 222         .name           = "sh_tmu",
 223         .id             = 2,
 224         .dev = {
 225                 .platform_data  = &tmu2_platform_data,
 226         },
 227         .resource       = tmu2_resources,
 228         .num_resources  = ARRAY_SIZE(tmu2_resources),
 229 };
 230
 231 static struct sh_timer_config tmu3_platform_data = {
 232         .channel_offset = 0x04,
 233         .timer_bit = 0,
 234 };
 235
 236 static struct resource tmu3_resources[] = {
 237         [0] = {
 238                 .start  = 0xffd88008,
 239                 .end    = 0xffd88013,
 240                 .flags  = IORESOURCE_MEM,
 241         },
 242         [1] = {
 243                 .start  = evt2irq(0xe00),
 244                 .flags  = IORESOURCE_IRQ,
 245         },
 246 };
 247
 248 static struct platform_device tmu3_device = {
 249         .name           = "sh_tmu",
 250         .id             = 3,
 251         .dev = {
 252                 .platform_data  = &tmu3_platform_data,
 253         },
 254         .resource       = tmu3_resources,
 255         .num_resources  = ARRAY_SIZE(tmu3_resources),
 256 };
 257
 258 static struct sh_timer_config tmu4_platform_data = {
 259         .channel_offset = 0x10,
 260         .timer_bit = 1,
 261 };
 262
 263 static struct resource tmu4_resources[] = {
 264         [0] = {
 265                 .start  = 0xffd88014,
 266                 .end    = 0xffd8801f,
 267                 .flags  = IORESOURCE_MEM,
 268         },
 269         [1] = {
 270                 .start  = evt2irq(0xe20),
 271                 .flags  = IORESOURCE_IRQ,
 272         },
 273 };
 274
 275 static struct platform_device tmu4_device = {
 276         .name           = "sh_tmu",
 277         .id             = 4,
 278         .dev = {
 279                 .platform_data  = &tmu4_platform_data,
 280         },
 281         .resource       = tmu4_resources,
 282         .num_resources  = ARRAY_SIZE(tmu4_resources),
 283 };
 284
 285 static struct sh_timer_config tmu5_platform_data = {
 286         .channel_offset = 0x1c,
 287         .timer_bit = 2,
 288 };
 289
 290 static struct resource tmu5_resources[] = {
 291         [0] = {
 292                 .start  = 0xffd88020,
 293                 .end    = 0xffd8802b,
 294                 .flags  = IORESOURCE_MEM,
 295         },
 296         [1] = {
 297                 .start  = evt2irq(0xe40),
 298                 .flags  = IORESOURCE_IRQ,
 299         },
 300 };
 301
 302 static struct platform_device tmu5_device = {
 303         .name           = "sh_tmu",
 304         .id             = 5,
 305         .dev = {
 306                 .platform_data  = &tmu5_platform_data,
 307         },
 308         .resource       = tmu5_resources,
 309         .num_resources  = ARRAY_SIZE(tmu5_resources),
 310 };
 311
 312 static struct platform_device *sh7763_devices[] __initdata = {
 313         &scif0_device,
 314         &scif1_device,
 315         &scif2_device,
 316         &tmu0_device,
 317         &tmu1_device,
 318         &tmu2_device,
 319         &tmu3_device,
 320         &tmu4_device,
 321         &tmu5_device,
 322         &rtc_device,
 323         &usb_ohci_device,
 324         &usbf_device,
 325 };
 326
 327 static int __init sh7763_devices_setup(void)
 328 {
 329         return platform_add_devices(sh7763_devices,
 330                                     ARRAY_SIZE(sh7763_devices));
 331 }
 332 arch_initcall(sh7763_devices_setup);
 333
 334 static struct platform_device *sh7763_early_devices[] __initdata = {
 335         &scif0_device,
 336         &scif1_device,
 337         &scif2_device,
 338         &tmu0_device,
 339         &tmu1_device,
 340         &tmu2_device,
 341         &tmu3_device,
 342         &tmu4_device,
 343         &tmu5_device,
 344 };
 345
 346 void __init plat_early_device_setup(void)
 347 {
 348         early_platform_add_devices(sh7763_early_devices,
 349                                    ARRAY_SIZE(sh7763_early_devices));
 350 }
 351
 352 enum {
 353         UNUSED = 0,
 354
 355         /* interrupt sources */
 356
 357         IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 358         IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 359         IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 360         IRL_HHLL, IRL_HHLH, IRL_HHHL,
 361
 362         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 363         RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
 364         HUDI, LCDC, DMAC, SCIF0, IIC0, IIC1, CMT, GETHER, HAC,
 365         PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
 366         STIF0, STIF1, SCIF1, SIOF0, SIOF1, SIOF2,
 367         USBH, USBF, TPU, PCC, MMCIF, SIM,
 368         TMU3, TMU4, TMU5, ADC, SSI0, SSI1, SSI2, SSI3,
 369         SCIF2, GPIO,
 370
 371         /* interrupt groups */
 372
 373         TMU012, TMU345,
 374 };
 375
 376 static struct intc_vect vectors[] __initdata = {
 377         INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
 378         INTC_VECT(RTC, 0x4c0),
 379         INTC_VECT(WDT, 0x560), INTC_VECT(TMU0, 0x580),
 380         INTC_VECT(TMU1, 0x5a0), INTC_VECT(TMU2, 0x5c0),
 381         INTC_VECT(TMU2_TICPI, 0x5e0), INTC_VECT(HUDI, 0x600),
 382         INTC_VECT(LCDC, 0x620),
 383         INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
 384         INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
 385         INTC_VECT(DMAC, 0x6c0),
 386         INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
 387         INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
 388         INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
 389         INTC_VECT(IIC0, 0x8A0), INTC_VECT(IIC1, 0x8C0),
 390         INTC_VECT(CMT, 0x900), INTC_VECT(GETHER, 0x920),
 391         INTC_VECT(GETHER, 0x940), INTC_VECT(GETHER, 0x960),
 392         INTC_VECT(HAC, 0x980),
 393         INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
 394         INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
 395         INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
 396         INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
 397         INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
 398         INTC_VECT(STIF0, 0xb40), INTC_VECT(STIF1, 0xb60),
 399         INTC_VECT(SCIF1, 0xb80), INTC_VECT(SCIF1, 0xba0),
 400         INTC_VECT(SCIF1, 0xbc0), INTC_VECT(SCIF1, 0xbe0),
 401         INTC_VECT(SIOF0, 0xc00), INTC_VECT(SIOF1, 0xc20),
 402         INTC_VECT(USBH, 0xc60), INTC_VECT(USBF, 0xc80),
 403         INTC_VECT(USBF, 0xca0),
 404         INTC_VECT(TPU, 0xcc0), INTC_VECT(PCC, 0xce0),
 405         INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
 406         INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
 407         INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0),
 408         INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0),
 409         INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
 410         INTC_VECT(TMU5, 0xe40), INTC_VECT(ADC, 0xe60),
 411         INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
 412         INTC_VECT(SSI2, 0xec0), INTC_VECT(SSI3, 0xee0),
 413         INTC_VECT(SCIF2, 0xf00), INTC_VECT(SCIF2, 0xf20),
 414         INTC_VECT(SCIF2, 0xf40), INTC_VECT(SCIF2, 0xf60),
 415         INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
 416         INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
 417 };
 418
 419 static struct intc_group groups[] __initdata = {
 420         INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
 421         INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
 422 };
 423
 424 static struct intc_mask_reg mask_registers[] __initdata = {
 425         { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
 426           { 0, 0, 0, 0, 0, 0, GPIO, 0,
 427             SSI0, MMCIF, 0, SIOF0, PCIC5, PCIINTD, PCIINTC, PCIINTB,
 428             PCIINTA, PCISERR, HAC, CMT, 0, 0, 0, DMAC,
 429             HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
 430         { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */
 431           { 0, 0, 0, 0, 0, 0, SCIF2, USBF,
 432             0, 0, STIF1, STIF0, 0, 0, USBH, GETHER,
 433             PCC, 0, 0, ADC, TPU, SIM, SIOF2, SIOF1,
 434             LCDC, 0, IIC1, IIC0, SSI3, SSI2, SSI1, 0 } },
 435 };
 436
 437 static struct intc_prio_reg prio_registers[] __initdata = {
 438         { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
 439                                                  TMU2, TMU2_TICPI } },
 440         { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } },
 441         { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } },
 442         { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { HUDI, DMAC, ADC } },
 443         { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { CMT, HAC,
 444                                                  PCISERR, PCIINTA } },
 445         { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC,
 446                                                  PCIINTD, PCIC5 } },
 447         { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { SIOF0, USBF, MMCIF, SSI0 } },
 448         { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SCIF2, GPIO } },
 449         { 0xffd400a0, 0, 32, 8, /* INT2PRI8 */ { SSI3, SSI2, SSI1, 0 } },
 450         { 0xffd400a4, 0, 32, 8, /* INT2PRI9 */ { LCDC, 0, IIC1, IIC0 } },
 451         { 0xffd400a8, 0, 32, 8, /* INT2PRI10 */ { TPU, SIM, SIOF2, SIOF1 } },
 452         { 0xffd400ac, 0, 32, 8, /* INT2PRI11 */ { PCC } },
 453         { 0xffd400b0, 0, 32, 8, /* INT2PRI12 */ { 0, 0, USBH, GETHER } },
 454         { 0xffd400b4, 0, 32, 8, /* INT2PRI13 */ { 0, 0, STIF1, STIF0 } },
 455 };
 456
 457 static DECLARE_INTC_DESC(intc_desc, "sh7763", vectors, groups,
 458                          mask_registers, prio_registers, NULL);
 459
 460 /* Support for external interrupt pins in IRQ mode */
 461 static struct intc_vect irq_vectors[] __initdata = {
 462         INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
 463         INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
 464         INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
 465         INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
 466 };
 467
 468 static struct intc_mask_reg irq_mask_registers[] __initdata = {
 469         { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
 470           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 471 };
 472
 473 static struct intc_prio_reg irq_prio_registers[] __initdata = {
 474         { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
 475                                                IRQ4, IRQ5, IRQ6, IRQ7 } },
 476 };
 477
 478 static struct intc_sense_reg irq_sense_registers[] __initdata = {
 479         { 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
 480                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
 481 };
 482
 483 static struct intc_mask_reg irq_ack_registers[] __initdata = {
 484         { 0xffd00024, 0, 32, /* INTREQ */
 485           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 486 };
 487
 488 static DECLARE_INTC_DESC_ACK(intc_irq_desc, "sh7763-irq", irq_vectors,
 489                              NULL, irq_mask_registers, irq_prio_registers,
 490                              irq_sense_registers, irq_ack_registers);
 491
 492
 493 /* External interrupt pins in IRL mode */
 494 static struct intc_vect irl_vectors[] __initdata = {
 495         INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
 496         INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
 497         INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
 498         INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
 499         INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
 500         INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
 501         INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
 502         INTC_VECT(IRL_HHHL, 0x3c0),
 503 };
 504
 505 static struct intc_mask_reg irl3210_mask_registers[] __initdata = {
 506         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 507           { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 508             IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 509             IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 510             IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
 511 };
 512
 513 static struct intc_mask_reg irl7654_mask_registers[] __initdata = {
 514         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 515           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 516             IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 517             IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 518             IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 519             IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
 520 };
 521
 522 static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7763-irl7654", irl_vectors,
 523                         NULL, irl7654_mask_registers, NULL, NULL);
 524
 525 static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7763-irl3210", irl_vectors,
 526                         NULL, irl3210_mask_registers, NULL, NULL);
 527
 528 #define INTC_ICR0       0xffd00000
 529 #define INTC_INTMSK0    0xffd00044
 530 #define INTC_INTMSK1    0xffd00048
 531 #define INTC_INTMSK2    0xffd40080
 532 #define INTC_INTMSKCLR1 0xffd00068
 533 #define INTC_INTMSKCLR2 0xffd40084
 534
 535 void __init plat_irq_setup(void)
 536 {
 537         /* disable IRQ7-0 */
 538         __raw_writel(0xff000000, INTC_INTMSK0);
 539
 540         /* disable IRL3-0 + IRL7-4 */
 541         __raw_writel(0xc0000000, INTC_INTMSK1);
 542         __raw_writel(0xfffefffe, INTC_INTMSK2);
 543
 544         register_intc_controller(&intc_desc);
 545 }
 546
 547 void __init plat_irq_setup_pins(int mode)
 548 {
 549         switch (mode) {
 550         case IRQ_MODE_IRQ:
 551                 /* select IRQ mode for IRL3-0 + IRL7-4 */
 552                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
 553                 register_intc_controller(&intc_irq_desc);
 554                 break;
 555         case IRQ_MODE_IRL7654:
 556                 /* enable IRL7-4 but don't provide any masking */
 557                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 558                 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
 559                 break;
 560         case IRQ_MODE_IRL3210:
 561                 /* enable IRL0-3 but don't provide any masking */
 562                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 563                 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
 564                 break;
 565         case IRQ_MODE_IRL7654_MASK:
 566                 /* enable IRL7-4 and mask using cpu intc controller */
 567                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 568                 register_intc_controller(&intc_irl7654_desc);
 569                 break;
 570         case IRQ_MODE_IRL3210_MASK:
 571                 /* enable IRL0-3 and mask using cpu intc controller */
 572                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 573                 register_intc_controller(&intc_irl3210_desc);
 574                 break;
 575         default:
 576                 BUG();
 577         }
 578 }