arch/sh/kernel/cpu/sh4a/setup-sh7757.c

   1 /*
   2  * SH7757 Setup
   3  *
   4  * Copyright (C) 2009, 2011  Renesas Solutions Corp.
   5  *
   6  *  based on setup-sh7785.c : Copyright (C) 2007  Paul Mundt
   7  *
   8  * This file is subject to the terms and conditions of the GNU General Public
   9  * License.  See the file "COPYING" in the main directory of this archive
  10  * for more details.
  11  */
  12 #include <linux/platform_device.h>
  13 #include <linux/init.h>
  14 #include <linux/serial.h>
  15 #include <linux/serial_sci.h>
  16 #include <linux/io.h>
  17 #include <linux/mm.h>
  18 #include <linux/dma-mapping.h>
  19 #include <linux/sh_timer.h>
  20 #include <linux/sh_dma.h>
  21 #include <linux/sh_intc.h>
  22 #include <linux/usb/ohci_pdriver.h>
  23 #include <cpu/dma-register.h>
  24 #include <cpu/sh7757.h>
  25
  26 static struct plat_sci_port scif2_platform_data = {
  27         .flags          = UPF_BOOT_AUTOCONF,
  28         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
  29         .type           = PORT_SCIF,
  30 };
  31
  32 static struct resource scif2_resources[] = {
  33         DEFINE_RES_MEM(0xfe4b0000, 0x100),              /* SCIF2 */
  34         DEFINE_RES_IRQ(evt2irq(0x700)),
  35 };
  36
  37 static struct platform_device scif2_device = {
  38         .name           = "sh-sci",
  39         .id             = 0,
  40         .resource       = scif2_resources,
  41         .num_resources  = ARRAY_SIZE(scif2_resources),
  42         .dev            = {
  43                 .platform_data  = &scif2_platform_data,
  44         },
  45 };
  46
  47 static struct plat_sci_port scif3_platform_data = {
  48         .flags          = UPF_BOOT_AUTOCONF,
  49         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
  50         .type           = PORT_SCIF,
  51 };
  52
  53 static struct resource scif3_resources[] = {
  54         DEFINE_RES_MEM(0xfe4c0000, 0x100),              /* SCIF3 */
  55         DEFINE_RES_IRQ(evt2irq(0xb80)),
  56 };
  57
  58 static struct platform_device scif3_device = {
  59         .name           = "sh-sci",
  60         .id             = 1,
  61         .resource       = scif3_resources,
  62         .num_resources  = ARRAY_SIZE(scif3_resources),
  63         .dev            = {
  64                 .platform_data  = &scif3_platform_data,
  65         },
  66 };
  67
  68 static struct plat_sci_port scif4_platform_data = {
  69         .flags          = UPF_BOOT_AUTOCONF,
  70         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
  71         .type           = PORT_SCIF,
  72 };
  73
  74 static struct resource scif4_resources[] = {
  75         DEFINE_RES_MEM(0xfe4d0000, 0x100),              /* SCIF4 */
  76         DEFINE_RES_IRQ(evt2irq(0xf00)),
  77 };
  78
  79 static struct platform_device scif4_device = {
  80         .name           = "sh-sci",
  81         .id             = 2,
  82         .resource       = scif4_resources,
  83         .num_resources  = ARRAY_SIZE(scif4_resources),
  84         .dev            = {
  85                 .platform_data  = &scif4_platform_data,
  86         },
  87 };
  88
  89 static struct sh_timer_config tmu0_platform_data = {
  90         .channel_offset = 0x04,
  91         .timer_bit = 0,
  92         .clockevent_rating = 200,
  93 };
  94
  95 static struct resource tmu0_resources[] = {
  96         [0] = {
  97                 .start  = 0xfe430008,
  98                 .end    = 0xfe430013,
  99                 .flags  = IORESOURCE_MEM,
 100         },
 101         [1] = {
 102                 .start  = evt2irq(0x580),
 103                 .flags  = IORESOURCE_IRQ,
 104         },
 105 };
 106
 107 static struct platform_device tmu0_device = {
 108         .name           = "sh_tmu",
 109         .id             = 0,
 110         .dev = {
 111                 .platform_data  = &tmu0_platform_data,
 112         },
 113         .resource       = tmu0_resources,
 114         .num_resources  = ARRAY_SIZE(tmu0_resources),
 115 };
 116
 117 static struct sh_timer_config tmu1_platform_data = {
 118         .channel_offset = 0x10,
 119         .timer_bit = 1,
 120         .clocksource_rating = 200,
 121 };
 122
 123 static struct resource tmu1_resources[] = {
 124         [0] = {
 125                 .start  = 0xfe430014,
 126                 .end    = 0xfe43001f,
 127                 .flags  = IORESOURCE_MEM,
 128         },
 129         [1] = {
 130                 .start  = evt2irq(0x5a0),
 131                 .flags  = IORESOURCE_IRQ,
 132         },
 133 };
 134
 135 static struct platform_device tmu1_device = {
 136         .name           = "sh_tmu",
 137         .id             = 1,
 138         .dev = {
 139                 .platform_data  = &tmu1_platform_data,
 140         },
 141         .resource       = tmu1_resources,
 142         .num_resources  = ARRAY_SIZE(tmu1_resources),
 143 };
 144
 145 static struct resource spi0_resources[] = {
 146         [0] = {
 147                 .start  = 0xfe002000,
 148                 .end    = 0xfe0020ff,
 149                 .flags  = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
 150         },
 151         [1] = {
 152                 .start  = evt2irq(0xcc0),
 153                 .flags  = IORESOURCE_IRQ,
 154         },
 155 };
 156
 157 /* DMA */
 158 static const struct sh_dmae_slave_config sh7757_dmae0_slaves[] = {
 159         {
 160                 .slave_id       = SHDMA_SLAVE_SDHI_TX,
 161                 .addr           = 0x1fe50030,
 162                 .chcr           = SM_INC | 0x800 | 0x40000000 |
 163                                   TS_INDEX2VAL(XMIT_SZ_16BIT),
 164                 .mid_rid        = 0xc5,
 165         },
 166         {
 167                 .slave_id       = SHDMA_SLAVE_SDHI_RX,
 168                 .addr           = 0x1fe50030,
 169                 .chcr           = DM_INC | 0x800 | 0x40000000 |
 170                                   TS_INDEX2VAL(XMIT_SZ_16BIT),
 171                 .mid_rid        = 0xc6,
 172         },
 173         {
 174                 .slave_id       = SHDMA_SLAVE_MMCIF_TX,
 175                 .addr           = 0x1fcb0034,
 176                 .chcr           = SM_INC | 0x800 | 0x40000000 |
 177                                   TS_INDEX2VAL(XMIT_SZ_32BIT),
 178                 .mid_rid        = 0xd3,
 179         },
 180         {
 181                 .slave_id       = SHDMA_SLAVE_MMCIF_RX,
 182                 .addr           = 0x1fcb0034,
 183                 .chcr           = DM_INC | 0x800 | 0x40000000 |
 184                                   TS_INDEX2VAL(XMIT_SZ_32BIT),
 185                 .mid_rid        = 0xd7,
 186         },
 187 };
 188
 189 static const struct sh_dmae_slave_config sh7757_dmae1_slaves[] = {
 190         {
 191                 .slave_id       = SHDMA_SLAVE_SCIF2_TX,
 192                 .addr           = 0x1f4b000c,
 193                 .chcr           = SM_INC | 0x800 | 0x40000000 |
 194                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 195                 .mid_rid        = 0x21,
 196         },
 197         {
 198                 .slave_id       = SHDMA_SLAVE_SCIF2_RX,
 199                 .addr           = 0x1f4b0014,
 200                 .chcr           = DM_INC | 0x800 | 0x40000000 |
 201                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 202                 .mid_rid        = 0x22,
 203         },
 204         {
 205                 .slave_id       = SHDMA_SLAVE_SCIF3_TX,
 206                 .addr           = 0x1f4c000c,
 207                 .chcr           = SM_INC | 0x800 | 0x40000000 |
 208                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 209                 .mid_rid        = 0x29,
 210         },
 211         {
 212                 .slave_id       = SHDMA_SLAVE_SCIF3_RX,
 213                 .addr           = 0x1f4c0014,
 214                 .chcr           = DM_INC | 0x800 | 0x40000000 |
 215                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 216                 .mid_rid        = 0x2a,
 217         },
 218         {
 219                 .slave_id       = SHDMA_SLAVE_SCIF4_TX,
 220                 .addr           = 0x1f4d000c,
 221                 .chcr           = SM_INC | 0x800 | 0x40000000 |
 222                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 223                 .mid_rid        = 0x41,
 224         },
 225         {
 226                 .slave_id       = SHDMA_SLAVE_SCIF4_RX,
 227                 .addr           = 0x1f4d0014,
 228                 .chcr           = DM_INC | 0x800 | 0x40000000 |
 229                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 230                 .mid_rid        = 0x42,
 231         },
 232         {
 233                 .slave_id       = SHDMA_SLAVE_RSPI_TX,
 234                 .addr           = 0xfe480004,
 235                 .chcr           = SM_INC | 0x800 | 0x40000000 |
 236                                   TS_INDEX2VAL(XMIT_SZ_16BIT),
 237                 .mid_rid        = 0xc1,
 238         },
 239         {
 240                 .slave_id       = SHDMA_SLAVE_RSPI_RX,
 241                 .addr           = 0xfe480004,
 242                 .chcr           = DM_INC | 0x800 | 0x40000000 |
 243                                   TS_INDEX2VAL(XMIT_SZ_16BIT),
 244                 .mid_rid        = 0xc2,
 245         },
 246 };
 247
 248 static const struct sh_dmae_slave_config sh7757_dmae2_slaves[] = {
 249         {
 250                 .slave_id       = SHDMA_SLAVE_RIIC0_TX,
 251                 .addr           = 0x1e500012,
 252                 .chcr           = SM_INC | 0x800 | 0x40000000 |
 253                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 254                 .mid_rid        = 0x21,
 255         },
 256         {
 257                 .slave_id       = SHDMA_SLAVE_RIIC0_RX,
 258                 .addr           = 0x1e500013,
 259                 .chcr           = DM_INC | 0x800 | 0x40000000 |
 260                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 261                 .mid_rid        = 0x22,
 262         },
 263         {
 264                 .slave_id       = SHDMA_SLAVE_RIIC1_TX,
 265                 .addr           = 0x1e510012,
 266                 .chcr           = SM_INC | 0x800 | 0x40000000 |
 267                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 268                 .mid_rid        = 0x29,
 269         },
 270         {
 271                 .slave_id       = SHDMA_SLAVE_RIIC1_RX,
 272                 .addr           = 0x1e510013,
 273                 .chcr           = DM_INC | 0x800 | 0x40000000 |
 274                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 275                 .mid_rid        = 0x2a,
 276         },
 277         {
 278                 .slave_id       = SHDMA_SLAVE_RIIC2_TX,
 279                 .addr           = 0x1e520012,
 280                 .chcr           = SM_INC | 0x800 | 0x40000000 |
 281                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 282                 .mid_rid        = 0xa1,
 283         },
 284         {
 285                 .slave_id       = SHDMA_SLAVE_RIIC2_RX,
 286                 .addr           = 0x1e520013,
 287                 .chcr           = DM_INC | 0x800 | 0x40000000 |
 288                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 289                 .mid_rid        = 0xa2,
 290         },
 291         {
 292                 .slave_id       = SHDMA_SLAVE_RIIC3_TX,
 293                 .addr           = 0x1e530012,
 294                 .chcr           = SM_INC | 0x800 | 0x40000000 |
 295                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 296                 .mid_rid        = 0xa9,
 297         },
 298         {
 299                 .slave_id       = SHDMA_SLAVE_RIIC3_RX,
 300                 .addr           = 0x1e530013,
 301                 .chcr           = DM_INC | 0x800 | 0x40000000 |
 302                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 303                 .mid_rid        = 0xaf,
 304         },
 305         {
 306                 .slave_id       = SHDMA_SLAVE_RIIC4_TX,
 307                 .addr           = 0x1e540012,
 308                 .chcr           = SM_INC | 0x800 | 0x40000000 |
 309                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 310                 .mid_rid        = 0xc5,
 311         },
 312         {
 313                 .slave_id       = SHDMA_SLAVE_RIIC4_RX,
 314                 .addr           = 0x1e540013,
 315                 .chcr           = DM_INC | 0x800 | 0x40000000 |
 316                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 317                 .mid_rid        = 0xc6,
 318         },
 319 };
 320
 321 static const struct sh_dmae_slave_config sh7757_dmae3_slaves[] = {
 322         {
 323                 .slave_id       = SHDMA_SLAVE_RIIC5_TX,
 324                 .addr           = 0x1e550012,
 325                 .chcr           = SM_INC | 0x800 | 0x40000000 |
 326                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 327                 .mid_rid        = 0x21,
 328         },
 329         {
 330                 .slave_id       = SHDMA_SLAVE_RIIC5_RX,
 331                 .addr           = 0x1e550013,
 332                 .chcr           = DM_INC | 0x800 | 0x40000000 |
 333                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 334                 .mid_rid        = 0x22,
 335         },
 336         {
 337                 .slave_id       = SHDMA_SLAVE_RIIC6_TX,
 338                 .addr           = 0x1e560012,
 339                 .chcr           = SM_INC | 0x800 | 0x40000000 |
 340                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 341                 .mid_rid        = 0x29,
 342         },
 343         {
 344                 .slave_id       = SHDMA_SLAVE_RIIC6_RX,
 345                 .addr           = 0x1e560013,
 346                 .chcr           = DM_INC | 0x800 | 0x40000000 |
 347                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 348                 .mid_rid        = 0x2a,
 349         },
 350         {
 351                 .slave_id       = SHDMA_SLAVE_RIIC7_TX,
 352                 .addr           = 0x1e570012,
 353                 .chcr           = SM_INC | 0x800 | 0x40000000 |
 354                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 355                 .mid_rid        = 0x41,
 356         },
 357         {
 358                 .slave_id       = SHDMA_SLAVE_RIIC7_RX,
 359                 .addr           = 0x1e570013,
 360                 .chcr           = DM_INC | 0x800 | 0x40000000 |
 361                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 362                 .mid_rid        = 0x42,
 363         },
 364         {
 365                 .slave_id       = SHDMA_SLAVE_RIIC8_TX,
 366                 .addr           = 0x1e580012,
 367                 .chcr           = SM_INC | 0x800 | 0x40000000 |
 368                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 369                 .mid_rid        = 0x45,
 370         },
 371         {
 372                 .slave_id       = SHDMA_SLAVE_RIIC8_RX,
 373                 .addr           = 0x1e580013,
 374                 .chcr           = DM_INC | 0x800 | 0x40000000 |
 375                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 376                 .mid_rid        = 0x46,
 377         },
 378         {
 379                 .slave_id       = SHDMA_SLAVE_RIIC9_TX,
 380                 .addr           = 0x1e590012,
 381                 .chcr           = SM_INC | 0x800 | 0x40000000 |
 382                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 383                 .mid_rid        = 0x51,
 384         },
 385         {
 386                 .slave_id       = SHDMA_SLAVE_RIIC9_RX,
 387                 .addr           = 0x1e590013,
 388                 .chcr           = DM_INC | 0x800 | 0x40000000 |
 389                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
 390                 .mid_rid        = 0x52,
 391         },
 392 };
 393
 394 static const struct sh_dmae_channel sh7757_dmae_channels[] = {
 395         {
 396                 .offset = 0,
 397                 .dmars = 0,
 398                 .dmars_bit = 0,
 399         }, {
 400                 .offset = 0x10,
 401                 .dmars = 0,
 402                 .dmars_bit = 8,
 403         }, {
 404                 .offset = 0x20,
 405                 .dmars = 4,
 406                 .dmars_bit = 0,
 407         }, {
 408                 .offset = 0x30,
 409                 .dmars = 4,
 410                 .dmars_bit = 8,
 411         }, {
 412                 .offset = 0x50,
 413                 .dmars = 8,
 414                 .dmars_bit = 0,
 415         }, {
 416                 .offset = 0x60,
 417                 .dmars = 8,
 418                 .dmars_bit = 8,
 419         }
 420 };
 421
 422 static const unsigned int ts_shift[] = TS_SHIFT;
 423
 424 static struct sh_dmae_pdata dma0_platform_data = {
 425         .slave          = sh7757_dmae0_slaves,
 426         .slave_num      = ARRAY_SIZE(sh7757_dmae0_slaves),
 427         .channel        = sh7757_dmae_channels,
 428         .channel_num    = ARRAY_SIZE(sh7757_dmae_channels),
 429         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
 430         .ts_low_mask    = CHCR_TS_LOW_MASK,
 431         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
 432         .ts_high_mask   = CHCR_TS_HIGH_MASK,
 433         .ts_shift       = ts_shift,
 434         .ts_shift_num   = ARRAY_SIZE(ts_shift),
 435         .dmaor_init     = DMAOR_INIT,
 436 };
 437
 438 static struct sh_dmae_pdata dma1_platform_data = {
 439         .slave          = sh7757_dmae1_slaves,
 440         .slave_num      = ARRAY_SIZE(sh7757_dmae1_slaves),
 441         .channel        = sh7757_dmae_channels,
 442         .channel_num    = ARRAY_SIZE(sh7757_dmae_channels),
 443         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
 444         .ts_low_mask    = CHCR_TS_LOW_MASK,
 445         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
 446         .ts_high_mask   = CHCR_TS_HIGH_MASK,
 447         .ts_shift       = ts_shift,
 448         .ts_shift_num   = ARRAY_SIZE(ts_shift),
 449         .dmaor_init     = DMAOR_INIT,
 450 };
 451
 452 static struct sh_dmae_pdata dma2_platform_data = {
 453         .slave          = sh7757_dmae2_slaves,
 454         .slave_num      = ARRAY_SIZE(sh7757_dmae2_slaves),
 455         .channel        = sh7757_dmae_channels,
 456         .channel_num    = ARRAY_SIZE(sh7757_dmae_channels),
 457         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
 458         .ts_low_mask    = CHCR_TS_LOW_MASK,
 459         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
 460         .ts_high_mask   = CHCR_TS_HIGH_MASK,
 461         .ts_shift       = ts_shift,
 462         .ts_shift_num   = ARRAY_SIZE(ts_shift),
 463         .dmaor_init     = DMAOR_INIT,
 464 };
 465
 466 static struct sh_dmae_pdata dma3_platform_data = {
 467         .slave          = sh7757_dmae3_slaves,
 468         .slave_num      = ARRAY_SIZE(sh7757_dmae3_slaves),
 469         .channel        = sh7757_dmae_channels,
 470         .channel_num    = ARRAY_SIZE(sh7757_dmae_channels),
 471         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
 472         .ts_low_mask    = CHCR_TS_LOW_MASK,
 473         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
 474         .ts_high_mask   = CHCR_TS_HIGH_MASK,
 475         .ts_shift       = ts_shift,
 476         .ts_shift_num   = ARRAY_SIZE(ts_shift),
 477         .dmaor_init     = DMAOR_INIT,
 478 };
 479
 480 /* channel 0 to 5 */
 481 static struct resource sh7757_dmae0_resources[] = {
 482         [0] = {
 483                 /* Channel registers and DMAOR */
 484                 .start  = 0xff608020,
 485                 .end    = 0xff60808f,
 486                 .flags  = IORESOURCE_MEM,
 487         },
 488         [1] = {
 489                 /* DMARSx */
 490                 .start  = 0xff609000,
 491                 .end    = 0xff60900b,
 492                 .flags  = IORESOURCE_MEM,
 493         },
 494         {
 495                 .name   = "error_irq",
 496                 .start  = evt2irq(0x640),
 497                 .end    = evt2irq(0x640),
 498                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 499         },
 500 };
 501
 502 /* channel 6 to 11 */
 503 static struct resource sh7757_dmae1_resources[] = {
 504         [0] = {
 505                 /* Channel registers and DMAOR */
 506                 .start  = 0xff618020,
 507                 .end    = 0xff61808f,
 508                 .flags  = IORESOURCE_MEM,
 509         },
 510         [1] = {
 511                 /* DMARSx */
 512                 .start  = 0xff619000,
 513                 .end    = 0xff61900b,
 514                 .flags  = IORESOURCE_MEM,
 515         },
 516         {
 517                 .name   = "error_irq",
 518                 .start  = evt2irq(0x640),
 519                 .end    = evt2irq(0x640),
 520                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 521         },
 522         {
 523                 /* IRQ for channels 4 */
 524                 .start  = evt2irq(0x7c0),
 525                 .end    = evt2irq(0x7c0),
 526                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 527         },
 528         {
 529                 /* IRQ for channels 5 */
 530                 .start  = evt2irq(0x7c0),
 531                 .end    = evt2irq(0x7c0),
 532                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 533         },
 534         {
 535                 /* IRQ for channels 6 */
 536                 .start  = evt2irq(0xd00),
 537                 .end    = evt2irq(0xd00),
 538                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 539         },
 540         {
 541                 /* IRQ for channels 7 */
 542                 .start  = evt2irq(0xd00),
 543                 .end    = evt2irq(0xd00),
 544                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 545         },
 546         {
 547                 /* IRQ for channels 8 */
 548                 .start  = evt2irq(0xd00),
 549                 .end    = evt2irq(0xd00),
 550                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 551         },
 552         {
 553                 /* IRQ for channels 9 */
 554                 .start  = evt2irq(0xd00),
 555                 .end    = evt2irq(0xd00),
 556                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 557         },
 558         {
 559                 /* IRQ for channels 10 */
 560                 .start  = evt2irq(0xd00),
 561                 .end    = evt2irq(0xd00),
 562                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 563         },
 564         {
 565                 /* IRQ for channels 11 */
 566                 .start  = evt2irq(0xd00),
 567                 .end    = evt2irq(0xd00),
 568                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 569         },
 570 };
 571
 572 /* channel 12 to 17 */
 573 static struct resource sh7757_dmae2_resources[] = {
 574         [0] = {
 575                 /* Channel registers and DMAOR */
 576                 .start  = 0xff708020,
 577                 .end    = 0xff70808f,
 578                 .flags  = IORESOURCE_MEM,
 579         },
 580         [1] = {
 581                 /* DMARSx */
 582                 .start  = 0xff709000,
 583                 .end    = 0xff70900b,
 584                 .flags  = IORESOURCE_MEM,
 585         },
 586         {
 587                 .name   = "error_irq",
 588                 .start  = evt2irq(0x2a60),
 589                 .end    = evt2irq(0x2a60),
 590                 .flags  = IORESOURCE_IRQ,
 591         },
 592         {
 593                 /* IRQ for channels 12 to 16 */
 594                 .start  = evt2irq(0x2400),
 595                 .end    = evt2irq(0x2480),
 596                 .flags  = IORESOURCE_IRQ,
 597         },
 598         {
 599                 /* IRQ for channel 17 */
 600                 .start  = evt2irq(0x24e0),
 601                 .end    = evt2irq(0x24e0),
 602                 .flags  = IORESOURCE_IRQ,
 603         },
 604 };
 605
 606 /* channel 18 to 23 */
 607 static struct resource sh7757_dmae3_resources[] = {
 608         [0] = {
 609                 /* Channel registers and DMAOR */
 610                 .start  = 0xff718020,
 611                 .end    = 0xff71808f,
 612                 .flags  = IORESOURCE_MEM,
 613         },
 614         [1] = {
 615                 /* DMARSx */
 616                 .start  = 0xff719000,
 617                 .end    = 0xff71900b,
 618                 .flags  = IORESOURCE_MEM,
 619         },
 620         {
 621                 .name   = "error_irq",
 622                 .start  = evt2irq(0x2a80),
 623                 .end    = evt2irq(0x2a80),
 624                 .flags  = IORESOURCE_IRQ,
 625         },
 626         {
 627                 /* IRQ for channels 18 to 22 */
 628                 .start  = evt2irq(0x2500),
 629                 .end    = evt2irq(0x2580),
 630                 .flags  = IORESOURCE_IRQ,
 631         },
 632         {
 633                 /* IRQ for channel 23 */
 634                 .start  = evt2irq(0x2600),
 635                 .end    = evt2irq(0x2600),
 636                 .flags  = IORESOURCE_IRQ,
 637         },
 638 };
 639
 640 static struct platform_device dma0_device = {
 641         .name           = "sh-dma-engine",
 642         .id             = 0,
 643         .resource       = sh7757_dmae0_resources,
 644         .num_resources  = ARRAY_SIZE(sh7757_dmae0_resources),
 645         .dev            = {
 646                 .platform_data  = &dma0_platform_data,
 647         },
 648 };
 649
 650 static struct platform_device dma1_device = {
 651         .name           = "sh-dma-engine",
 652         .id             = 1,
 653         .resource       = sh7757_dmae1_resources,
 654         .num_resources  = ARRAY_SIZE(sh7757_dmae1_resources),
 655         .dev            = {
 656                 .platform_data  = &dma1_platform_data,
 657         },
 658 };
 659
 660 static struct platform_device dma2_device = {
 661         .name           = "sh-dma-engine",
 662         .id             = 2,
 663         .resource       = sh7757_dmae2_resources,
 664         .num_resources  = ARRAY_SIZE(sh7757_dmae2_resources),
 665         .dev            = {
 666                 .platform_data  = &dma2_platform_data,
 667         },
 668 };
 669
 670 static struct platform_device dma3_device = {
 671         .name           = "sh-dma-engine",
 672         .id             = 3,
 673         .resource       = sh7757_dmae3_resources,
 674         .num_resources  = ARRAY_SIZE(sh7757_dmae3_resources),
 675         .dev            = {
 676                 .platform_data  = &dma3_platform_data,
 677         },
 678 };
 679
 680 static struct platform_device spi0_device = {
 681         .name   = "sh_spi",
 682         .id     = 0,
 683         .dev    = {
 684                 .dma_mask               = NULL,
 685                 .coherent_dma_mask      = 0xffffffff,
 686         },
 687         .num_resources  = ARRAY_SIZE(spi0_resources),
 688         .resource       = spi0_resources,
 689 };
 690
 691 static struct resource spi1_resources[] = {
 692         {
 693                 .start  = 0xffd8ee70,
 694                 .end    = 0xffd8eeff,
 695                 .flags  = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
 696         },
 697         {
 698                 .start  = evt2irq(0x8c0),
 699                 .flags  = IORESOURCE_IRQ,
 700         },
 701 };
 702
 703 static struct platform_device spi1_device = {
 704         .name   = "sh_spi",
 705         .id     = 1,
 706         .num_resources  = ARRAY_SIZE(spi1_resources),
 707         .resource       = spi1_resources,
 708 };
 709
 710 static struct resource rspi_resources[] = {
 711         {
 712                 .start  = 0xfe480000,
 713                 .end    = 0xfe4800ff,
 714                 .flags  = IORESOURCE_MEM,
 715         },
 716         {
 717                 .start  = evt2irq(0x1d80),
 718                 .flags  = IORESOURCE_IRQ,
 719         },
 720 };
 721
 722 static struct platform_device rspi_device = {
 723         .name   = "rspi",
 724         .id     = 2,
 725         .num_resources  = ARRAY_SIZE(rspi_resources),
 726         .resource       = rspi_resources,
 727 };
 728
 729 static struct resource usb_ehci_resources[] = {
 730         [0] = {
 731                 .start  = 0xfe4f1000,
 732                 .end    = 0xfe4f10ff,
 733                 .flags  = IORESOURCE_MEM,
 734         },
 735         [1] = {
 736                 .start  = evt2irq(0x920),
 737                 .end    = evt2irq(0x920),
 738                 .flags  = IORESOURCE_IRQ,
 739         },
 740 };
 741
 742 static struct platform_device usb_ehci_device = {
 743         .name           = "sh_ehci",
 744         .id             = -1,
 745         .dev = {
 746                 .dma_mask = &usb_ehci_device.dev.coherent_dma_mask,
 747                 .coherent_dma_mask = DMA_BIT_MASK(32),
 748         },
 749         .num_resources  = ARRAY_SIZE(usb_ehci_resources),
 750         .resource       = usb_ehci_resources,
 751 };
 752
 753 static struct resource usb_ohci_resources[] = {
 754         [0] = {
 755                 .start  = 0xfe4f1800,
 756                 .end    = 0xfe4f18ff,
 757                 .flags  = IORESOURCE_MEM,
 758         },
 759         [1] = {
 760                 .start  = evt2irq(0x920),
 761                 .end    = evt2irq(0x920),
 762                 .flags  = IORESOURCE_IRQ,
 763         },
 764 };
 765
 766 static struct usb_ohci_pdata usb_ohci_pdata;
 767
 768 static struct platform_device usb_ohci_device = {
 769         .name           = "ohci-platform",
 770         .id             = -1,
 771         .dev = {
 772                 .dma_mask = &usb_ohci_device.dev.coherent_dma_mask,
 773                 .coherent_dma_mask = DMA_BIT_MASK(32),
 774                 .platform_data  = &usb_ohci_pdata,
 775         },
 776         .num_resources  = ARRAY_SIZE(usb_ohci_resources),
 777         .resource       = usb_ohci_resources,
 778 };
 779
 780 static struct platform_device *sh7757_devices[] __initdata = {
 781         &scif2_device,
 782         &scif3_device,
 783         &scif4_device,
 784         &tmu0_device,
 785         &tmu1_device,
 786         &dma0_device,
 787         &dma1_device,
 788         &dma2_device,
 789         &dma3_device,
 790         &spi0_device,
 791         &spi1_device,
 792         &rspi_device,
 793         &usb_ehci_device,
 794         &usb_ohci_device,
 795 };
 796
 797 static int __init sh7757_devices_setup(void)
 798 {
 799         return platform_add_devices(sh7757_devices,
 800                                     ARRAY_SIZE(sh7757_devices));
 801 }
 802 arch_initcall(sh7757_devices_setup);
 803
 804 static struct platform_device *sh7757_early_devices[] __initdata = {
 805         &scif2_device,
 806         &scif3_device,
 807         &scif4_device,
 808         &tmu0_device,
 809         &tmu1_device,
 810 };
 811
 812 void __init plat_early_device_setup(void)
 813 {
 814         early_platform_add_devices(sh7757_early_devices,
 815                                    ARRAY_SIZE(sh7757_early_devices));
 816 }
 817
 818 enum {
 819         UNUSED = 0,
 820
 821         /* interrupt sources */
 822
 823         IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 824         IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 825         IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 826         IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
 827
 828         IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
 829         IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
 830         IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
 831         IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
 832         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 833
 834         SDHI, DVC,
 835         IRQ8, IRQ9, IRQ11, IRQ10, IRQ12, IRQ13, IRQ14, IRQ15,
 836         TMU0, TMU1, TMU2, TMU2_TICPI, TMU3, TMU4, TMU5,
 837         HUDI,
 838         ARC4,
 839         DMAC0_5, DMAC6_7, DMAC8_11,
 840         SCIF0, SCIF1, SCIF2, SCIF3, SCIF4,
 841         USB0, USB1,
 842         JMC,
 843         SPI0, SPI1,
 844         TMR01, TMR23, TMR45,
 845         FRT,
 846         LPC, LPC5, LPC6, LPC7, LPC8,
 847         PECI0, PECI1, PECI2, PECI3, PECI4, PECI5,
 848         ETHERC,
 849         ADC0, ADC1,
 850         SIM,
 851         IIC0_0, IIC0_1, IIC0_2, IIC0_3,
 852         IIC1_0, IIC1_1, IIC1_2, IIC1_3,
 853         IIC2_0, IIC2_1, IIC2_2, IIC2_3,
 854         IIC3_0, IIC3_1, IIC3_2, IIC3_3,
 855         IIC4_0, IIC4_1, IIC4_2, IIC4_3,
 856         IIC5_0, IIC5_1, IIC5_2, IIC5_3,
 857         IIC6_0, IIC6_1, IIC6_2, IIC6_3,
 858         IIC7_0, IIC7_1, IIC7_2, IIC7_3,
 859         IIC8_0, IIC8_1, IIC8_2, IIC8_3,
 860         IIC9_0, IIC9_1, IIC9_2, IIC9_3,
 861         ONFICTL,
 862         MMC1, MMC2,
 863         ECCU,
 864         PCIC,
 865         G200,
 866         RSPI,
 867         SGPIO,
 868         DMINT12, DMINT13, DMINT14, DMINT15, DMINT16, DMINT17, DMINT18, DMINT19,
 869         DMINT20, DMINT21, DMINT22, DMINT23,
 870         DDRECC,
 871         TSIP,
 872         PCIE_BRIDGE,
 873         WDT0B, WDT1B, WDT2B, WDT3B, WDT4B, WDT5B, WDT6B, WDT7B, WDT8B,
 874         GETHER0, GETHER1, GETHER2,
 875         PBIA, PBIB, PBIC,
 876         DMAE2, DMAE3,
 877         SERMUX2, SERMUX3,
 878
 879         /* interrupt groups */
 880
 881         TMU012, TMU345,
 882 };
 883
 884 static struct intc_vect vectors[] __initdata = {
 885         INTC_VECT(SDHI, 0x480), INTC_VECT(SDHI, 0x04a0),
 886         INTC_VECT(SDHI, 0x4c0),
 887         INTC_VECT(DVC, 0x4e0),
 888         INTC_VECT(IRQ8, 0x500), INTC_VECT(IRQ9, 0x520),
 889         INTC_VECT(IRQ10, 0x540),
 890         INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
 891         INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
 892         INTC_VECT(HUDI, 0x600),
 893         INTC_VECT(ARC4, 0x620),
 894         INTC_VECT(DMAC0_5, 0x640), INTC_VECT(DMAC0_5, 0x660),
 895         INTC_VECT(DMAC0_5, 0x680), INTC_VECT(DMAC0_5, 0x6a0),
 896         INTC_VECT(DMAC0_5, 0x6c0),
 897         INTC_VECT(IRQ11, 0x6e0),
 898         INTC_VECT(SCIF2, 0x700), INTC_VECT(SCIF2, 0x720),
 899         INTC_VECT(SCIF2, 0x740), INTC_VECT(SCIF2, 0x760),
 900         INTC_VECT(DMAC0_5, 0x780), INTC_VECT(DMAC0_5, 0x7a0),
 901         INTC_VECT(DMAC6_7, 0x7c0), INTC_VECT(DMAC6_7, 0x7e0),
 902         INTC_VECT(USB0, 0x840),
 903         INTC_VECT(IRQ12, 0x880),
 904         INTC_VECT(JMC, 0x8a0),
 905         INTC_VECT(SPI1, 0x8c0),
 906         INTC_VECT(IRQ13, 0x8e0), INTC_VECT(IRQ14, 0x900),
 907         INTC_VECT(USB1, 0x920),
 908         INTC_VECT(TMR01, 0xa00), INTC_VECT(TMR23, 0xa20),
 909         INTC_VECT(TMR45, 0xa40),
 910         INTC_VECT(FRT, 0xa80),
 911         INTC_VECT(LPC, 0xaa0), INTC_VECT(LPC, 0xac0),
 912         INTC_VECT(LPC, 0xae0), INTC_VECT(LPC, 0xb00),
 913         INTC_VECT(LPC, 0xb20),
 914         INTC_VECT(SCIF0, 0xb40), INTC_VECT(SCIF1, 0xb60),
 915         INTC_VECT(SCIF3, 0xb80), INTC_VECT(SCIF3, 0xba0),
 916         INTC_VECT(SCIF3, 0xbc0), INTC_VECT(SCIF3, 0xbe0),
 917         INTC_VECT(PECI0, 0xc00), INTC_VECT(PECI1, 0xc20),
 918         INTC_VECT(PECI2, 0xc40),
 919         INTC_VECT(IRQ15, 0xc60),
 920         INTC_VECT(ETHERC, 0xc80), INTC_VECT(ETHERC, 0xca0),
 921         INTC_VECT(SPI0, 0xcc0),
 922         INTC_VECT(ADC1, 0xce0),
 923         INTC_VECT(DMAC8_11, 0xd00), INTC_VECT(DMAC8_11, 0xd20),
 924         INTC_VECT(DMAC8_11, 0xd40), INTC_VECT(DMAC8_11, 0xd60),
 925         INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0),
 926         INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0),
 927         INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
 928         INTC_VECT(TMU5, 0xe40),
 929         INTC_VECT(ADC0, 0xe60),
 930         INTC_VECT(SCIF4, 0xf00), INTC_VECT(SCIF4, 0xf20),
 931         INTC_VECT(SCIF4, 0xf40), INTC_VECT(SCIF4, 0xf60),
 932         INTC_VECT(IIC0_0, 0x1400), INTC_VECT(IIC0_1, 0x1420),
 933         INTC_VECT(IIC0_2, 0x1440), INTC_VECT(IIC0_3, 0x1460),
 934         INTC_VECT(IIC1_0, 0x1480), INTC_VECT(IIC1_1, 0x14e0),
 935         INTC_VECT(IIC1_2, 0x1500), INTC_VECT(IIC1_3, 0x1520),
 936         INTC_VECT(IIC2_0, 0x1540), INTC_VECT(IIC2_1, 0x1560),
 937         INTC_VECT(IIC2_2, 0x1580), INTC_VECT(IIC2_3, 0x1600),
 938         INTC_VECT(IIC3_0, 0x1620), INTC_VECT(IIC3_1, 0x1640),
 939         INTC_VECT(IIC3_2, 0x16e0), INTC_VECT(IIC3_3, 0x1700),
 940         INTC_VECT(IIC4_0, 0x17c0), INTC_VECT(IIC4_1, 0x1800),
 941         INTC_VECT(IIC4_2, 0x1820), INTC_VECT(IIC4_3, 0x1840),
 942         INTC_VECT(IIC5_0, 0x1860), INTC_VECT(IIC5_1, 0x1880),
 943         INTC_VECT(IIC5_2, 0x18a0), INTC_VECT(IIC5_3, 0x18c0),
 944         INTC_VECT(IIC6_0, 0x18e0), INTC_VECT(IIC6_1, 0x1900),
 945         INTC_VECT(IIC6_2, 0x1920),
 946         INTC_VECT(ONFICTL, 0x1960),
 947         INTC_VECT(IIC6_3, 0x1980),
 948         INTC_VECT(IIC7_0, 0x19a0), INTC_VECT(IIC7_1, 0x1a00),
 949         INTC_VECT(IIC7_2, 0x1a20), INTC_VECT(IIC7_3, 0x1a40),
 950         INTC_VECT(IIC8_0, 0x1a60), INTC_VECT(IIC8_1, 0x1a80),
 951         INTC_VECT(IIC8_2, 0x1aa0), INTC_VECT(IIC8_3, 0x1b40),
 952         INTC_VECT(IIC9_0, 0x1b60), INTC_VECT(IIC9_1, 0x1b80),
 953         INTC_VECT(IIC9_2, 0x1c00), INTC_VECT(IIC9_3, 0x1c20),
 954         INTC_VECT(MMC1, 0x1c60), INTC_VECT(MMC2, 0x1c80),
 955         INTC_VECT(ECCU, 0x1cc0),
 956         INTC_VECT(PCIC, 0x1ce0),
 957         INTC_VECT(G200, 0x1d00),
 958         INTC_VECT(RSPI, 0x1d80), INTC_VECT(RSPI, 0x1da0),
 959         INTC_VECT(RSPI, 0x1dc0), INTC_VECT(RSPI, 0x1de0),
 960         INTC_VECT(PECI3, 0x1ec0), INTC_VECT(PECI4, 0x1ee0),
 961         INTC_VECT(PECI5, 0x1f00),
 962         INTC_VECT(SGPIO, 0x1f80), INTC_VECT(SGPIO, 0x1fa0),
 963         INTC_VECT(SGPIO, 0x1fc0),
 964         INTC_VECT(DMINT12, 0x2400), INTC_VECT(DMINT13, 0x2420),
 965         INTC_VECT(DMINT14, 0x2440), INTC_VECT(DMINT15, 0x2460),
 966         INTC_VECT(DMINT16, 0x2480), INTC_VECT(DMINT17, 0x24e0),
 967         INTC_VECT(DMINT18, 0x2500), INTC_VECT(DMINT19, 0x2520),
 968         INTC_VECT(DMINT20, 0x2540), INTC_VECT(DMINT21, 0x2560),
 969         INTC_VECT(DMINT22, 0x2580), INTC_VECT(DMINT23, 0x2600),
 970         INTC_VECT(DDRECC, 0x2620),
 971         INTC_VECT(TSIP, 0x2640),
 972         INTC_VECT(PCIE_BRIDGE, 0x27c0),
 973         INTC_VECT(WDT0B, 0x2800), INTC_VECT(WDT1B, 0x2820),
 974         INTC_VECT(WDT2B, 0x2840), INTC_VECT(WDT3B, 0x2860),
 975         INTC_VECT(WDT4B, 0x2880), INTC_VECT(WDT5B, 0x28a0),
 976         INTC_VECT(WDT6B, 0x28c0), INTC_VECT(WDT7B, 0x28e0),
 977         INTC_VECT(WDT8B, 0x2900),
 978         INTC_VECT(GETHER0, 0x2960), INTC_VECT(GETHER1, 0x2980),
 979         INTC_VECT(GETHER2, 0x29a0),
 980         INTC_VECT(PBIA, 0x2a00), INTC_VECT(PBIB, 0x2a20),
 981         INTC_VECT(PBIC, 0x2a40),
 982         INTC_VECT(DMAE2, 0x2a60), INTC_VECT(DMAE3, 0x2a80),
 983         INTC_VECT(SERMUX2, 0x2aa0), INTC_VECT(SERMUX3, 0x2b40),
 984         INTC_VECT(LPC5, 0x2b60), INTC_VECT(LPC6, 0x2b80),
 985         INTC_VECT(LPC7, 0x2c00), INTC_VECT(LPC8, 0x2c20),
 986 };
 987
 988 static struct intc_group groups[] __initdata = {
 989         INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
 990         INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
 991 };
 992
 993 static struct intc_mask_reg mask_registers[] __initdata = {
 994         { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
 995           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 996
 997         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 998           { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 999             IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
1000             IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
1001             IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
1002             IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
1003             IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
1004             IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
1005             IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
1006
1007         { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
1008           { 0, 0, 0, 0, 0, 0, 0, 0,
1009             0, DMAC8_11, 0, PECI0, LPC, FRT, 0, TMR45,
1010             TMR23, TMR01, 0, 0, 0, 0, 0, DMAC0_5,
1011             HUDI, 0, 0, SCIF3, SCIF2, SDHI, TMU345, TMU012
1012              } },
1013
1014         { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */
1015           { IRQ15, IRQ14, IRQ13, IRQ12, IRQ11, IRQ10, SCIF4, ETHERC,
1016             IRQ9, IRQ8, SCIF1, SCIF0, USB0, 0, 0, USB1,
1017             ADC1, 0, DMAC6_7, ADC0, SPI0, SIM, PECI2, PECI1,
1018             ARC4, 0, SPI1, JMC, 0, 0, 0, DVC
1019              } },
1020
1021         { 0xffd10038, 0xffd1003c, 32, /* INT2MSKR2 / INT2MSKCR2 */
1022           { IIC4_1, IIC4_2, IIC5_0, ONFICTL, 0, 0, SGPIO, 0,
1023             0, G200, 0, IIC9_2, IIC8_2, IIC8_1, IIC8_0, IIC7_3,
1024             IIC7_2, IIC7_1, IIC6_3, IIC0_0, IIC0_1, IIC0_2, IIC0_3, IIC3_1,
1025             IIC2_3, 0, IIC2_1, IIC9_1, IIC3_3, IIC1_0, 0, IIC2_2
1026              } },
1027
1028         { 0xffd100d0, 0xffd100d4, 32, /* INT2MSKR3 / INT2MSKCR3 */
1029           { MMC1, IIC6_1, IIC6_0, IIC5_1, IIC3_2, IIC2_0, PECI5, MMC2,
1030             IIC1_3, IIC1_2, IIC9_0, IIC8_3, IIC4_3, IIC7_0, 0, IIC6_2,
1031             PCIC, 0, IIC4_0, 0, ECCU, RSPI, 0, IIC9_3,
1032             IIC3_0, 0, IIC5_3, IIC5_2, 0, 0, 0, IIC1_1
1033              } },
1034
1035         { 0xffd20038, 0xffd2003c, 32, /* INT2MSKR4 / INT2MSKCR4 */
1036           { WDT0B, WDT1B, WDT3B, GETHER0, 0, 0, 0, 0,
1037             0, 0, 0, LPC7, SERMUX2, DMAE3, DMAE2, PBIC,
1038             PBIB, PBIA, GETHER1, DMINT12, DMINT13, DMINT14, DMINT15, TSIP,
1039             DMINT23, 0, DMINT21, LPC6, 0, DMINT16, 0, DMINT22
1040              } },
1041
1042         { 0xffd200d0, 0xffd200d4, 32, /* INT2MSKR5 / INT2MSKCR5 */
1043           { 0, WDT8B, WDT7B, WDT4B, 0, DMINT20, 0, 0,
1044             DMINT19, DMINT18, LPC5, SERMUX3, WDT2B, GETHER2, 0, 0,
1045             0, 0, PCIE_BRIDGE, 0, 0, 0, 0, LPC8,
1046             DDRECC, 0, WDT6B, WDT5B, 0, 0, 0, DMINT17
1047              } },
1048 };
1049
1050 #define INTPRI          0xffd00010
1051 #define INT2PRI0        0xffd40000
1052 #define INT2PRI1        0xffd40004
1053 #define INT2PRI2        0xffd40008
1054 #define INT2PRI3        0xffd4000c
1055 #define INT2PRI4        0xffd40010
1056 #define INT2PRI5        0xffd40014
1057 #define INT2PRI6        0xffd40018
1058 #define INT2PRI7        0xffd4001c
1059 #define INT2PRI8        0xffd400a0
1060 #define INT2PRI9        0xffd400a4
1061 #define INT2PRI10       0xffd400a8
1062 #define INT2PRI11       0xffd400ac
1063 #define INT2PRI12       0xffd400b0
1064 #define INT2PRI13       0xffd400b4
1065 #define INT2PRI14       0xffd400b8
1066 #define INT2PRI15       0xffd400bc
1067 #define INT2PRI16       0xffd10000
1068 #define INT2PRI17       0xffd10004
1069 #define INT2PRI18       0xffd10008
1070 #define INT2PRI19       0xffd1000c
1071 #define INT2PRI20       0xffd10010
1072 #define INT2PRI21       0xffd10014
1073 #define INT2PRI22       0xffd10018
1074 #define INT2PRI23       0xffd1001c
1075 #define INT2PRI24       0xffd100a0
1076 #define INT2PRI25       0xffd100a4
1077 #define INT2PRI26       0xffd100a8
1078 #define INT2PRI27       0xffd100ac
1079 #define INT2PRI28       0xffd100b0
1080 #define INT2PRI29       0xffd100b4
1081 #define INT2PRI30       0xffd100b8
1082 #define INT2PRI31       0xffd100bc
1083 #define INT2PRI32       0xffd20000
1084 #define INT2PRI33       0xffd20004
1085 #define INT2PRI34       0xffd20008
1086 #define INT2PRI35       0xffd2000c
1087 #define INT2PRI36       0xffd20010
1088 #define INT2PRI37       0xffd20014
1089 #define INT2PRI38       0xffd20018
1090 #define INT2PRI39       0xffd2001c
1091 #define INT2PRI40       0xffd200a0
1092 #define INT2PRI41       0xffd200a4
1093 #define INT2PRI42       0xffd200a8
1094 #define INT2PRI43       0xffd200ac
1095 #define INT2PRI44       0xffd200b0
1096 #define INT2PRI45       0xffd200b4
1097 #define INT2PRI46       0xffd200b8
1098 #define INT2PRI47       0xffd200bc
1099
1100 static struct intc_prio_reg prio_registers[] __initdata = {
1101         { INTPRI, 0, 32, 4, { IRQ0, IRQ1, IRQ2, IRQ3,
1102                               IRQ4, IRQ5, IRQ6, IRQ7 } },
1103
1104         { INT2PRI0, 0, 32, 8, { TMU0, TMU1, TMU2, TMU2_TICPI } },
1105         { INT2PRI1, 0, 32, 8, { TMU3, TMU4, TMU5, SDHI } },
1106         { INT2PRI2, 0, 32, 8, { SCIF2, SCIF3, 0, IRQ8 } },
1107         { INT2PRI3, 0, 32, 8, { HUDI, DMAC0_5, ADC0, IRQ9 } },
1108         { INT2PRI4, 0, 32, 8, { IRQ10, 0, TMR01, TMR23 } },
1109         { INT2PRI5, 0, 32, 8, { TMR45, 0, FRT, LPC } },
1110         { INT2PRI6, 0, 32, 8, { PECI0, ETHERC, DMAC8_11, 0 } },
1111         { INT2PRI7, 0, 32, 8, { SCIF4, 0, IRQ11, IRQ12 } },
1112         { INT2PRI8, 0, 32, 8, { 0, 0, 0, DVC } },
1113         { INT2PRI9, 0, 32, 8, { ARC4, 0, SPI1, JMC } },
1114         { INT2PRI10, 0, 32, 8, { SPI0, SIM, PECI2, PECI1 } },
1115         { INT2PRI11, 0, 32, 8, { ADC1, IRQ13, DMAC6_7, IRQ14 } },
1116         { INT2PRI12, 0, 32, 8, { USB0, 0, IRQ15, USB1 } },
1117         { INT2PRI13, 0, 32, 8, { 0, 0, SCIF1, SCIF0 } },
1118
1119         { INT2PRI16, 0, 32, 8, { IIC2_2, 0, 0, 0 } },
1120         { INT2PRI17, 0, 32, 8, { 0, 0, 0, IIC1_0 } },
1121         { INT2PRI18, 0, 32, 8, { IIC3_3, IIC9_1, IIC2_1, IIC1_2 } },
1122         { INT2PRI19, 0, 32, 8, { IIC2_3, IIC3_1, 0, IIC1_3 } },
1123         { INT2PRI20, 0, 32, 8, { IIC2_0, IIC6_3, IIC7_1, IIC7_2 } },
1124         { INT2PRI21, 0, 32, 8, { IIC7_3, IIC8_0, IIC8_1, IIC8_2 } },
1125         { INT2PRI22, 0, 32, 8, { IIC9_2, MMC2, G200, 0 } },
1126         { INT2PRI23, 0, 32, 8, { PECI5, SGPIO, IIC3_2, IIC5_1 } },
1127         { INT2PRI24, 0, 32, 8, { PECI4, PECI3, 0, IIC1_1 } },
1128         { INT2PRI25, 0, 32, 8, { IIC3_0, 0, IIC5_3, IIC5_2 } },
1129         { INT2PRI26, 0, 32, 8, { ECCU, RSPI, 0, IIC9_3 } },
1130         { INT2PRI27, 0, 32, 8, { PCIC, IIC6_0, IIC4_0, IIC6_1 } },
1131         { INT2PRI28, 0, 32, 8, { IIC4_3, IIC7_0, MMC1, IIC6_2 } },
1132         { INT2PRI29, 0, 32, 8, { 0, 0, IIC9_0, IIC8_3 } },
1133         { INT2PRI30, 0, 32, 8, { IIC4_1, IIC4_2, IIC5_0, ONFICTL } },
1134         { INT2PRI31, 0, 32, 8, { IIC0_0, IIC0_1, IIC0_2, IIC0_3 } },
1135         { INT2PRI32, 0, 32, 8, { DMINT22, 0, 0, 0 } },
1136         { INT2PRI33, 0, 32, 8, { 0, 0, 0, DMINT16 } },
1137         { INT2PRI34, 0, 32, 8, { 0, LPC6, DMINT21, DMINT18 } },
1138         { INT2PRI35, 0, 32, 8, { DMINT23, TSIP, 0, DMINT19 } },
1139         { INT2PRI36, 0, 32, 8, { DMINT20, GETHER1, PBIA, PBIB } },
1140         { INT2PRI37, 0, 32, 8, { PBIC, DMAE2, DMAE3, SERMUX2 } },
1141         { INT2PRI38, 0, 32, 8, { LPC7, 0, 0, 0 } },
1142         { INT2PRI39, 0, 32, 8, { 0, 0, 0, WDT4B } },
1143         { INT2PRI40, 0, 32, 8, { 0, 0, 0, DMINT17 } },
1144         { INT2PRI41, 0, 32, 8, { DDRECC, 0, WDT6B, WDT5B } },
1145         { INT2PRI42, 0, 32, 8, { 0, 0, 0, LPC8 } },
1146         { INT2PRI43, 0, 32, 8, { 0, WDT7B, PCIE_BRIDGE, WDT8B } },
1147         { INT2PRI44, 0, 32, 8, { WDT2B, GETHER2, 0, 0 } },
1148         { INT2PRI45, 0, 32, 8, { 0, 0, LPC5, SERMUX3 } },
1149         { INT2PRI46, 0, 32, 8, { WDT0B, WDT1B, WDT3B, GETHER0 } },
1150         { INT2PRI47, 0, 32, 8, { DMINT12, DMINT13, DMINT14, DMINT15 } },
1151 };
1152
1153 static struct intc_sense_reg sense_registers_irq8to15[] __initdata = {
1154         { 0xffd100f8, 32, 2, /* ICR2 */   { IRQ15, IRQ14, IRQ13, IRQ12,
1155                                             IRQ11, IRQ10, IRQ9, IRQ8 } },
1156 };
1157
1158 static DECLARE_INTC_DESC(intc_desc, "sh7757", vectors, groups,
1159                          mask_registers, prio_registers,
1160                          sense_registers_irq8to15);
1161
1162 /* Support for external interrupt pins in IRQ mode */
1163 static struct intc_vect vectors_irq0123[] __initdata = {
1164         INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240),
1165         INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0),
1166 };
1167
1168 static struct intc_vect vectors_irq4567[] __initdata = {
1169         INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340),
1170         INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0),
1171 };
1172
1173 static struct intc_sense_reg sense_registers[] __initdata = {
1174         { 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
1175                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
1176 };
1177
1178 static struct intc_mask_reg ack_registers[] __initdata = {
1179         { 0xffd00024, 0, 32, /* INTREQ */
1180           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1181 };
1182
1183 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7757-irq0123",
1184                              vectors_irq0123, NULL, mask_registers,
1185                              prio_registers, sense_registers, ack_registers);
1186
1187 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7757-irq4567",
1188                              vectors_irq4567, NULL, mask_registers,
1189                              prio_registers, sense_registers, ack_registers);
1190
1191 /* External interrupt pins in IRL mode */
1192 static struct intc_vect vectors_irl0123[] __initdata = {
1193         INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
1194         INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
1195         INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
1196         INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
1197         INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
1198         INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
1199         INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
1200         INTC_VECT(IRL0_HHHL, 0x3c0),
1201 };
1202
1203 static struct intc_vect vectors_irl4567[] __initdata = {
1204         INTC_VECT(IRL4_LLLL, 0x200), INTC_VECT(IRL4_LLLH, 0x220),
1205         INTC_VECT(IRL4_LLHL, 0x240), INTC_VECT(IRL4_LLHH, 0x260),
1206         INTC_VECT(IRL4_LHLL, 0x280), INTC_VECT(IRL4_LHLH, 0x2a0),
1207         INTC_VECT(IRL4_LHHL, 0x2c0), INTC_VECT(IRL4_LHHH, 0x2e0),
1208         INTC_VECT(IRL4_HLLL, 0x300), INTC_VECT(IRL4_HLLH, 0x320),
1209         INTC_VECT(IRL4_HLHL, 0x340), INTC_VECT(IRL4_HLHH, 0x360),
1210         INTC_VECT(IRL4_HHLL, 0x380), INTC_VECT(IRL4_HHLH, 0x3a0),
1211         INTC_VECT(IRL4_HHHL, 0x3c0),
1212 };
1213
1214 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7757-irl0123", vectors_irl0123,
1215                          NULL, mask_registers, NULL, NULL);
1216
1217 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7757-irl4567", vectors_irl4567,
1218                          NULL, mask_registers, NULL, NULL);
1219
1220 #define INTC_ICR0       0xffd00000
1221 #define INTC_INTMSK0    0xffd00044
1222 #define INTC_INTMSK1    0xffd00048
1223 #define INTC_INTMSK2    0xffd40080
1224 #define INTC_INTMSKCLR1 0xffd00068
1225 #define INTC_INTMSKCLR2 0xffd40084
1226
1227 void __init plat_irq_setup(void)
1228 {
1229         /* disable IRQ3-0 + IRQ7-4 */
1230         __raw_writel(0xff000000, INTC_INTMSK0);
1231
1232         /* disable IRL3-0 + IRL7-4 */
1233         __raw_writel(0xc0000000, INTC_INTMSK1);
1234         __raw_writel(0xfffefffe, INTC_INTMSK2);
1235
1236         /* select IRL mode for IRL3-0 + IRL7-4 */
1237         __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
1238
1239         /* disable holding function, ie enable "SH-4 Mode" */
1240         __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
1241
1242         register_intc_controller(&intc_desc);
1243 }
1244
1245 void __init plat_irq_setup_pins(int mode)
1246 {
1247         switch (mode) {
1248         case IRQ_MODE_IRQ7654:
1249                 /* select IRQ mode for IRL7-4 */
1250                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
1251                 register_intc_controller(&intc_desc_irq4567);
1252                 break;
1253         case IRQ_MODE_IRQ3210:
1254                 /* select IRQ mode for IRL3-0 */
1255                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
1256                 register_intc_controller(&intc_desc_irq0123);
1257                 break;
1258         case IRQ_MODE_IRL7654:
1259                 /* enable IRL7-4 but don't provide any masking */
1260                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
1261                 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
1262                 break;
1263         case IRQ_MODE_IRL3210:
1264                 /* enable IRL0-3 but don't provide any masking */
1265                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
1266                 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
1267                 break;
1268         case IRQ_MODE_IRL7654_MASK:
1269                 /* enable IRL7-4 and mask using cpu intc controller */
1270                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
1271                 register_intc_controller(&intc_desc_irl4567);
1272                 break;
1273         case IRQ_MODE_IRL3210_MASK:
1274                 /* enable IRL0-3 and mask using cpu intc controller */
1275                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
1276                 register_intc_controller(&intc_desc_irl0123);
1277                 break;
1278         default:
1279                 BUG();
1280         }
1281 }
1282
1283 void __init plat_mem_setup(void)
1284 {
1285 }