4 * Copyright (C) 2009 Renesas Solutions Corp.
6 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
8 * Based on SH7723 Setup
9 * Copyright (C) 2008 Paul Mundt
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
15 #include <linux/platform_device.h>
16 #include <linux/init.h>
17 #include <linux/serial.h>
19 #include <linux/serial_sci.h>
20 #include <linux/uio_driver.h>
21 #include <linux/sh_dma.h>
22 #include <linux/sh_timer.h>
23 #include <linux/sh_intc.h>
25 #include <linux/notifier.h>
27 #include <asm/suspend.h>
28 #include <asm/clock.h>
29 #include <asm/mmzone.h>
31 #include <cpu/dma-register.h>
32 #include <cpu/sh7724.h>
35 static const struct sh_dmae_slave_config sh7724_dmae_slaves[] = {
37 .slave_id = SHDMA_SLAVE_SCIF0_TX,
39 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
42 .slave_id = SHDMA_SLAVE_SCIF0_RX,
44 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
47 .slave_id = SHDMA_SLAVE_SCIF1_TX,
49 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
52 .slave_id = SHDMA_SLAVE_SCIF1_RX,
54 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
57 .slave_id = SHDMA_SLAVE_SCIF2_TX,
59 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
62 .slave_id = SHDMA_SLAVE_SCIF2_RX,
64 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
67 .slave_id = SHDMA_SLAVE_SCIF3_TX,
69 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
72 .slave_id = SHDMA_SLAVE_SCIF3_RX,
74 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
77 .slave_id = SHDMA_SLAVE_SCIF4_TX,
79 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
82 .slave_id = SHDMA_SLAVE_SCIF4_RX,
84 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
87 .slave_id = SHDMA_SLAVE_SCIF5_TX,
89 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
92 .slave_id = SHDMA_SLAVE_SCIF5_RX,
94 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
97 .slave_id = SHDMA_SLAVE_USB0D0_TX,
99 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
102 .slave_id = SHDMA_SLAVE_USB0D0_RX,
104 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
107 .slave_id = SHDMA_SLAVE_USB0D1_TX,
109 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
112 .slave_id = SHDMA_SLAVE_USB0D1_RX,
114 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
117 .slave_id = SHDMA_SLAVE_USB1D0_TX,
119 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
122 .slave_id = SHDMA_SLAVE_USB1D0_RX,
124 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
127 .slave_id = SHDMA_SLAVE_USB1D1_TX,
129 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
132 .slave_id = SHDMA_SLAVE_USB1D1_RX,
134 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
137 .slave_id = SHDMA_SLAVE_SDHI0_TX,
139 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
142 .slave_id = SHDMA_SLAVE_SDHI0_RX,
144 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
147 .slave_id = SHDMA_SLAVE_SDHI1_TX,
149 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
152 .slave_id = SHDMA_SLAVE_SDHI1_RX,
154 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
159 static const struct sh_dmae_channel sh7724_dmae_channels[] = {
187 static const unsigned int ts_shift[] = TS_SHIFT;
189 static struct sh_dmae_pdata dma_platform_data = {
190 .slave = sh7724_dmae_slaves,
191 .slave_num = ARRAY_SIZE(sh7724_dmae_slaves),
192 .channel = sh7724_dmae_channels,
193 .channel_num = ARRAY_SIZE(sh7724_dmae_channels),
194 .ts_low_shift = CHCR_TS_LOW_SHIFT,
195 .ts_low_mask = CHCR_TS_LOW_MASK,
196 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
197 .ts_high_mask = CHCR_TS_HIGH_MASK,
198 .ts_shift = ts_shift,
199 .ts_shift_num = ARRAY_SIZE(ts_shift),
200 .dmaor_init = DMAOR_INIT,
203 /* Resource order important! */
204 static struct resource sh7724_dmae0_resources[] = {
206 /* Channel registers and DMAOR */
209 .flags = IORESOURCE_MEM,
215 .flags = IORESOURCE_MEM,
219 .start = evt2irq(0xbc0),
220 .end = evt2irq(0xbc0),
221 .flags = IORESOURCE_IRQ,
224 /* IRQ for channels 0-3 */
225 .start = evt2irq(0x800),
226 .end = evt2irq(0x860),
227 .flags = IORESOURCE_IRQ,
230 /* IRQ for channels 4-5 */
231 .start = evt2irq(0xb80),
232 .end = evt2irq(0xba0),
233 .flags = IORESOURCE_IRQ,
237 /* Resource order important! */
238 static struct resource sh7724_dmae1_resources[] = {
240 /* Channel registers and DMAOR */
243 .flags = IORESOURCE_MEM,
249 .flags = IORESOURCE_MEM,
253 .start = evt2irq(0xb40),
254 .end = evt2irq(0xb40),
255 .flags = IORESOURCE_IRQ,
258 /* IRQ for channels 0-3 */
259 .start = evt2irq(0x700),
260 .end = evt2irq(0x760),
261 .flags = IORESOURCE_IRQ,
264 /* IRQ for channels 4-5 */
265 .start = evt2irq(0xb00),
266 .end = evt2irq(0xb20),
267 .flags = IORESOURCE_IRQ,
271 static struct platform_device dma0_device = {
272 .name = "sh-dma-engine",
274 .resource = sh7724_dmae0_resources,
275 .num_resources = ARRAY_SIZE(sh7724_dmae0_resources),
277 .platform_data = &dma_platform_data,
281 static struct platform_device dma1_device = {
282 .name = "sh-dma-engine",
284 .resource = sh7724_dmae1_resources,
285 .num_resources = ARRAY_SIZE(sh7724_dmae1_resources),
287 .platform_data = &dma_platform_data,
292 static struct plat_sci_port scif0_platform_data = {
293 .port_reg = SCIx_NOT_SUPPORTED,
294 .flags = UPF_BOOT_AUTOCONF,
295 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
297 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
300 static struct resource scif0_resources[] = {
301 DEFINE_RES_MEM(0xffe00000, 0x100),
302 DEFINE_RES_IRQ(evt2irq(0xc00)),
305 static struct platform_device scif0_device = {
308 .resource = scif0_resources,
309 .num_resources = ARRAY_SIZE(scif0_resources),
311 .platform_data = &scif0_platform_data,
315 static struct plat_sci_port scif1_platform_data = {
316 .port_reg = SCIx_NOT_SUPPORTED,
317 .flags = UPF_BOOT_AUTOCONF,
318 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
320 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
323 static struct resource scif1_resources[] = {
324 DEFINE_RES_MEM(0xffe10000, 0x100),
325 DEFINE_RES_IRQ(evt2irq(0xc20)),
328 static struct platform_device scif1_device = {
331 .resource = scif1_resources,
332 .num_resources = ARRAY_SIZE(scif1_resources),
334 .platform_data = &scif1_platform_data,
338 static struct plat_sci_port scif2_platform_data = {
339 .port_reg = SCIx_NOT_SUPPORTED,
340 .flags = UPF_BOOT_AUTOCONF,
341 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
343 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
346 static struct resource scif2_resources[] = {
347 DEFINE_RES_MEM(0xffe20000, 0x100),
348 DEFINE_RES_IRQ(evt2irq(0xc40)),
351 static struct platform_device scif2_device = {
354 .resource = scif2_resources,
355 .num_resources = ARRAY_SIZE(scif2_resources),
357 .platform_data = &scif2_platform_data,
361 static struct plat_sci_port scif3_platform_data = {
362 .port_reg = SCIx_NOT_SUPPORTED,
363 .flags = UPF_BOOT_AUTOCONF,
364 .scscr = SCSCR_RE | SCSCR_TE,
369 static struct resource scif3_resources[] = {
370 DEFINE_RES_MEM(0xa4e30000, 0x100),
371 DEFINE_RES_IRQ(evt2irq(0x900)),
374 static struct platform_device scif3_device = {
377 .resource = scif3_resources,
378 .num_resources = ARRAY_SIZE(scif3_resources),
380 .platform_data = &scif3_platform_data,
384 static struct plat_sci_port scif4_platform_data = {
385 .port_reg = SCIx_NOT_SUPPORTED,
386 .flags = UPF_BOOT_AUTOCONF,
387 .scscr = SCSCR_RE | SCSCR_TE,
392 static struct resource scif4_resources[] = {
393 DEFINE_RES_MEM(0xa4e40000, 0x100),
394 DEFINE_RES_IRQ(evt2irq(0xd00)),
397 static struct platform_device scif4_device = {
400 .resource = scif4_resources,
401 .num_resources = ARRAY_SIZE(scif4_resources),
403 .platform_data = &scif4_platform_data,
407 static struct plat_sci_port scif5_platform_data = {
408 .port_reg = SCIx_NOT_SUPPORTED,
409 .flags = UPF_BOOT_AUTOCONF,
410 .scscr = SCSCR_RE | SCSCR_TE,
415 static struct resource scif5_resources[] = {
416 DEFINE_RES_MEM(0xa4e50000, 0x100),
417 DEFINE_RES_IRQ(evt2irq(0xfa0)),
420 static struct platform_device scif5_device = {
423 .resource = scif5_resources,
424 .num_resources = ARRAY_SIZE(scif5_resources),
426 .platform_data = &scif5_platform_data,
431 static struct resource rtc_resources[] = {
434 .end = 0xa465fec0 + 0x58 - 1,
435 .flags = IORESOURCE_IO,
439 .start = evt2irq(0xaa0),
440 .flags = IORESOURCE_IRQ,
444 .start = evt2irq(0xac0),
445 .flags = IORESOURCE_IRQ,
449 .start = evt2irq(0xa80),
450 .flags = IORESOURCE_IRQ,
454 static struct platform_device rtc_device = {
457 .num_resources = ARRAY_SIZE(rtc_resources),
458 .resource = rtc_resources,
462 static struct resource iic0_resources[] = {
466 .end = 0x04470018 - 1,
467 .flags = IORESOURCE_MEM,
470 .start = evt2irq(0xe00),
471 .end = evt2irq(0xe60),
472 .flags = IORESOURCE_IRQ,
476 static struct platform_device iic0_device = {
477 .name = "i2c-sh_mobile",
478 .id = 0, /* "i2c0" clock */
479 .num_resources = ARRAY_SIZE(iic0_resources),
480 .resource = iic0_resources,
484 static struct resource iic1_resources[] = {
488 .end = 0x04750018 - 1,
489 .flags = IORESOURCE_MEM,
492 .start = evt2irq(0xd80),
493 .end = evt2irq(0xde0),
494 .flags = IORESOURCE_IRQ,
498 static struct platform_device iic1_device = {
499 .name = "i2c-sh_mobile",
500 .id = 1, /* "i2c1" clock */
501 .num_resources = ARRAY_SIZE(iic1_resources),
502 .resource = iic1_resources,
506 static struct uio_info vpu_platform_data = {
509 .irq = evt2irq(0x980),
512 static struct resource vpu_resources[] = {
517 .flags = IORESOURCE_MEM,
520 /* place holder for contiguous memory */
524 static struct platform_device vpu_device = {
525 .name = "uio_pdrv_genirq",
528 .platform_data = &vpu_platform_data,
530 .resource = vpu_resources,
531 .num_resources = ARRAY_SIZE(vpu_resources),
535 static struct uio_info veu0_platform_data = {
538 .irq = evt2irq(0xc60),
541 static struct resource veu0_resources[] = {
546 .flags = IORESOURCE_MEM,
549 /* place holder for contiguous memory */
553 static struct platform_device veu0_device = {
554 .name = "uio_pdrv_genirq",
557 .platform_data = &veu0_platform_data,
559 .resource = veu0_resources,
560 .num_resources = ARRAY_SIZE(veu0_resources),
564 static struct uio_info veu1_platform_data = {
567 .irq = evt2irq(0x8c0),
570 static struct resource veu1_resources[] = {
575 .flags = IORESOURCE_MEM,
578 /* place holder for contiguous memory */
582 static struct platform_device veu1_device = {
583 .name = "uio_pdrv_genirq",
586 .platform_data = &veu1_platform_data,
588 .resource = veu1_resources,
589 .num_resources = ARRAY_SIZE(veu1_resources),
593 static struct uio_info beu0_platform_data = {
596 .irq = evt2irq(0x8A0),
599 static struct resource beu0_resources[] = {
604 .flags = IORESOURCE_MEM,
607 /* place holder for contiguous memory */
611 static struct platform_device beu0_device = {
612 .name = "uio_pdrv_genirq",
615 .platform_data = &beu0_platform_data,
617 .resource = beu0_resources,
618 .num_resources = ARRAY_SIZE(beu0_resources),
622 static struct uio_info beu1_platform_data = {
625 .irq = evt2irq(0xA00),
628 static struct resource beu1_resources[] = {
633 .flags = IORESOURCE_MEM,
636 /* place holder for contiguous memory */
640 static struct platform_device beu1_device = {
641 .name = "uio_pdrv_genirq",
644 .platform_data = &beu1_platform_data,
646 .resource = beu1_resources,
647 .num_resources = ARRAY_SIZE(beu1_resources),
650 static struct sh_timer_config cmt_platform_data = {
651 .channel_offset = 0x60,
653 .clockevent_rating = 125,
654 .clocksource_rating = 200,
657 static struct resource cmt_resources[] = {
661 .flags = IORESOURCE_MEM,
664 .start = evt2irq(0xf00),
665 .flags = IORESOURCE_IRQ,
669 static struct platform_device cmt_device = {
673 .platform_data = &cmt_platform_data,
675 .resource = cmt_resources,
676 .num_resources = ARRAY_SIZE(cmt_resources),
679 static struct sh_timer_config tmu0_platform_data = {
680 .channel_offset = 0x04,
682 .clockevent_rating = 200,
685 static struct resource tmu0_resources[] = {
689 .flags = IORESOURCE_MEM,
692 .start = evt2irq(0x400),
693 .flags = IORESOURCE_IRQ,
697 static struct platform_device tmu0_device = {
701 .platform_data = &tmu0_platform_data,
703 .resource = tmu0_resources,
704 .num_resources = ARRAY_SIZE(tmu0_resources),
707 static struct sh_timer_config tmu1_platform_data = {
708 .channel_offset = 0x10,
710 .clocksource_rating = 200,
713 static struct resource tmu1_resources[] = {
717 .flags = IORESOURCE_MEM,
720 .start = evt2irq(0x420),
721 .flags = IORESOURCE_IRQ,
725 static struct platform_device tmu1_device = {
729 .platform_data = &tmu1_platform_data,
731 .resource = tmu1_resources,
732 .num_resources = ARRAY_SIZE(tmu1_resources),
735 static struct sh_timer_config tmu2_platform_data = {
736 .channel_offset = 0x1c,
740 static struct resource tmu2_resources[] = {
744 .flags = IORESOURCE_MEM,
747 .start = evt2irq(0x440),
748 .flags = IORESOURCE_IRQ,
752 static struct platform_device tmu2_device = {
756 .platform_data = &tmu2_platform_data,
758 .resource = tmu2_resources,
759 .num_resources = ARRAY_SIZE(tmu2_resources),
763 static struct sh_timer_config tmu3_platform_data = {
764 .channel_offset = 0x04,
768 static struct resource tmu3_resources[] = {
772 .flags = IORESOURCE_MEM,
775 .start = evt2irq(0x920),
776 .flags = IORESOURCE_IRQ,
780 static struct platform_device tmu3_device = {
784 .platform_data = &tmu3_platform_data,
786 .resource = tmu3_resources,
787 .num_resources = ARRAY_SIZE(tmu3_resources),
790 static struct sh_timer_config tmu4_platform_data = {
791 .channel_offset = 0x10,
795 static struct resource tmu4_resources[] = {
799 .flags = IORESOURCE_MEM,
802 .start = evt2irq(0x940),
803 .flags = IORESOURCE_IRQ,
807 static struct platform_device tmu4_device = {
811 .platform_data = &tmu4_platform_data,
813 .resource = tmu4_resources,
814 .num_resources = ARRAY_SIZE(tmu4_resources),
817 static struct sh_timer_config tmu5_platform_data = {
818 .channel_offset = 0x1c,
822 static struct resource tmu5_resources[] = {
826 .flags = IORESOURCE_MEM,
829 .start = evt2irq(0x920),
830 .flags = IORESOURCE_IRQ,
834 static struct platform_device tmu5_device = {
838 .platform_data = &tmu5_platform_data,
840 .resource = tmu5_resources,
841 .num_resources = ARRAY_SIZE(tmu5_resources),
845 static struct uio_info jpu_platform_data = {
848 .irq = evt2irq(0x560),
851 static struct resource jpu_resources[] = {
856 .flags = IORESOURCE_MEM,
859 /* place holder for contiguous memory */
863 static struct platform_device jpu_device = {
864 .name = "uio_pdrv_genirq",
867 .platform_data = &jpu_platform_data,
869 .resource = jpu_resources,
870 .num_resources = ARRAY_SIZE(jpu_resources),
874 static struct uio_info spu0_platform_data = {
877 .irq = evt2irq(0xcc0),
880 static struct resource spu0_resources[] = {
885 .flags = IORESOURCE_MEM,
888 /* place holder for contiguous memory */
892 static struct platform_device spu0_device = {
893 .name = "uio_pdrv_genirq",
896 .platform_data = &spu0_platform_data,
898 .resource = spu0_resources,
899 .num_resources = ARRAY_SIZE(spu0_resources),
903 static struct uio_info spu1_platform_data = {
906 .irq = evt2irq(0xce0),
909 static struct resource spu1_resources[] = {
914 .flags = IORESOURCE_MEM,
917 /* place holder for contiguous memory */
921 static struct platform_device spu1_device = {
922 .name = "uio_pdrv_genirq",
925 .platform_data = &spu1_platform_data,
927 .resource = spu1_resources,
928 .num_resources = ARRAY_SIZE(spu1_resources),
931 static struct platform_device *sh7724_devices[] __initdata = {
960 static int __init sh7724_devices_setup(void)
962 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
963 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
964 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
965 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
966 platform_resource_setup_memory(&spu0_device, "spu0", 2 << 20);
967 platform_resource_setup_memory(&spu1_device, "spu1", 2 << 20);
969 return platform_add_devices(sh7724_devices,
970 ARRAY_SIZE(sh7724_devices));
972 arch_initcall(sh7724_devices_setup);
974 static struct platform_device *sh7724_early_devices[] __initdata = {
990 void __init plat_early_device_setup(void)
992 early_platform_add_devices(sh7724_early_devices,
993 ARRAY_SIZE(sh7724_early_devices));
996 #define RAMCR_CACHE_L2FC 0x0002
997 #define RAMCR_CACHE_L2E 0x0001
998 #define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC)
1000 void l2_cache_init(void)
1002 /* Enable L2 cache */
1003 __raw_writel(L2_CACHE_ENABLE, RAMCR);
1011 /* interrupt sources */
1012 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
1014 DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3,
1015 _2DG_TRI, _2DG_INI, _2DG_CEI,
1016 DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3,
1017 VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU,
1025 RTC_ATI, RTC_PRI, RTC_CUI,
1026 DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR,
1027 DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR,
1029 SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,
1031 MSIOF_MSIOFI0, MSIOF_MSIOFI1,
1032 SPU_SPUI0, SPU_SPUI1,
1036 I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
1037 I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
1042 TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
1046 MMC_MMC2I, MMC_MMC3I,
1048 TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2,
1050 /* interrupt groups */
1051 DMAC1A, _2DG, DMAC0A, VIO, USB, RTC,
1052 DMAC1B, DMAC0B, I2C0, I2C1, SDHI0, SDHI1, SPU, MMCIF,
1055 static struct intc_vect vectors[] __initdata = {
1056 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
1057 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
1058 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
1059 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
1061 INTC_VECT(DMAC1A_DEI0, 0x700),
1062 INTC_VECT(DMAC1A_DEI1, 0x720),
1063 INTC_VECT(DMAC1A_DEI2, 0x740),
1064 INTC_VECT(DMAC1A_DEI3, 0x760),
1066 INTC_VECT(_2DG_TRI, 0x780),
1067 INTC_VECT(_2DG_INI, 0x7A0),
1068 INTC_VECT(_2DG_CEI, 0x7C0),
1070 INTC_VECT(DMAC0A_DEI0, 0x800),
1071 INTC_VECT(DMAC0A_DEI1, 0x820),
1072 INTC_VECT(DMAC0A_DEI2, 0x840),
1073 INTC_VECT(DMAC0A_DEI3, 0x860),
1075 INTC_VECT(VIO_CEU0, 0x880),
1076 INTC_VECT(VIO_BEU0, 0x8A0),
1077 INTC_VECT(VIO_VEU1, 0x8C0),
1078 INTC_VECT(VIO_VOU, 0x8E0),
1080 INTC_VECT(SCIFA3, 0x900),
1081 INTC_VECT(VPU, 0x980),
1082 INTC_VECT(TPU, 0x9A0),
1083 INTC_VECT(CEU1, 0x9E0),
1084 INTC_VECT(BEU1, 0xA00),
1085 INTC_VECT(USB0, 0xA20),
1086 INTC_VECT(USB1, 0xA40),
1087 INTC_VECT(ATAPI, 0xA60),
1089 INTC_VECT(RTC_ATI, 0xA80),
1090 INTC_VECT(RTC_PRI, 0xAA0),
1091 INTC_VECT(RTC_CUI, 0xAC0),
1093 INTC_VECT(DMAC1B_DEI4, 0xB00),
1094 INTC_VECT(DMAC1B_DEI5, 0xB20),
1095 INTC_VECT(DMAC1B_DADERR, 0xB40),
1097 INTC_VECT(DMAC0B_DEI4, 0xB80),
1098 INTC_VECT(DMAC0B_DEI5, 0xBA0),
1099 INTC_VECT(DMAC0B_DADERR, 0xBC0),
1101 INTC_VECT(KEYSC, 0xBE0),
1102 INTC_VECT(SCIF_SCIF0, 0xC00),
1103 INTC_VECT(SCIF_SCIF1, 0xC20),
1104 INTC_VECT(SCIF_SCIF2, 0xC40),
1105 INTC_VECT(VEU0, 0xC60),
1106 INTC_VECT(MSIOF_MSIOFI0, 0xC80),
1107 INTC_VECT(MSIOF_MSIOFI1, 0xCA0),
1108 INTC_VECT(SPU_SPUI0, 0xCC0),
1109 INTC_VECT(SPU_SPUI1, 0xCE0),
1110 INTC_VECT(SCIFA4, 0xD00),
1112 INTC_VECT(ICB, 0xD20),
1113 INTC_VECT(ETHI, 0xD60),
1115 INTC_VECT(I2C1_ALI, 0xD80),
1116 INTC_VECT(I2C1_TACKI, 0xDA0),
1117 INTC_VECT(I2C1_WAITI, 0xDC0),
1118 INTC_VECT(I2C1_DTEI, 0xDE0),
1120 INTC_VECT(I2C0_ALI, 0xE00),
1121 INTC_VECT(I2C0_TACKI, 0xE20),
1122 INTC_VECT(I2C0_WAITI, 0xE40),
1123 INTC_VECT(I2C0_DTEI, 0xE60),
1125 INTC_VECT(SDHI0, 0xE80),
1126 INTC_VECT(SDHI0, 0xEA0),
1127 INTC_VECT(SDHI0, 0xEC0),
1128 INTC_VECT(SDHI0, 0xEE0),
1130 INTC_VECT(CMT, 0xF00),
1131 INTC_VECT(TSIF, 0xF20),
1132 INTC_VECT(FSI, 0xF80),
1133 INTC_VECT(SCIFA5, 0xFA0),
1135 INTC_VECT(TMU0_TUNI0, 0x400),
1136 INTC_VECT(TMU0_TUNI1, 0x420),
1137 INTC_VECT(TMU0_TUNI2, 0x440),
1139 INTC_VECT(IRDA, 0x480),
1141 INTC_VECT(SDHI1, 0x4E0),
1142 INTC_VECT(SDHI1, 0x500),
1143 INTC_VECT(SDHI1, 0x520),
1145 INTC_VECT(JPU, 0x560),
1146 INTC_VECT(_2DDMAC, 0x4A0),
1148 INTC_VECT(MMC_MMC2I, 0x5A0),
1149 INTC_VECT(MMC_MMC3I, 0x5C0),
1151 INTC_VECT(LCDC, 0xF40),
1153 INTC_VECT(TMU1_TUNI0, 0x920),
1154 INTC_VECT(TMU1_TUNI1, 0x940),
1155 INTC_VECT(TMU1_TUNI2, 0x960),
1158 static struct intc_group groups[] __initdata = {
1159 INTC_GROUP(DMAC1A, DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3),
1160 INTC_GROUP(_2DG, _2DG_TRI, _2DG_INI, _2DG_CEI),
1161 INTC_GROUP(DMAC0A, DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3),
1162 INTC_GROUP(VIO, VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU),
1163 INTC_GROUP(USB, USB0, USB1),
1164 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
1165 INTC_GROUP(DMAC1B, DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR),
1166 INTC_GROUP(DMAC0B, DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR),
1167 INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
1168 INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
1169 INTC_GROUP(SPU, SPU_SPUI0, SPU_SPUI1),
1170 INTC_GROUP(MMCIF, MMC_MMC2I, MMC_MMC3I),
1173 static struct intc_mask_reg mask_registers[] __initdata = {
1174 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
1175 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
1176 0, ENABLED, ENABLED, ENABLED } },
1177 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
1178 { VIO_VOU, VIO_VEU1, VIO_BEU0, VIO_CEU0,
1179 DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } },
1180 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
1181 { 0, 0, 0, VPU, ATAPI, ETHI, 0, SCIFA3 } },
1182 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
1183 { DMAC1A_DEI3, DMAC1A_DEI2, DMAC1A_DEI1, DMAC1A_DEI0,
1184 SPU_SPUI1, SPU_SPUI0, BEU1, IRDA } },
1185 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
1186 { 0, TMU0_TUNI2, TMU0_TUNI1, TMU0_TUNI0,
1187 JPU, 0, 0, LCDC } },
1188 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
1189 { KEYSC, DMAC0B_DADERR, DMAC0B_DEI5, DMAC0B_DEI4,
1190 VEU0, SCIF_SCIF2, SCIF_SCIF1, SCIF_SCIF0 } },
1191 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
1192 { 0, 0, ICB, SCIFA4,
1193 CEU1, 0, MSIOF_MSIOFI1, MSIOF_MSIOFI0 } },
1194 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
1195 { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
1196 I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } },
1197 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
1198 { DISABLED, ENABLED, ENABLED, ENABLED,
1199 0, 0, SCIFA5, FSI } },
1200 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
1201 { 0, 0, 0, CMT, 0, USB1, USB0, 0 } },
1202 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
1203 { 0, DMAC1B_DADERR, DMAC1B_DEI5, DMAC1B_DEI4,
1204 0, RTC_CUI, RTC_PRI, RTC_ATI } },
1205 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
1206 { 0, _2DG_CEI, _2DG_INI, _2DG_TRI,
1207 0, TPU, 0, TSIF } },
1208 { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
1209 { 0, 0, MMC_MMC3I, MMC_MMC2I, 0, 0, 0, _2DDMAC } },
1210 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
1211 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1214 static struct intc_prio_reg prio_registers[] __initdata = {
1215 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1,
1216 TMU0_TUNI2, IRDA } },
1217 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, DMAC1A, BEU1 } },
1218 { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1,
1219 TMU1_TUNI2, SPU } },
1220 { 0xa408000c, 0, 16, 4, /* IPRD */ { 0, MMCIF, 0, ATAPI } },
1221 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA3, VPU } },
1222 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC0B, USB, CMT } },
1223 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1,
1224 SCIF_SCIF2, VEU0 } },
1225 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0, MSIOF_MSIOFI1,
1227 { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA4, ICB, TSIF, _2DG } },
1228 { 0xa4080024, 0, 16, 4, /* IPRJ */ { CEU1, ETHI, FSI, SDHI1 } },
1229 { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC, DMAC1B, 0, SDHI0 } },
1230 { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA5, 0, TPU, _2DDMAC } },
1231 { 0xa4140010, 0, 32, 4, /* INTPRI00 */
1232 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1235 static struct intc_sense_reg sense_registers[] __initdata = {
1236 { 0xa414001c, 16, 2, /* ICR1 */
1237 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1240 static struct intc_mask_reg ack_registers[] __initdata = {
1241 { 0xa4140024, 0, 8, /* INTREQ00 */
1242 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1245 static struct intc_desc intc_desc __initdata = {
1247 .force_enable = ENABLED,
1248 .force_disable = DISABLED,
1249 .hw = INTC_HW_DESC(vectors, groups, mask_registers,
1250 prio_registers, sense_registers, ack_registers),
1253 void __init plat_irq_setup(void)
1255 register_intc_controller(&intc_desc);
1260 unsigned long mmselr;
1261 unsigned long cs0bcr;
1262 unsigned long cs4bcr;
1263 unsigned long cs5abcr;
1264 unsigned long cs5bbcr;
1265 unsigned long cs6abcr;
1266 unsigned long cs6bbcr;
1267 unsigned long cs4wcr;
1268 unsigned long cs5awcr;
1269 unsigned long cs5bwcr;
1270 unsigned long cs6awcr;
1271 unsigned long cs6bwcr;
1273 unsigned short ipra;
1274 unsigned short iprb;
1275 unsigned short iprc;
1276 unsigned short iprd;
1277 unsigned short ipre;
1278 unsigned short iprf;
1279 unsigned short iprg;
1280 unsigned short iprh;
1281 unsigned short ipri;
1282 unsigned short iprj;
1283 unsigned short iprk;
1284 unsigned short iprl;
1295 unsigned char imr10;
1296 unsigned char imr11;
1297 unsigned char imr12;
1299 unsigned short rwtcnt;
1300 unsigned short rwtcsr;
1302 unsigned long irdaclk;
1303 unsigned long spuclk;
1304 } sh7724_rstandby_state;
1306 static int sh7724_pre_sleep_notifier_call(struct notifier_block *nb,
1307 unsigned long flags, void *unused)
1309 if (!(flags & SUSP_SH_RSTANDBY))
1313 sh7724_rstandby_state.mmselr = __raw_readl(0xff800020); /* MMSELR */
1314 sh7724_rstandby_state.mmselr |= 0xa5a50000;
1315 sh7724_rstandby_state.cs0bcr = __raw_readl(0xfec10004); /* CS0BCR */
1316 sh7724_rstandby_state.cs4bcr = __raw_readl(0xfec10010); /* CS4BCR */
1317 sh7724_rstandby_state.cs5abcr = __raw_readl(0xfec10014); /* CS5ABCR */
1318 sh7724_rstandby_state.cs5bbcr = __raw_readl(0xfec10018); /* CS5BBCR */
1319 sh7724_rstandby_state.cs6abcr = __raw_readl(0xfec1001c); /* CS6ABCR */
1320 sh7724_rstandby_state.cs6bbcr = __raw_readl(0xfec10020); /* CS6BBCR */
1321 sh7724_rstandby_state.cs4wcr = __raw_readl(0xfec10030); /* CS4WCR */
1322 sh7724_rstandby_state.cs5awcr = __raw_readl(0xfec10034); /* CS5AWCR */
1323 sh7724_rstandby_state.cs5bwcr = __raw_readl(0xfec10038); /* CS5BWCR */
1324 sh7724_rstandby_state.cs6awcr = __raw_readl(0xfec1003c); /* CS6AWCR */
1325 sh7724_rstandby_state.cs6bwcr = __raw_readl(0xfec10040); /* CS6BWCR */
1328 sh7724_rstandby_state.ipra = __raw_readw(0xa4080000); /* IPRA */
1329 sh7724_rstandby_state.iprb = __raw_readw(0xa4080004); /* IPRB */
1330 sh7724_rstandby_state.iprc = __raw_readw(0xa4080008); /* IPRC */
1331 sh7724_rstandby_state.iprd = __raw_readw(0xa408000c); /* IPRD */
1332 sh7724_rstandby_state.ipre = __raw_readw(0xa4080010); /* IPRE */
1333 sh7724_rstandby_state.iprf = __raw_readw(0xa4080014); /* IPRF */
1334 sh7724_rstandby_state.iprg = __raw_readw(0xa4080018); /* IPRG */
1335 sh7724_rstandby_state.iprh = __raw_readw(0xa408001c); /* IPRH */
1336 sh7724_rstandby_state.ipri = __raw_readw(0xa4080020); /* IPRI */
1337 sh7724_rstandby_state.iprj = __raw_readw(0xa4080024); /* IPRJ */
1338 sh7724_rstandby_state.iprk = __raw_readw(0xa4080028); /* IPRK */
1339 sh7724_rstandby_state.iprl = __raw_readw(0xa408002c); /* IPRL */
1340 sh7724_rstandby_state.imr0 = __raw_readb(0xa4080080); /* IMR0 */
1341 sh7724_rstandby_state.imr1 = __raw_readb(0xa4080084); /* IMR1 */
1342 sh7724_rstandby_state.imr2 = __raw_readb(0xa4080088); /* IMR2 */
1343 sh7724_rstandby_state.imr3 = __raw_readb(0xa408008c); /* IMR3 */
1344 sh7724_rstandby_state.imr4 = __raw_readb(0xa4080090); /* IMR4 */
1345 sh7724_rstandby_state.imr5 = __raw_readb(0xa4080094); /* IMR5 */
1346 sh7724_rstandby_state.imr6 = __raw_readb(0xa4080098); /* IMR6 */
1347 sh7724_rstandby_state.imr7 = __raw_readb(0xa408009c); /* IMR7 */
1348 sh7724_rstandby_state.imr8 = __raw_readb(0xa40800a0); /* IMR8 */
1349 sh7724_rstandby_state.imr9 = __raw_readb(0xa40800a4); /* IMR9 */
1350 sh7724_rstandby_state.imr10 = __raw_readb(0xa40800a8); /* IMR10 */
1351 sh7724_rstandby_state.imr11 = __raw_readb(0xa40800ac); /* IMR11 */
1352 sh7724_rstandby_state.imr12 = __raw_readb(0xa40800b0); /* IMR12 */
1355 sh7724_rstandby_state.rwtcnt = __raw_readb(0xa4520000); /* RWTCNT */
1356 sh7724_rstandby_state.rwtcnt |= 0x5a00;
1357 sh7724_rstandby_state.rwtcsr = __raw_readb(0xa4520004); /* RWTCSR */
1358 sh7724_rstandby_state.rwtcsr |= 0xa500;
1359 __raw_writew(sh7724_rstandby_state.rwtcsr & 0x07, 0xa4520004);
1362 sh7724_rstandby_state.irdaclk = __raw_readl(0xa4150018); /* IRDACLKCR */
1363 sh7724_rstandby_state.spuclk = __raw_readl(0xa415003c); /* SPUCLKCR */
1368 static int sh7724_post_sleep_notifier_call(struct notifier_block *nb,
1369 unsigned long flags, void *unused)
1371 if (!(flags & SUSP_SH_RSTANDBY))
1375 __raw_writel(sh7724_rstandby_state.mmselr, 0xff800020); /* MMSELR */
1376 __raw_writel(sh7724_rstandby_state.cs0bcr, 0xfec10004); /* CS0BCR */
1377 __raw_writel(sh7724_rstandby_state.cs4bcr, 0xfec10010); /* CS4BCR */
1378 __raw_writel(sh7724_rstandby_state.cs5abcr, 0xfec10014); /* CS5ABCR */
1379 __raw_writel(sh7724_rstandby_state.cs5bbcr, 0xfec10018); /* CS5BBCR */
1380 __raw_writel(sh7724_rstandby_state.cs6abcr, 0xfec1001c); /* CS6ABCR */
1381 __raw_writel(sh7724_rstandby_state.cs6bbcr, 0xfec10020); /* CS6BBCR */
1382 __raw_writel(sh7724_rstandby_state.cs4wcr, 0xfec10030); /* CS4WCR */
1383 __raw_writel(sh7724_rstandby_state.cs5awcr, 0xfec10034); /* CS5AWCR */
1384 __raw_writel(sh7724_rstandby_state.cs5bwcr, 0xfec10038); /* CS5BWCR */
1385 __raw_writel(sh7724_rstandby_state.cs6awcr, 0xfec1003c); /* CS6AWCR */
1386 __raw_writel(sh7724_rstandby_state.cs6bwcr, 0xfec10040); /* CS6BWCR */
1389 __raw_writew(sh7724_rstandby_state.ipra, 0xa4080000); /* IPRA */
1390 __raw_writew(sh7724_rstandby_state.iprb, 0xa4080004); /* IPRB */
1391 __raw_writew(sh7724_rstandby_state.iprc, 0xa4080008); /* IPRC */
1392 __raw_writew(sh7724_rstandby_state.iprd, 0xa408000c); /* IPRD */
1393 __raw_writew(sh7724_rstandby_state.ipre, 0xa4080010); /* IPRE */
1394 __raw_writew(sh7724_rstandby_state.iprf, 0xa4080014); /* IPRF */
1395 __raw_writew(sh7724_rstandby_state.iprg, 0xa4080018); /* IPRG */
1396 __raw_writew(sh7724_rstandby_state.iprh, 0xa408001c); /* IPRH */
1397 __raw_writew(sh7724_rstandby_state.ipri, 0xa4080020); /* IPRI */
1398 __raw_writew(sh7724_rstandby_state.iprj, 0xa4080024); /* IPRJ */
1399 __raw_writew(sh7724_rstandby_state.iprk, 0xa4080028); /* IPRK */
1400 __raw_writew(sh7724_rstandby_state.iprl, 0xa408002c); /* IPRL */
1401 __raw_writeb(sh7724_rstandby_state.imr0, 0xa4080080); /* IMR0 */
1402 __raw_writeb(sh7724_rstandby_state.imr1, 0xa4080084); /* IMR1 */
1403 __raw_writeb(sh7724_rstandby_state.imr2, 0xa4080088); /* IMR2 */
1404 __raw_writeb(sh7724_rstandby_state.imr3, 0xa408008c); /* IMR3 */
1405 __raw_writeb(sh7724_rstandby_state.imr4, 0xa4080090); /* IMR4 */
1406 __raw_writeb(sh7724_rstandby_state.imr5, 0xa4080094); /* IMR5 */
1407 __raw_writeb(sh7724_rstandby_state.imr6, 0xa4080098); /* IMR6 */
1408 __raw_writeb(sh7724_rstandby_state.imr7, 0xa408009c); /* IMR7 */
1409 __raw_writeb(sh7724_rstandby_state.imr8, 0xa40800a0); /* IMR8 */
1410 __raw_writeb(sh7724_rstandby_state.imr9, 0xa40800a4); /* IMR9 */
1411 __raw_writeb(sh7724_rstandby_state.imr10, 0xa40800a8); /* IMR10 */
1412 __raw_writeb(sh7724_rstandby_state.imr11, 0xa40800ac); /* IMR11 */
1413 __raw_writeb(sh7724_rstandby_state.imr12, 0xa40800b0); /* IMR12 */
1416 __raw_writew(sh7724_rstandby_state.rwtcnt, 0xa4520000); /* RWTCNT */
1417 __raw_writew(sh7724_rstandby_state.rwtcsr, 0xa4520004); /* RWTCSR */
1420 __raw_writel(sh7724_rstandby_state.irdaclk, 0xa4150018); /* IRDACLKCR */
1421 __raw_writel(sh7724_rstandby_state.spuclk, 0xa415003c); /* SPUCLKCR */
1426 static struct notifier_block sh7724_pre_sleep_notifier = {
1427 .notifier_call = sh7724_pre_sleep_notifier_call,
1428 .priority = SH_MOBILE_PRE(SH_MOBILE_SLEEP_CPU),
1431 static struct notifier_block sh7724_post_sleep_notifier = {
1432 .notifier_call = sh7724_post_sleep_notifier_call,
1433 .priority = SH_MOBILE_POST(SH_MOBILE_SLEEP_CPU),
1436 static int __init sh7724_sleep_setup(void)
1438 atomic_notifier_chain_register(&sh_mobile_pre_sleep_notifier_list,
1439 &sh7724_pre_sleep_notifier);
1441 atomic_notifier_chain_register(&sh_mobile_post_sleep_notifier_list,
1442 &sh7724_post_sleep_notifier);
1445 arch_initcall(sh7724_sleep_setup);