4 * Copyright (C) 2006 - 2008 Paul Mundt
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/init.h>
12 #include <linux/platform_device.h>
13 #include <linux/serial.h>
14 #include <linux/serial_sci.h>
15 #include <linux/sh_dma.h>
16 #include <linux/sh_timer.h>
17 #include <linux/sh_intc.h>
18 #include <linux/uio_driver.h>
19 #include <linux/usb/m66592.h>
21 #include <asm/clock.h>
22 #include <asm/mmzone.h>
25 #include <cpu/dma-register.h>
26 #include <cpu/sh7722.h>
27 #include <cpu/serial.h>
29 static const struct sh_dmae_slave_config sh7722_dmae_slaves[] = {
31 .slave_id = SHDMA_SLAVE_SCIF0_TX,
33 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
36 .slave_id = SHDMA_SLAVE_SCIF0_RX,
38 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
41 .slave_id = SHDMA_SLAVE_SCIF1_TX,
43 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
46 .slave_id = SHDMA_SLAVE_SCIF1_RX,
48 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
51 .slave_id = SHDMA_SLAVE_SCIF2_TX,
53 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
56 .slave_id = SHDMA_SLAVE_SCIF2_RX,
58 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
61 .slave_id = SHDMA_SLAVE_SIUA_TX,
63 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
66 .slave_id = SHDMA_SLAVE_SIUA_RX,
68 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
71 .slave_id = SHDMA_SLAVE_SIUB_TX,
73 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
76 .slave_id = SHDMA_SLAVE_SIUB_RX,
78 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
81 .slave_id = SHDMA_SLAVE_SDHI0_TX,
83 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
86 .slave_id = SHDMA_SLAVE_SDHI0_RX,
88 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
93 static const struct sh_dmae_channel sh7722_dmae_channels[] = {
121 static const unsigned int ts_shift[] = TS_SHIFT;
123 static struct sh_dmae_pdata dma_platform_data = {
124 .slave = sh7722_dmae_slaves,
125 .slave_num = ARRAY_SIZE(sh7722_dmae_slaves),
126 .channel = sh7722_dmae_channels,
127 .channel_num = ARRAY_SIZE(sh7722_dmae_channels),
128 .ts_low_shift = CHCR_TS_LOW_SHIFT,
129 .ts_low_mask = CHCR_TS_LOW_MASK,
130 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
131 .ts_high_mask = CHCR_TS_HIGH_MASK,
132 .ts_shift = ts_shift,
133 .ts_shift_num = ARRAY_SIZE(ts_shift),
134 .dmaor_init = DMAOR_INIT,
137 static struct resource sh7722_dmae_resources[] = {
139 /* Channel registers and DMAOR */
142 .flags = IORESOURCE_MEM,
148 .flags = IORESOURCE_MEM,
152 .start = evt2irq(0xbc0),
153 .end = evt2irq(0xbc0),
154 .flags = IORESOURCE_IRQ,
157 /* IRQ for channels 0-3 */
158 .start = evt2irq(0x800),
159 .end = evt2irq(0x860),
160 .flags = IORESOURCE_IRQ,
163 /* IRQ for channels 4-5 */
164 .start = evt2irq(0xb80),
165 .end = evt2irq(0xba0),
166 .flags = IORESOURCE_IRQ,
170 struct platform_device dma_device = {
171 .name = "sh-dma-engine",
173 .resource = sh7722_dmae_resources,
174 .num_resources = ARRAY_SIZE(sh7722_dmae_resources),
176 .platform_data = &dma_platform_data,
181 static struct plat_sci_port scif0_platform_data = {
182 .flags = UPF_BOOT_AUTOCONF,
183 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
185 .ops = &sh7722_sci_port_ops,
186 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
189 static struct resource scif0_resources[] = {
190 DEFINE_RES_MEM(0xffe00000, 0x100),
191 DEFINE_RES_IRQ(evt2irq(0xc00)),
194 static struct platform_device scif0_device = {
197 .resource = scif0_resources,
198 .num_resources = ARRAY_SIZE(scif0_resources),
200 .platform_data = &scif0_platform_data,
204 static struct plat_sci_port scif1_platform_data = {
205 .flags = UPF_BOOT_AUTOCONF,
206 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
208 .ops = &sh7722_sci_port_ops,
209 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
212 static struct resource scif1_resources[] = {
213 DEFINE_RES_MEM(0xffe10000, 0x100),
214 DEFINE_RES_IRQ(evt2irq(0xc20)),
217 static struct platform_device scif1_device = {
220 .resource = scif1_resources,
221 .num_resources = ARRAY_SIZE(scif1_resources),
223 .platform_data = &scif1_platform_data,
227 static struct plat_sci_port scif2_platform_data = {
228 .flags = UPF_BOOT_AUTOCONF,
229 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
231 .ops = &sh7722_sci_port_ops,
232 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
235 static struct resource scif2_resources[] = {
236 DEFINE_RES_MEM(0xffe20000, 0x100),
237 DEFINE_RES_IRQ(evt2irq(0xc40)),
240 static struct platform_device scif2_device = {
243 .resource = scif2_resources,
244 .num_resources = ARRAY_SIZE(scif2_resources),
246 .platform_data = &scif2_platform_data,
250 static struct resource rtc_resources[] = {
253 .end = 0xa465fec0 + 0x58 - 1,
254 .flags = IORESOURCE_IO,
258 .start = evt2irq(0x7a0),
259 .flags = IORESOURCE_IRQ,
263 .start = evt2irq(0x7c0),
264 .flags = IORESOURCE_IRQ,
268 .start = evt2irq(0x780),
269 .flags = IORESOURCE_IRQ,
273 static struct platform_device rtc_device = {
276 .num_resources = ARRAY_SIZE(rtc_resources),
277 .resource = rtc_resources,
280 static struct m66592_platdata usbf_platdata = {
284 static struct resource usbf_resources[] = {
289 .flags = IORESOURCE_MEM,
292 .start = evt2irq(0xa20),
293 .end = evt2irq(0xa20),
294 .flags = IORESOURCE_IRQ,
298 static struct platform_device usbf_device = {
299 .name = "m66592_udc",
300 .id = 0, /* "usbf0" clock */
303 .coherent_dma_mask = 0xffffffff,
304 .platform_data = &usbf_platdata,
306 .num_resources = ARRAY_SIZE(usbf_resources),
307 .resource = usbf_resources,
310 static struct resource iic_resources[] = {
315 .flags = IORESOURCE_MEM,
318 .start = evt2irq(0xe00),
319 .end = evt2irq(0xe60),
320 .flags = IORESOURCE_IRQ,
324 static struct platform_device iic_device = {
325 .name = "i2c-sh_mobile",
326 .id = 0, /* "i2c0" clock */
327 .num_resources = ARRAY_SIZE(iic_resources),
328 .resource = iic_resources,
331 static struct uio_info vpu_platform_data = {
334 .irq = evt2irq(0x980),
337 static struct resource vpu_resources[] = {
342 .flags = IORESOURCE_MEM,
345 /* place holder for contiguous memory */
349 static struct platform_device vpu_device = {
350 .name = "uio_pdrv_genirq",
353 .platform_data = &vpu_platform_data,
355 .resource = vpu_resources,
356 .num_resources = ARRAY_SIZE(vpu_resources),
359 static struct uio_info veu_platform_data = {
362 .irq = evt2irq(0x8c0),
365 static struct resource veu_resources[] = {
370 .flags = IORESOURCE_MEM,
373 /* place holder for contiguous memory */
377 static struct platform_device veu_device = {
378 .name = "uio_pdrv_genirq",
381 .platform_data = &veu_platform_data,
383 .resource = veu_resources,
384 .num_resources = ARRAY_SIZE(veu_resources),
387 static struct uio_info jpu_platform_data = {
390 .irq = evt2irq(0x560),
393 static struct resource jpu_resources[] = {
398 .flags = IORESOURCE_MEM,
401 /* place holder for contiguous memory */
405 static struct platform_device jpu_device = {
406 .name = "uio_pdrv_genirq",
409 .platform_data = &jpu_platform_data,
411 .resource = jpu_resources,
412 .num_resources = ARRAY_SIZE(jpu_resources),
415 static struct sh_timer_config cmt_platform_data = {
416 .channel_offset = 0x60,
418 .clockevent_rating = 125,
419 .clocksource_rating = 125,
422 static struct resource cmt_resources[] = {
426 .flags = IORESOURCE_MEM,
429 .start = evt2irq(0xf00),
430 .flags = IORESOURCE_IRQ,
434 static struct platform_device cmt_device = {
438 .platform_data = &cmt_platform_data,
440 .resource = cmt_resources,
441 .num_resources = ARRAY_SIZE(cmt_resources),
444 static struct sh_timer_config tmu0_platform_data = {
445 .channel_offset = 0x04,
447 .clockevent_rating = 200,
450 static struct resource tmu0_resources[] = {
454 .flags = IORESOURCE_MEM,
457 .start = evt2irq(0x400),
458 .flags = IORESOURCE_IRQ,
462 static struct platform_device tmu0_device = {
466 .platform_data = &tmu0_platform_data,
468 .resource = tmu0_resources,
469 .num_resources = ARRAY_SIZE(tmu0_resources),
472 static struct sh_timer_config tmu1_platform_data = {
473 .channel_offset = 0x10,
475 .clocksource_rating = 200,
478 static struct resource tmu1_resources[] = {
482 .flags = IORESOURCE_MEM,
485 .start = evt2irq(0x420),
486 .flags = IORESOURCE_IRQ,
490 static struct platform_device tmu1_device = {
494 .platform_data = &tmu1_platform_data,
496 .resource = tmu1_resources,
497 .num_resources = ARRAY_SIZE(tmu1_resources),
500 static struct sh_timer_config tmu2_platform_data = {
501 .channel_offset = 0x1c,
505 static struct resource tmu2_resources[] = {
509 .flags = IORESOURCE_MEM,
513 .flags = IORESOURCE_IRQ,
517 static struct platform_device tmu2_device = {
521 .platform_data = &tmu2_platform_data,
523 .resource = tmu2_resources,
524 .num_resources = ARRAY_SIZE(tmu2_resources),
527 static struct siu_platform siu_platform_data = {
528 .dma_slave_tx_a = SHDMA_SLAVE_SIUA_TX,
529 .dma_slave_rx_a = SHDMA_SLAVE_SIUA_RX,
530 .dma_slave_tx_b = SHDMA_SLAVE_SIUB_TX,
531 .dma_slave_rx_b = SHDMA_SLAVE_SIUB_RX,
534 static struct resource siu_resources[] = {
538 .flags = IORESOURCE_MEM,
541 .start = evt2irq(0xf80),
542 .flags = IORESOURCE_IRQ,
546 static struct platform_device siu_device = {
547 .name = "siu-pcm-audio",
550 .platform_data = &siu_platform_data,
552 .resource = siu_resources,
553 .num_resources = ARRAY_SIZE(siu_resources),
556 static struct platform_device *sh7722_devices[] __initdata = {
574 static int __init sh7722_devices_setup(void)
576 platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
577 platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
578 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
580 return platform_add_devices(sh7722_devices,
581 ARRAY_SIZE(sh7722_devices));
583 arch_initcall(sh7722_devices_setup);
585 static struct platform_device *sh7722_early_devices[] __initdata = {
595 void __init plat_early_device_setup(void)
597 early_platform_add_devices(sh7722_early_devices,
598 ARRAY_SIZE(sh7722_early_devices));
606 /* interrupt sources */
607 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
609 SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
610 RTC_ATI, RTC_PRI, RTC_CUI,
611 DMAC0, DMAC1, DMAC2, DMAC3,
612 VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
614 USB_USBI0, USB_USBI1,
615 DMAC4, DMAC5, DMAC_DADERR,
617 SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO,
618 FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
619 I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
620 CMT, TSIF, SIU, TWODG,
624 /* interrupt groups */
625 SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI,
628 static struct intc_vect vectors[] __initdata = {
629 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
630 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
631 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
632 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
633 INTC_VECT(SIM_ERI, 0x700), INTC_VECT(SIM_RXI, 0x720),
634 INTC_VECT(SIM_TXI, 0x740), INTC_VECT(SIM_TEI, 0x760),
635 INTC_VECT(RTC_ATI, 0x780), INTC_VECT(RTC_PRI, 0x7a0),
636 INTC_VECT(RTC_CUI, 0x7c0),
637 INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
638 INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
639 INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
640 INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
641 INTC_VECT(VPU, 0x980), INTC_VECT(TPU, 0x9a0),
642 INTC_VECT(USB_USBI0, 0xa20), INTC_VECT(USB_USBI1, 0xa40),
643 INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
644 INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
645 INTC_VECT(SCIF0, 0xc00), INTC_VECT(SCIF1, 0xc20),
646 INTC_VECT(SCIF2, 0xc40), INTC_VECT(SIOF0, 0xc80),
647 INTC_VECT(SIOF1, 0xca0), INTC_VECT(SIO, 0xd00),
648 INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
649 INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
650 INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
651 INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
652 INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
653 INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
654 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
655 INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0),
656 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
657 INTC_VECT(TMU2, 0x440), INTC_VECT(IRDA, 0x480),
658 INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
661 static struct intc_group groups[] __initdata = {
662 INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
663 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
664 INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
665 INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
666 INTC_GROUP(USB, USB_USBI0, USB_USBI1),
667 INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
668 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
669 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
670 INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
673 static struct intc_mask_reg mask_registers[] __initdata = {
674 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
676 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
677 { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
678 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
680 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
681 { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
682 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
683 { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
684 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
685 { KEYSC, DMAC_DADERR, DMAC5, DMAC4, 0, SCIF2, SCIF1, SCIF0 } },
686 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
687 { 0, 0, 0, SIO, 0, 0, SIOF1, SIOF0 } },
688 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
689 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
690 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
691 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
692 { DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, TWODG, SIU } },
693 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
694 { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } },
695 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
697 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
698 { 0, RTC_CUI, RTC_PRI, RTC_ATI, 0, TPU, 0, TSIF } },
699 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
700 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
703 static struct intc_prio_reg prio_registers[] __initdata = {
704 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } },
705 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
706 { 0xa4080008, 0, 16, 4, /* IPRC */ { } },
707 { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
708 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } },
709 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
710 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } },
711 { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } },
712 { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } },
713 { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
714 { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } },
715 { 0xa408002c, 0, 16, 4, /* IPRL */ { TWODG, 0, TPU } },
716 { 0xa4140010, 0, 32, 4, /* INTPRI00 */
717 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
720 static struct intc_sense_reg sense_registers[] __initdata = {
721 { 0xa414001c, 16, 2, /* ICR1 */
722 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
725 static struct intc_mask_reg ack_registers[] __initdata = {
726 { 0xa4140024, 0, 8, /* INTREQ00 */
727 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
730 static struct intc_desc intc_desc __initdata = {
732 .force_enable = ENABLED,
733 .force_disable = DISABLED,
734 .hw = INTC_HW_DESC(vectors, groups, mask_registers,
735 prio_registers, sense_registers, ack_registers),
738 void __init plat_irq_setup(void)
740 register_intc_controller(&intc_desc);
743 void __init plat_mem_setup(void)
745 /* Register the URAM space as Node 1 */
746 setup_bootmem_node(1, 0x055f0000, 0x05610000);