4 * Copyright (C) 2008 Renesas Solutions
6 * Based on linux/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
12 #include <linux/platform_device.h>
13 #include <linux/init.h>
14 #include <linux/serial.h>
15 #include <linux/serial_sci.h>
16 #include <linux/uio_driver.h>
17 #include <linux/sh_timer.h>
18 #include <linux/sh_intc.h>
19 #include <linux/usb/r8a66597.h>
20 #include <asm/clock.h>
22 static struct plat_sci_port scif0_platform_data = {
23 .port_reg = 0xa405013e,
24 .flags = UPF_BOOT_AUTOCONF,
25 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
29 static struct resource scif0_resources[] = {
30 DEFINE_RES_MEM(0xffe00000, 0x100),
31 DEFINE_RES_IRQ(evt2irq(0xc00)),
34 static struct platform_device scif0_device = {
37 .resource = scif0_resources,
38 .num_resources = ARRAY_SIZE(scif0_resources),
40 .platform_data = &scif0_platform_data,
44 static struct resource iic_resources[] = {
49 .flags = IORESOURCE_MEM,
52 .start = evt2irq(0xe00),
53 .end = evt2irq(0xe60),
54 .flags = IORESOURCE_IRQ,
58 static struct platform_device iic_device = {
59 .name = "i2c-sh_mobile",
60 .id = 0, /* "i2c0" clock */
61 .num_resources = ARRAY_SIZE(iic_resources),
62 .resource = iic_resources,
65 static struct r8a66597_platdata r8a66597_data = {
69 static struct resource usb_host_resources[] = {
73 .flags = IORESOURCE_MEM,
76 .start = evt2irq(0xa20),
77 .end = evt2irq(0xa20),
78 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
82 static struct platform_device usb_host_device = {
83 .name = "r8a66597_hcd",
87 .coherent_dma_mask = 0xffffffff,
88 .platform_data = &r8a66597_data,
90 .num_resources = ARRAY_SIZE(usb_host_resources),
91 .resource = usb_host_resources,
94 static struct uio_info vpu_platform_data = {
97 .irq = evt2irq(0x980),
100 static struct resource vpu_resources[] = {
105 .flags = IORESOURCE_MEM,
108 /* place holder for contiguous memory */
112 static struct platform_device vpu_device = {
113 .name = "uio_pdrv_genirq",
116 .platform_data = &vpu_platform_data,
118 .resource = vpu_resources,
119 .num_resources = ARRAY_SIZE(vpu_resources),
122 static struct uio_info veu0_platform_data = {
125 .irq = evt2irq(0x8c0),
128 static struct resource veu0_resources[] = {
133 .flags = IORESOURCE_MEM,
136 /* place holder for contiguous memory */
140 static struct platform_device veu0_device = {
141 .name = "uio_pdrv_genirq",
144 .platform_data = &veu0_platform_data,
146 .resource = veu0_resources,
147 .num_resources = ARRAY_SIZE(veu0_resources),
150 static struct uio_info veu1_platform_data = {
153 .irq = evt2irq(0x560),
156 static struct resource veu1_resources[] = {
161 .flags = IORESOURCE_MEM,
164 /* place holder for contiguous memory */
168 static struct platform_device veu1_device = {
169 .name = "uio_pdrv_genirq",
172 .platform_data = &veu1_platform_data,
174 .resource = veu1_resources,
175 .num_resources = ARRAY_SIZE(veu1_resources),
178 static struct sh_timer_config cmt_platform_data = {
179 .channels_mask = 0x20,
182 static struct resource cmt_resources[] = {
183 DEFINE_RES_MEM(0x044a0000, 0x70),
184 DEFINE_RES_IRQ(evt2irq(0xf00)),
187 static struct platform_device cmt_device = {
191 .platform_data = &cmt_platform_data,
193 .resource = cmt_resources,
194 .num_resources = ARRAY_SIZE(cmt_resources),
197 static struct sh_timer_config tmu0_platform_data = {
198 .channel_offset = 0x04,
200 .clockevent_rating = 200,
203 static struct resource tmu0_resources[] = {
207 .flags = IORESOURCE_MEM,
211 .flags = IORESOURCE_IRQ,
215 static struct platform_device tmu0_device = {
219 .platform_data = &tmu0_platform_data,
221 .resource = tmu0_resources,
222 .num_resources = ARRAY_SIZE(tmu0_resources),
225 static struct sh_timer_config tmu1_platform_data = {
226 .channel_offset = 0x10,
228 .clocksource_rating = 200,
231 static struct resource tmu1_resources[] = {
235 .flags = IORESOURCE_MEM,
238 .start = evt2irq(0x420),
239 .flags = IORESOURCE_IRQ,
243 static struct platform_device tmu1_device = {
247 .platform_data = &tmu1_platform_data,
249 .resource = tmu1_resources,
250 .num_resources = ARRAY_SIZE(tmu1_resources),
253 static struct sh_timer_config tmu2_platform_data = {
254 .channel_offset = 0x1c,
258 static struct resource tmu2_resources[] = {
262 .flags = IORESOURCE_MEM,
265 .start = evt2irq(0x440),
266 .flags = IORESOURCE_IRQ,
270 static struct platform_device tmu2_device = {
274 .platform_data = &tmu2_platform_data,
276 .resource = tmu2_resources,
277 .num_resources = ARRAY_SIZE(tmu2_resources),
280 static struct platform_device *sh7366_devices[] __initdata = {
293 static int __init sh7366_devices_setup(void)
295 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
296 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
297 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
299 return platform_add_devices(sh7366_devices,
300 ARRAY_SIZE(sh7366_devices));
302 arch_initcall(sh7366_devices_setup);
304 static struct platform_device *sh7366_early_devices[] __initdata = {
312 void __init plat_early_device_setup(void)
314 early_platform_add_devices(sh7366_early_devices,
315 ARRAY_SIZE(sh7366_early_devices));
323 /* interrupt sources */
324 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
326 DMAC0, DMAC1, DMAC2, DMAC3,
327 VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
329 MMC_MMC1I, MMC_MMC2I, MMC_MMC3I,
330 DMAC4, DMAC5, DMAC_DADERR,
331 SCIF, SCIFA1, SCIFA2,
333 FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
334 I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
335 SDHI, CMT, TSIF, SIU,
339 /* interrupt groups */
341 DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C,
344 static struct intc_vect vectors[] __initdata = {
345 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
346 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
347 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
348 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
349 INTC_VECT(ICB, 0x700),
350 INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
351 INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
352 INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
353 INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
354 INTC_VECT(MFI, 0x900), INTC_VECT(VPU, 0x980), INTC_VECT(USB, 0xa20),
355 INTC_VECT(MMC_MMC1I, 0xb00), INTC_VECT(MMC_MMC2I, 0xb20),
356 INTC_VECT(MMC_MMC3I, 0xb40),
357 INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
358 INTC_VECT(DMAC_DADERR, 0xbc0),
359 INTC_VECT(SCIF, 0xc00), INTC_VECT(SCIFA1, 0xc20),
360 INTC_VECT(SCIFA2, 0xc40),
361 INTC_VECT(DENC, 0xc60), INTC_VECT(MSIOF, 0xc80),
362 INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
363 INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
364 INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
365 INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
366 INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
367 INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
368 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
369 INTC_VECT(SIU, 0xf80),
370 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
371 INTC_VECT(TMU2, 0x440),
372 INTC_VECT(VEU2, 0x560), INTC_VECT(LCDC, 0x580),
375 static struct intc_group groups[] __initdata = {
376 INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
377 INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
378 INTC_GROUP(MMC, MMC_MMC1I, MMC_MMC2I, MMC_MMC3I),
379 INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
380 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
381 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
382 INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
385 static struct intc_mask_reg mask_registers[] __initdata = {
386 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
388 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
389 { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
390 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
391 { 0, 0, 0, VPU, 0, 0, 0, MFI } },
392 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
394 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
395 { 0, TMU2, TMU1, TMU0, VEU2, 0, 0, LCDC } },
396 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
397 { 0, DMAC_DADERR, DMAC5, DMAC4, DENC, SCIFA2, SCIFA1, SCIF } },
398 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
399 { 0, 0, 0, 0, 0, 0, 0, MSIOF } },
400 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
401 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
402 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
403 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
404 { DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, 0, SIU } },
405 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
406 { 0, 0, 0, CMT, 0, USB, } },
407 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
408 { 0, MMC_MMC3I, MMC_MMC2I, MMC_MMC1I } },
409 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
410 { 0, 0, 0, 0, 0, 0, 0, TSIF } },
411 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
412 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
415 static struct intc_prio_reg prio_registers[] __initdata = {
416 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
417 { 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2, LCDC, ICB } },
418 { 0xa4080008, 0, 16, 4, /* IPRC */ { } },
419 { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
420 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, MFI, VPU } },
421 { 0xa4080014, 0, 16, 4, /* IPRF */ { 0, DMAC45, USB, CMT } },
422 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF, SCIFA1, SCIFA2, DENC } },
423 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF, 0, FLCTL, I2C } },
424 { 0xa4080020, 0, 16, 4, /* IPRI */ { 0, 0, TSIF, } },
425 { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
426 { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } },
427 { 0xa408002c, 0, 16, 4, /* IPRL */ { } },
428 { 0xa4140010, 0, 32, 4, /* INTPRI00 */
429 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
432 static struct intc_sense_reg sense_registers[] __initdata = {
433 { 0xa414001c, 16, 2, /* ICR1 */
434 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
437 static struct intc_mask_reg ack_registers[] __initdata = {
438 { 0xa4140024, 0, 8, /* INTREQ00 */
439 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
442 static struct intc_desc intc_desc __initdata = {
444 .force_enable = ENABLED,
445 .force_disable = DISABLED,
446 .hw = INTC_HW_DESC(vectors, groups, mask_registers,
447 prio_registers, sense_registers, ack_registers),
450 void __init plat_irq_setup(void)
452 register_intc_controller(&intc_desc);
455 void __init plat_mem_setup(void)
457 /* TODO: Register Node 1 */