arch/sh/kernel/cpu/sh4a/setup-sh7343.c

   1 /*
   2  * SH7343 Setup
   3  *
   4  *  Copyright (C) 2006  Paul Mundt
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/platform_device.h>
  11 #include <linux/init.h>
  12 #include <linux/serial.h>
  13 #include <linux/serial_sci.h>
  14 #include <linux/uio_driver.h>
  15 #include <linux/sh_timer.h>
  16 #include <linux/sh_intc.h>
  17 #include <asm/clock.h>
  18
  19 /* Serial */
  20 static struct plat_sci_port scif0_platform_data = {
  21         .flags          = UPF_BOOT_AUTOCONF,
  22         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
  23         .type           = PORT_SCIF,
  24 };
  25
  26 static struct resource scif0_resources[] = {
  27         DEFINE_RES_MEM(0xffe00000, 0x100),
  28         DEFINE_RES_IRQ(evt2irq(0xc00)),
  29 };
  30
  31 static struct platform_device scif0_device = {
  32         .name           = "sh-sci",
  33         .id             = 0,
  34         .resource       = scif0_resources,
  35         .num_resources  = ARRAY_SIZE(scif0_resources),
  36         .dev            = {
  37                 .platform_data  = &scif0_platform_data,
  38         },
  39 };
  40
  41 static struct plat_sci_port scif1_platform_data = {
  42         .flags          = UPF_BOOT_AUTOCONF,
  43         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
  44         .type           = PORT_SCIF,
  45 };
  46
  47 static struct resource scif1_resources[] = {
  48         DEFINE_RES_MEM(0xffe10000, 0x100),
  49         DEFINE_RES_IRQ(evt2irq(0xc20)),
  50 };
  51
  52 static struct platform_device scif1_device = {
  53         .name           = "sh-sci",
  54         .id             = 1,
  55         .resource       = scif1_resources,
  56         .num_resources  = ARRAY_SIZE(scif1_resources),
  57         .dev            = {
  58                 .platform_data  = &scif1_platform_data,
  59         },
  60 };
  61
  62 static struct plat_sci_port scif2_platform_data = {
  63         .flags          = UPF_BOOT_AUTOCONF,
  64         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
  65         .type           = PORT_SCIF,
  66 };
  67
  68 static struct resource scif2_resources[] = {
  69         DEFINE_RES_MEM(0xffe20000, 0x100),
  70         DEFINE_RES_IRQ(evt2irq(0xc40)),
  71 };
  72
  73 static struct platform_device scif2_device = {
  74         .name           = "sh-sci",
  75         .id             = 2,
  76         .resource       = scif2_resources,
  77         .num_resources  = ARRAY_SIZE(scif2_resources),
  78         .dev            = {
  79                 .platform_data  = &scif2_platform_data,
  80         },
  81 };
  82
  83 static struct plat_sci_port scif3_platform_data = {
  84         .flags          = UPF_BOOT_AUTOCONF,
  85         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
  86         .type           = PORT_SCIF,
  87 };
  88
  89 static struct resource scif3_resources[] = {
  90         DEFINE_RES_MEM(0xffe30000, 0x100),
  91         DEFINE_RES_IRQ(evt2irq(0xc60)),
  92 };
  93
  94 static struct platform_device scif3_device = {
  95         .name           = "sh-sci",
  96         .id             = 3,
  97         .resource       = scif3_resources,
  98         .num_resources  = ARRAY_SIZE(scif3_resources),
  99         .dev            = {
 100                 .platform_data  = &scif3_platform_data,
 101         },
 102 };
 103
 104 static struct resource iic0_resources[] = {
 105         [0] = {
 106                 .name   = "IIC0",
 107                 .start  = 0x04470000,
 108                 .end    = 0x04470017,
 109                 .flags  = IORESOURCE_MEM,
 110         },
 111         [1] = {
 112                 .start  = evt2irq(0xe00),
 113                 .end    = evt2irq(0xe60),
 114                 .flags  = IORESOURCE_IRQ,
 115        },
 116 };
 117
 118 static struct platform_device iic0_device = {
 119         .name           = "i2c-sh_mobile",
 120         .id             = 0, /* "i2c0" clock */
 121         .num_resources  = ARRAY_SIZE(iic0_resources),
 122         .resource       = iic0_resources,
 123 };
 124
 125 static struct resource iic1_resources[] = {
 126         [0] = {
 127                 .name   = "IIC1",
 128                 .start  = 0x04750000,
 129                 .end    = 0x04750017,
 130                 .flags  = IORESOURCE_MEM,
 131         },
 132         [1] = {
 133                 .start  = evt2irq(0x780),
 134                 .end    = evt2irq(0x7e0),
 135                 .flags  = IORESOURCE_IRQ,
 136        },
 137 };
 138
 139 static struct platform_device iic1_device = {
 140         .name           = "i2c-sh_mobile",
 141         .id             = 1, /* "i2c1" clock */
 142         .num_resources  = ARRAY_SIZE(iic1_resources),
 143         .resource       = iic1_resources,
 144 };
 145
 146 static struct uio_info vpu_platform_data = {
 147         .name = "VPU4",
 148         .version = "0",
 149         .irq = evt2irq(0x980),
 150 };
 151
 152 static struct resource vpu_resources[] = {
 153         [0] = {
 154                 .name   = "VPU",
 155                 .start  = 0xfe900000,
 156                 .end    = 0xfe9022eb,
 157                 .flags  = IORESOURCE_MEM,
 158         },
 159         [1] = {
 160                 /* place holder for contiguous memory */
 161         },
 162 };
 163
 164 static struct platform_device vpu_device = {
 165         .name           = "uio_pdrv_genirq",
 166         .id             = 0,
 167         .dev = {
 168                 .platform_data  = &vpu_platform_data,
 169         },
 170         .resource       = vpu_resources,
 171         .num_resources  = ARRAY_SIZE(vpu_resources),
 172 };
 173
 174 static struct uio_info veu_platform_data = {
 175         .name = "VEU",
 176         .version = "0",
 177         .irq = evt2irq(0x8c0),
 178 };
 179
 180 static struct resource veu_resources[] = {
 181         [0] = {
 182                 .name   = "VEU",
 183                 .start  = 0xfe920000,
 184                 .end    = 0xfe9200b7,
 185                 .flags  = IORESOURCE_MEM,
 186         },
 187         [1] = {
 188                 /* place holder for contiguous memory */
 189         },
 190 };
 191
 192 static struct platform_device veu_device = {
 193         .name           = "uio_pdrv_genirq",
 194         .id             = 1,
 195         .dev = {
 196                 .platform_data  = &veu_platform_data,
 197         },
 198         .resource       = veu_resources,
 199         .num_resources  = ARRAY_SIZE(veu_resources),
 200 };
 201
 202 static struct uio_info jpu_platform_data = {
 203         .name = "JPU",
 204         .version = "0",
 205         .irq = evt2irq(0x560),
 206 };
 207
 208 static struct resource jpu_resources[] = {
 209         [0] = {
 210                 .name   = "JPU",
 211                 .start  = 0xfea00000,
 212                 .end    = 0xfea102d3,
 213                 .flags  = IORESOURCE_MEM,
 214         },
 215         [1] = {
 216                 /* place holder for contiguous memory */
 217         },
 218 };
 219
 220 static struct platform_device jpu_device = {
 221         .name           = "uio_pdrv_genirq",
 222         .id             = 2,
 223         .dev = {
 224                 .platform_data  = &jpu_platform_data,
 225         },
 226         .resource       = jpu_resources,
 227         .num_resources  = ARRAY_SIZE(jpu_resources),
 228 };
 229
 230 static struct sh_timer_config cmt_platform_data = {
 231         .channel_offset = 0x60,
 232         .timer_bit = 5,
 233         .clockevent_rating = 125,
 234         .clocksource_rating = 200,
 235 };
 236
 237 static struct resource cmt_resources[] = {
 238         [0] = {
 239                 .start  = 0x044a0060,
 240                 .end    = 0x044a006b,
 241                 .flags  = IORESOURCE_MEM,
 242         },
 243         [1] = {
 244                 .start  = evt2irq(0xf00),
 245                 .flags  = IORESOURCE_IRQ,
 246         },
 247 };
 248
 249 static struct platform_device cmt_device = {
 250         .name           = "sh_cmt",
 251         .id             = 0,
 252         .dev = {
 253                 .platform_data  = &cmt_platform_data,
 254         },
 255         .resource       = cmt_resources,
 256         .num_resources  = ARRAY_SIZE(cmt_resources),
 257 };
 258
 259 static struct sh_timer_config tmu0_platform_data = {
 260         .channel_offset = 0x04,
 261         .timer_bit = 0,
 262         .clockevent_rating = 200,
 263 };
 264
 265 static struct resource tmu0_resources[] = {
 266         [0] = {
 267                 .start  = 0xffd80008,
 268                 .end    = 0xffd80013,
 269                 .flags  = IORESOURCE_MEM,
 270         },
 271         [1] = {
 272                 .start  = evt2irq(0x400),
 273                 .flags  = IORESOURCE_IRQ,
 274         },
 275 };
 276
 277 static struct platform_device tmu0_device = {
 278         .name           = "sh_tmu",
 279         .id             = 0,
 280         .dev = {
 281                 .platform_data  = &tmu0_platform_data,
 282         },
 283         .resource       = tmu0_resources,
 284         .num_resources  = ARRAY_SIZE(tmu0_resources),
 285 };
 286
 287 static struct sh_timer_config tmu1_platform_data = {
 288         .channel_offset = 0x10,
 289         .timer_bit = 1,
 290         .clocksource_rating = 200,
 291 };
 292
 293 static struct resource tmu1_resources[] = {
 294         [0] = {
 295                 .start  = 0xffd80014,
 296                 .end    = 0xffd8001f,
 297                 .flags  = IORESOURCE_MEM,
 298         },
 299         [1] = {
 300                 .start  = evt2irq(0x420),
 301                 .flags  = IORESOURCE_IRQ,
 302         },
 303 };
 304
 305 static struct platform_device tmu1_device = {
 306         .name           = "sh_tmu",
 307         .id             = 1,
 308         .dev = {
 309                 .platform_data  = &tmu1_platform_data,
 310         },
 311         .resource       = tmu1_resources,
 312         .num_resources  = ARRAY_SIZE(tmu1_resources),
 313 };
 314
 315 static struct sh_timer_config tmu2_platform_data = {
 316         .channel_offset = 0x1c,
 317         .timer_bit = 2,
 318 };
 319
 320 static struct resource tmu2_resources[] = {
 321         [0] = {
 322                 .start  = 0xffd80020,
 323                 .end    = 0xffd8002b,
 324                 .flags  = IORESOURCE_MEM,
 325         },
 326         [1] = {
 327                 .start  = evt2irq(0x440),
 328                 .flags  = IORESOURCE_IRQ,
 329         },
 330 };
 331
 332 static struct platform_device tmu2_device = {
 333         .name           = "sh_tmu",
 334         .id             = 2,
 335         .dev = {
 336                 .platform_data  = &tmu2_platform_data,
 337         },
 338         .resource       = tmu2_resources,
 339         .num_resources  = ARRAY_SIZE(tmu2_resources),
 340 };
 341
 342 static struct platform_device *sh7343_devices[] __initdata = {
 343         &scif0_device,
 344         &scif1_device,
 345         &scif2_device,
 346         &scif3_device,
 347         &cmt_device,
 348         &tmu0_device,
 349         &tmu1_device,
 350         &tmu2_device,
 351         &iic0_device,
 352         &iic1_device,
 353         &vpu_device,
 354         &veu_device,
 355         &jpu_device,
 356 };
 357
 358 static int __init sh7343_devices_setup(void)
 359 {
 360         platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
 361         platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
 362         platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
 363
 364         return platform_add_devices(sh7343_devices,
 365                                     ARRAY_SIZE(sh7343_devices));
 366 }
 367 arch_initcall(sh7343_devices_setup);
 368
 369 static struct platform_device *sh7343_early_devices[] __initdata = {
 370         &scif0_device,
 371         &scif1_device,
 372         &scif2_device,
 373         &scif3_device,
 374         &cmt_device,
 375         &tmu0_device,
 376         &tmu1_device,
 377         &tmu2_device,
 378 };
 379
 380 void __init plat_early_device_setup(void)
 381 {
 382         early_platform_add_devices(sh7343_early_devices,
 383                                    ARRAY_SIZE(sh7343_early_devices));
 384 }
 385
 386 enum {
 387         UNUSED = 0,
 388         ENABLED,
 389         DISABLED,
 390
 391         /* interrupt sources */
 392         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 393         DMAC0, DMAC1, DMAC2, DMAC3,
 394         VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
 395         MFI, VPU, TPU, Z3D4, USBI0, USBI1,
 396         MMC_ERR, MMC_TRAN, MMC_FSTAT, MMC_FRDY,
 397         DMAC4, DMAC5, DMAC_DADERR,
 398         KEYSC,
 399         SCIF, SCIF1, SCIF2, SCIF3,
 400         SIOF0, SIOF1, SIO,
 401         FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
 402         I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
 403         I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
 404         SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI,
 405         IRDA, SDHI, CMT, TSIF, SIU,
 406         TMU0, TMU1, TMU2,
 407         JPU, LCDC,
 408
 409         /* interrupt groups */
 410
 411         DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C0, I2C1, SIM, USB,
 412 };
 413
 414 static struct intc_vect vectors[] __initdata = {
 415         INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
 416         INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
 417         INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
 418         INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
 419         INTC_VECT(I2C1_ALI, 0x780), INTC_VECT(I2C1_TACKI, 0x7a0),
 420         INTC_VECT(I2C1_WAITI, 0x7c0), INTC_VECT(I2C1_DTEI, 0x7e0),
 421         INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
 422         INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
 423         INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
 424         INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
 425         INTC_VECT(MFI, 0x900), INTC_VECT(VPU, 0x980),
 426         INTC_VECT(TPU, 0x9a0), INTC_VECT(Z3D4, 0x9e0),
 427         INTC_VECT(USBI0, 0xa20), INTC_VECT(USBI1, 0xa40),
 428         INTC_VECT(MMC_ERR, 0xb00), INTC_VECT(MMC_TRAN, 0xb20),
 429         INTC_VECT(MMC_FSTAT, 0xb40), INTC_VECT(MMC_FRDY, 0xb60),
 430         INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
 431         INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
 432         INTC_VECT(SCIF, 0xc00), INTC_VECT(SCIF1, 0xc20),
 433         INTC_VECT(SCIF2, 0xc40), INTC_VECT(SCIF3, 0xc60),
 434         INTC_VECT(SIOF0, 0xc80), INTC_VECT(SIOF1, 0xca0),
 435         INTC_VECT(SIO, 0xd00),
 436         INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
 437         INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
 438         INTC_VECT(I2C0_ALI, 0xe00), INTC_VECT(I2C0_TACKI, 0xe20),
 439         INTC_VECT(I2C0_WAITI, 0xe40), INTC_VECT(I2C0_DTEI, 0xe60),
 440         INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
 441         INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
 442         INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
 443         INTC_VECT(SIU, 0xf80),
 444         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
 445         INTC_VECT(TMU2, 0x440),
 446         INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
 447 };
 448
 449 static struct intc_group groups[] __initdata = {
 450         INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
 451         INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
 452         INTC_GROUP(MMC, MMC_FRDY, MMC_FSTAT, MMC_TRAN, MMC_ERR),
 453         INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
 454         INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
 455                    FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
 456         INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
 457         INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
 458         INTC_GROUP(SIM, SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI),
 459         INTC_GROUP(USB, USBI0, USBI1),
 460 };
 461
 462 static struct intc_mask_reg mask_registers[] __initdata = {
 463         { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
 464           { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
 465         { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
 466           { 0, 0, 0, VPU, 0, 0, 0, MFI } },
 467         { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
 468           { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
 469         { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
 470           { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
 471         { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
 472           { KEYSC, DMAC_DADERR, DMAC5, DMAC4, SCIF3, SCIF2, SCIF1, SCIF } },
 473         { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
 474           { 0, 0, 0, SIO, Z3D4, 0, SIOF1, SIOF0 } },
 475         { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
 476           { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
 477             FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
 478         { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
 479           { DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, 0, SIU } },
 480         { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
 481           { 0, 0, 0, CMT, 0, USBI1, USBI0 } },
 482         { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
 483           { MMC_FRDY, MMC_FSTAT, MMC_TRAN, MMC_ERR } },
 484         { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
 485           { I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI, TPU, 0, 0, TSIF } },
 486         { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
 487           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 488 };
 489
 490 static struct intc_prio_reg prio_registers[] __initdata = {
 491         { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
 492         { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
 493         { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, MFI, VPU } },
 494         { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
 495         { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF, SCIF1, SCIF2, SCIF3 } },
 496         { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C0 } },
 497         { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, I2C1 } },
 498         { 0xa4080024, 0, 16, 4, /* IPRJ */ { Z3D4, 0, SIU } },
 499         { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } },
 500         { 0xa408002c, 0, 16, 4, /* IPRL */ { 0, 0, TPU } },
 501         { 0xa4140010, 0, 32, 4, /* INTPRI00 */
 502           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 503 };
 504
 505 static struct intc_sense_reg sense_registers[] __initdata = {
 506         { 0xa414001c, 16, 2, /* ICR1 */
 507           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 508 };
 509
 510 static struct intc_mask_reg ack_registers[] __initdata = {
 511         { 0xa4140024, 0, 8, /* INTREQ00 */
 512           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 513 };
 514
 515 static struct intc_desc intc_desc __initdata = {
 516         .name = "sh7343",
 517         .force_enable = ENABLED,
 518         .force_disable = DISABLED,
 519         .hw = INTC_HW_DESC(vectors, groups, mask_registers,
 520                            prio_registers, sense_registers, ack_registers),
 521 };
 522
 523 void __init plat_irq_setup(void)
 524 {
 525         register_intc_controller(&intc_desc);
 526 }