arch/sh/kernel/cpu/sh4/setup-sh7750.c

   1 /*
   2  * SH7091/SH7750/SH7750S/SH7750R/SH7751/SH7751R Setup
   3  *
   4  *  Copyright (C) 2006  Paul Mundt
   5  *  Copyright (C) 2006  Jamie Lenehan
   6  *
   7  * This file is subject to the terms and conditions of the GNU General Public
   8  * License.  See the file "COPYING" in the main directory of this archive
   9  * for more details.
  10  */
  11 #include <linux/platform_device.h>
  12 #include <linux/init.h>
  13 #include <linux/serial.h>
  14 #include <linux/io.h>
  15 #include <linux/sh_timer.h>
  16 #include <linux/sh_intc.h>
  17 #include <linux/serial_sci.h>
  18 #include <generated/machtypes.h>
  19
  20 static struct resource rtc_resources[] = {
  21         [0] = {
  22                 .start  = 0xffc80000,
  23                 .end    = 0xffc80000 + 0x58 - 1,
  24                 .flags  = IORESOURCE_IO,
  25         },
  26         [1] = {
  27                 /* Shared Period/Carry/Alarm IRQ */
  28                 .start  = evt2irq(0x480),
  29                 .flags  = IORESOURCE_IRQ,
  30         },
  31 };
  32
  33 static struct platform_device rtc_device = {
  34         .name           = "sh-rtc",
  35         .id             = -1,
  36         .num_resources  = ARRAY_SIZE(rtc_resources),
  37         .resource       = rtc_resources,
  38 };
  39
  40 static struct plat_sci_port sci_platform_data = {
  41         .port_reg       = 0xffe0001C,
  42         .flags          = UPF_BOOT_AUTOCONF,
  43         .scscr          = SCSCR_TE | SCSCR_RE,
  44         .type           = PORT_SCI,
  45         .regshift       = 2,
  46 };
  47
  48 static struct resource sci_resources[] = {
  49         DEFINE_RES_MEM(0xffe00000, 0x100),
  50         DEFINE_RES_IRQ(evt2irq(0x4e0)),
  51 };
  52
  53 static struct platform_device sci_device = {
  54         .name           = "sh-sci",
  55         .id             = 0,
  56         .resource       = sci_resources,
  57         .num_resources  = ARRAY_SIZE(sci_resources),
  58         .dev            = {
  59                 .platform_data  = &sci_platform_data,
  60         },
  61 };
  62
  63 static struct plat_sci_port scif_platform_data = {
  64         .flags          = UPF_BOOT_AUTOCONF,
  65         .scscr          = SCSCR_TE | SCSCR_RE | SCSCR_REIE,
  66         .type           = PORT_SCIF,
  67 };
  68
  69 static struct resource scif_resources[] = {
  70         DEFINE_RES_MEM(0xffe80000, 0x100),
  71         DEFINE_RES_IRQ(evt2irq(0x700)),
  72 };
  73
  74 static struct platform_device scif_device = {
  75         .name           = "sh-sci",
  76         .id             = 1,
  77         .resource       = scif_resources,
  78         .num_resources  = ARRAY_SIZE(scif_resources),
  79         .dev            = {
  80                 .platform_data  = &scif_platform_data,
  81         },
  82 };
  83
  84 static struct sh_timer_config tmu0_platform_data = {
  85         .channel_offset = 0x04,
  86         .timer_bit = 0,
  87         .clockevent_rating = 200,
  88 };
  89
  90 static struct resource tmu0_resources[] = {
  91         [0] = {
  92                 .start  = 0xffd80008,
  93                 .end    = 0xffd80013,
  94                 .flags  = IORESOURCE_MEM,
  95         },
  96         [1] = {
  97                 .start  = evt2irq(0x400),
  98                 .flags  = IORESOURCE_IRQ,
  99         },
 100 };
 101
 102 static struct platform_device tmu0_device = {
 103         .name           = "sh_tmu",
 104         .id             = 0,
 105         .dev = {
 106                 .platform_data  = &tmu0_platform_data,
 107         },
 108         .resource       = tmu0_resources,
 109         .num_resources  = ARRAY_SIZE(tmu0_resources),
 110 };
 111
 112 static struct sh_timer_config tmu1_platform_data = {
 113         .channel_offset = 0x10,
 114         .timer_bit = 1,
 115         .clocksource_rating = 200,
 116 };
 117
 118 static struct resource tmu1_resources[] = {
 119         [0] = {
 120                 .start  = 0xffd80014,
 121                 .end    = 0xffd8001f,
 122                 .flags  = IORESOURCE_MEM,
 123         },
 124         [1] = {
 125                 .start  = evt2irq(0x420),
 126                 .flags  = IORESOURCE_IRQ,
 127         },
 128 };
 129
 130 static struct platform_device tmu1_device = {
 131         .name           = "sh_tmu",
 132         .id             = 1,
 133         .dev = {
 134                 .platform_data  = &tmu1_platform_data,
 135         },
 136         .resource       = tmu1_resources,
 137         .num_resources  = ARRAY_SIZE(tmu1_resources),
 138 };
 139
 140 static struct sh_timer_config tmu2_platform_data = {
 141         .channel_offset = 0x1c,
 142         .timer_bit = 2,
 143 };
 144
 145 static struct resource tmu2_resources[] = {
 146         [0] = {
 147                 .start  = 0xffd80020,
 148                 .end    = 0xffd8002f,
 149                 .flags  = IORESOURCE_MEM,
 150         },
 151         [1] = {
 152                 .start  = evt2irq(0x440),
 153                 .flags  = IORESOURCE_IRQ,
 154         },
 155 };
 156
 157 static struct platform_device tmu2_device = {
 158         .name           = "sh_tmu",
 159         .id             = 2,
 160         .dev = {
 161                 .platform_data  = &tmu2_platform_data,
 162         },
 163         .resource       = tmu2_resources,
 164         .num_resources  = ARRAY_SIZE(tmu2_resources),
 165 };
 166
 167 /* SH7750R, SH7751 and SH7751R all have two extra timer channels */
 168 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 169         defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 170         defined(CONFIG_CPU_SUBTYPE_SH7751R)
 171
 172 static struct sh_timer_config tmu3_platform_data = {
 173         .channel_offset = 0x04,
 174         .timer_bit = 0,
 175 };
 176
 177 static struct resource tmu3_resources[] = {
 178         [0] = {
 179                 .start  = 0xfe100008,
 180                 .end    = 0xfe100013,
 181                 .flags  = IORESOURCE_MEM,
 182         },
 183         [1] = {
 184                 .start  = evt2irq(0xb00),
 185                 .flags  = IORESOURCE_IRQ,
 186         },
 187 };
 188
 189 static struct platform_device tmu3_device = {
 190         .name           = "sh_tmu",
 191         .id             = 3,
 192         .dev = {
 193                 .platform_data  = &tmu3_platform_data,
 194         },
 195         .resource       = tmu3_resources,
 196         .num_resources  = ARRAY_SIZE(tmu3_resources),
 197 };
 198
 199 static struct sh_timer_config tmu4_platform_data = {
 200         .channel_offset = 0x10,
 201         .timer_bit = 1,
 202 };
 203
 204 static struct resource tmu4_resources[] = {
 205         [0] = {
 206                 .start  = 0xfe100014,
 207                 .end    = 0xfe10001f,
 208                 .flags  = IORESOURCE_MEM,
 209         },
 210         [1] = {
 211                 .start  = evt2irq(0xb80),
 212                 .flags  = IORESOURCE_IRQ,
 213         },
 214 };
 215
 216 static struct platform_device tmu4_device = {
 217         .name           = "sh_tmu",
 218         .id             = 4,
 219         .dev = {
 220                 .platform_data  = &tmu4_platform_data,
 221         },
 222         .resource       = tmu4_resources,
 223         .num_resources  = ARRAY_SIZE(tmu4_resources),
 224 };
 225
 226 #endif
 227
 228 static struct platform_device *sh7750_devices[] __initdata = {
 229         &rtc_device,
 230         &tmu0_device,
 231         &tmu1_device,
 232         &tmu2_device,
 233 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 234         defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 235         defined(CONFIG_CPU_SUBTYPE_SH7751R)
 236         &tmu3_device,
 237         &tmu4_device,
 238 #endif
 239 };
 240
 241 static int __init sh7750_devices_setup(void)
 242 {
 243         if (mach_is_rts7751r2d()) {
 244                 platform_device_register(&scif_device);
 245         } else {
 246                 platform_device_register(&sci_device);
 247                 platform_device_register(&scif_device);
 248         }
 249
 250         return platform_add_devices(sh7750_devices,
 251                                     ARRAY_SIZE(sh7750_devices));
 252 }
 253 arch_initcall(sh7750_devices_setup);
 254
 255 static struct platform_device *sh7750_early_devices[] __initdata = {
 256         &tmu0_device,
 257         &tmu1_device,
 258         &tmu2_device,
 259 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 260         defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 261         defined(CONFIG_CPU_SUBTYPE_SH7751R)
 262         &tmu3_device,
 263         &tmu4_device,
 264 #endif
 265 };
 266
 267 void __init plat_early_device_setup(void)
 268 {
 269         struct platform_device *dev[1];
 270
 271         if (mach_is_rts7751r2d()) {
 272                 scif_platform_data.scscr |= SCSCR_CKE1;
 273                 dev[0] = &scif_device;
 274                 early_platform_add_devices(dev, 1);
 275         } else {
 276                 dev[0] = &sci_device;
 277                 early_platform_add_devices(dev, 1);
 278                 dev[0] = &scif_device;
 279                 early_platform_add_devices(dev, 1);
 280         }
 281
 282         early_platform_add_devices(sh7750_early_devices,
 283                                    ARRAY_SIZE(sh7750_early_devices));
 284 }
 285
 286 enum {
 287         UNUSED = 0,
 288
 289         /* interrupt sources */
 290         IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
 291         HUDI, GPIOI, DMAC,
 292         PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
 293         PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3,
 294         TMU3, TMU4, TMU0, TMU1, TMU2, RTC, SCI1, SCIF, WDT, REF,
 295
 296         /* interrupt groups */
 297         PCIC1,
 298 };
 299
 300 static struct intc_vect vectors[] __initdata = {
 301         INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
 302         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
 303         INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
 304         INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
 305         INTC_VECT(RTC, 0x4c0),
 306         INTC_VECT(SCI1, 0x4e0), INTC_VECT(SCI1, 0x500),
 307         INTC_VECT(SCI1, 0x520), INTC_VECT(SCI1, 0x540),
 308         INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720),
 309         INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760),
 310         INTC_VECT(WDT, 0x560),
 311         INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0),
 312 };
 313
 314 static struct intc_prio_reg prio_registers[] __initdata = {
 315         { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
 316         { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
 317         { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
 318         { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
 319         { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0,
 320                                                  TMU4, TMU3,
 321                                                  PCIC1, PCIC0_PCISERR } },
 322 };
 323
 324 static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, NULL,
 325                          NULL, prio_registers, NULL);
 326
 327 /* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */
 328 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
 329         defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
 330         defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 331         defined(CONFIG_CPU_SUBTYPE_SH7091)
 332 static struct intc_vect vectors_dma4[] __initdata = {
 333         INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
 334         INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
 335         INTC_VECT(DMAC, 0x6c0),
 336 };
 337
 338 static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4",
 339                          vectors_dma4, NULL,
 340                          NULL, prio_registers, NULL);
 341 #endif
 342
 343 /* SH7750R and SH7751R both have 8-channel DMA controllers */
 344 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
 345 static struct intc_vect vectors_dma8[] __initdata = {
 346         INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
 347         INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
 348         INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
 349         INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0),
 350         INTC_VECT(DMAC, 0x6c0),
 351 };
 352
 353 static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8",
 354                          vectors_dma8, NULL,
 355                          NULL, prio_registers, NULL);
 356 #endif
 357
 358 /* SH7750R, SH7751 and SH7751R all have two extra timer channels */
 359 #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 360         defined(CONFIG_CPU_SUBTYPE_SH7751) || \
 361         defined(CONFIG_CPU_SUBTYPE_SH7751R)
 362 static struct intc_vect vectors_tmu34[] __initdata = {
 363         INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
 364 };
 365
 366 static struct intc_mask_reg mask_registers[] __initdata = {
 367         { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
 368           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 369             0, 0, 0, 0, 0, 0, TMU4, TMU3,
 370             PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
 371             PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2,
 372             PCIC1_PCIDMA3, PCIC0_PCISERR } },
 373 };
 374
 375 static DECLARE_INTC_DESC(intc_desc_tmu34, "sh7750_tmu34",
 376                          vectors_tmu34, NULL,
 377                          mask_registers, prio_registers, NULL);
 378 #endif
 379
 380 /* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */
 381 static struct intc_vect vectors_irlm[] __initdata = {
 382         INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
 383         INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
 384 };
 385
 386 static DECLARE_INTC_DESC(intc_desc_irlm, "sh7750_irlm", vectors_irlm, NULL,
 387                          NULL, prio_registers, NULL);
 388
 389 /* SH7751 and SH7751R both have PCI */
 390 #if defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
 391 static struct intc_vect vectors_pci[] __initdata = {
 392         INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
 393         INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
 394         INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
 395         INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
 396 };
 397
 398 static struct intc_group groups_pci[] __initdata = {
 399         INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
 400                    PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
 401 };
 402
 403 static DECLARE_INTC_DESC(intc_desc_pci, "sh7750_pci", vectors_pci, groups_pci,
 404                          mask_registers, prio_registers, NULL);
 405 #endif
 406
 407 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
 408         defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
 409         defined(CONFIG_CPU_SUBTYPE_SH7091)
 410 void __init plat_irq_setup(void)
 411 {
 412         /*
 413          * same vectors for SH7750, SH7750S and SH7091 except for IRLM,
 414          * see below..
 415          */
 416         register_intc_controller(&intc_desc);
 417         register_intc_controller(&intc_desc_dma4);
 418 }
 419 #endif
 420
 421 #if defined(CONFIG_CPU_SUBTYPE_SH7750R)
 422 void __init plat_irq_setup(void)
 423 {
 424         register_intc_controller(&intc_desc);
 425         register_intc_controller(&intc_desc_dma8);
 426         register_intc_controller(&intc_desc_tmu34);
 427 }
 428 #endif
 429
 430 #if defined(CONFIG_CPU_SUBTYPE_SH7751)
 431 void __init plat_irq_setup(void)
 432 {
 433         register_intc_controller(&intc_desc);
 434         register_intc_controller(&intc_desc_dma4);
 435         register_intc_controller(&intc_desc_tmu34);
 436         register_intc_controller(&intc_desc_pci);
 437 }
 438 #endif
 439
 440 #if defined(CONFIG_CPU_SUBTYPE_SH7751R)
 441 void __init plat_irq_setup(void)
 442 {
 443         register_intc_controller(&intc_desc);
 444         register_intc_controller(&intc_desc_dma8);
 445         register_intc_controller(&intc_desc_tmu34);
 446         register_intc_controller(&intc_desc_pci);
 447 }
 448 #endif
 449
 450 #define INTC_ICR        0xffd00000UL
 451 #define INTC_ICR_IRLM   (1<<7)
 452
 453 void __init plat_irq_setup_pins(int mode)
 454 {
 455 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7091)
 456         BUG(); /* impossible to mask interrupts on SH7750 and SH7091 */
 457         return;
 458 #endif
 459
 460         switch (mode) {
 461         case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */
 462                 __raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
 463                 register_intc_controller(&intc_desc_irlm);
 464                 break;
 465         default:
 466                 BUG();
 467         }
 468 }