arch/sh/kernel/cpu/sh3/setup-sh7720.c

   1 /*
   2  * Setup code for SH7720, SH7721.
   3  *
   4  *  Copyright (C) 2007  Markus Brunner, Mark Jonas
   5  *  Copyright (C) 2009  Paul Mundt
   6  *
   7  *  Based on arch/sh/kernel/cpu/sh4/setup-sh7750.c:
   8  *
   9  *  Copyright (C) 2006  Paul Mundt
  10  *  Copyright (C) 2006  Jamie Lenehan
  11  *
  12  * This file is subject to the terms and conditions of the GNU General Public
  13  * License.  See the file "COPYING" in the main directory of this archive
  14  * for more details.
  15  */
  16 #include <linux/platform_device.h>
  17 #include <linux/init.h>
  18 #include <linux/serial.h>
  19 #include <linux/io.h>
  20 #include <linux/serial_sci.h>
  21 #include <linux/sh_timer.h>
  22 #include <linux/sh_intc.h>
  23 #include <linux/usb/ohci_pdriver.h>
  24 #include <asm/rtc.h>
  25 #include <cpu/serial.h>
  26
  27 static struct resource rtc_resources[] = {
  28         [0] = {
  29                 .start  = 0xa413fec0,
  30                 .end    = 0xa413fec0 + 0x28 - 1,
  31                 .flags  = IORESOURCE_IO,
  32         },
  33         [1] = {
  34                 /* Shared Period/Carry/Alarm IRQ */
  35                 .start  = evt2irq(0x480),
  36                 .flags  = IORESOURCE_IRQ,
  37         },
  38 };
  39
  40 static struct sh_rtc_platform_info rtc_info = {
  41         .capabilities   = RTC_CAP_4_DIGIT_YEAR,
  42 };
  43
  44 static struct platform_device rtc_device = {
  45         .name           = "sh-rtc",
  46         .id             = -1,
  47         .num_resources  = ARRAY_SIZE(rtc_resources),
  48         .resource       = rtc_resources,
  49         .dev            = {
  50                 .platform_data = &rtc_info,
  51         },
  52 };
  53
  54 static struct plat_sci_port scif0_platform_data = {
  55         .flags          = UPF_BOOT_AUTOCONF,
  56         .scscr          = SCSCR_RE | SCSCR_TE,
  57         .type           = PORT_SCIF,
  58         .ops            = &sh7720_sci_port_ops,
  59         .regtype        = SCIx_SH7705_SCIF_REGTYPE,
  60 };
  61
  62 static struct resource scif0_resources[] = {
  63         DEFINE_RES_MEM(0xa4430000, 0x100),
  64         DEFINE_RES_IRQ(evt2irq(0xc00)),
  65 };
  66
  67 static struct platform_device scif0_device = {
  68         .name           = "sh-sci",
  69         .id             = 0,
  70         .resource       = scif0_resources,
  71         .num_resources  = ARRAY_SIZE(scif0_resources),
  72         .dev            = {
  73                 .platform_data  = &scif0_platform_data,
  74         },
  75 };
  76
  77 static struct plat_sci_port scif1_platform_data = {
  78         .flags          = UPF_BOOT_AUTOCONF,
  79         .scscr          = SCSCR_RE | SCSCR_TE,
  80         .type           = PORT_SCIF,
  81         .ops            = &sh7720_sci_port_ops,
  82         .regtype        = SCIx_SH7705_SCIF_REGTYPE,
  83 };
  84
  85 static struct resource scif1_resources[] = {
  86         DEFINE_RES_MEM(0xa4438000, 0x100),
  87         DEFINE_RES_IRQ(evt2irq(0xc20)),
  88 };
  89
  90 static struct platform_device scif1_device = {
  91         .name           = "sh-sci",
  92         .id             = 1,
  93         .resource       = scif1_resources,
  94         .num_resources  = ARRAY_SIZE(scif1_resources),
  95         .dev            = {
  96                 .platform_data  = &scif1_platform_data,
  97         },
  98 };
  99
 100 static struct resource usb_ohci_resources[] = {
 101         [0] = {
 102                 .start  = 0xA4428000,
 103                 .end    = 0xA44280FF,
 104                 .flags  = IORESOURCE_MEM,
 105         },
 106         [1] = {
 107                 .start  = evt2irq(0xa60),
 108                 .end    = evt2irq(0xa60),
 109                 .flags  = IORESOURCE_IRQ,
 110         },
 111 };
 112
 113 static u64 usb_ohci_dma_mask = 0xffffffffUL;
 114
 115 static struct usb_ohci_pdata usb_ohci_pdata;
 116
 117 static struct platform_device usb_ohci_device = {
 118         .name           = "ohci-platform",
 119         .id             = -1,
 120         .dev = {
 121                 .dma_mask               = &usb_ohci_dma_mask,
 122                 .coherent_dma_mask      = 0xffffffff,
 123                 .platform_data          = &usb_ohci_pdata,
 124         },
 125         .num_resources  = ARRAY_SIZE(usb_ohci_resources),
 126         .resource       = usb_ohci_resources,
 127 };
 128
 129 static struct resource usbf_resources[] = {
 130         [0] = {
 131                 .name   = "sh_udc",
 132                 .start  = 0xA4420000,
 133                 .end    = 0xA44200FF,
 134                 .flags  = IORESOURCE_MEM,
 135         },
 136         [1] = {
 137                 .name   = "sh_udc",
 138                 .start  = evt2irq(0xa20),
 139                 .end    = evt2irq(0xa20),
 140                 .flags  = IORESOURCE_IRQ,
 141         },
 142 };
 143
 144 static struct platform_device usbf_device = {
 145         .name           = "sh_udc",
 146         .id             = -1,
 147         .dev = {
 148                 .dma_mask               = NULL,
 149                 .coherent_dma_mask      = 0xffffffff,
 150         },
 151         .num_resources  = ARRAY_SIZE(usbf_resources),
 152         .resource       = usbf_resources,
 153 };
 154
 155 static struct sh_timer_config cmt0_platform_data = {
 156         .channel_offset = 0x10,
 157         .timer_bit = 0,
 158         .clockevent_rating = 125,
 159         .clocksource_rating = 125,
 160 };
 161
 162 static struct resource cmt0_resources[] = {
 163         [0] = {
 164                 .start  = 0x044a0010,
 165                 .end    = 0x044a001b,
 166                 .flags  = IORESOURCE_MEM,
 167         },
 168         [1] = {
 169                 .start  = evt2irq(0xf00),
 170                 .flags  = IORESOURCE_IRQ,
 171         },
 172 };
 173
 174 static struct platform_device cmt0_device = {
 175         .name           = "sh_cmt",
 176         .id             = 0,
 177         .dev = {
 178                 .platform_data  = &cmt0_platform_data,
 179         },
 180         .resource       = cmt0_resources,
 181         .num_resources  = ARRAY_SIZE(cmt0_resources),
 182 };
 183
 184 static struct sh_timer_config cmt1_platform_data = {
 185         .channel_offset = 0x20,
 186         .timer_bit = 1,
 187 };
 188
 189 static struct resource cmt1_resources[] = {
 190         [0] = {
 191                 .start  = 0x044a0020,
 192                 .end    = 0x044a002b,
 193                 .flags  = IORESOURCE_MEM,
 194         },
 195         [1] = {
 196                 .start  = evt2irq(0xf00),
 197                 .flags  = IORESOURCE_IRQ,
 198         },
 199 };
 200
 201 static struct platform_device cmt1_device = {
 202         .name           = "sh_cmt",
 203         .id             = 1,
 204         .dev = {
 205                 .platform_data  = &cmt1_platform_data,
 206         },
 207         .resource       = cmt1_resources,
 208         .num_resources  = ARRAY_SIZE(cmt1_resources),
 209 };
 210
 211 static struct sh_timer_config cmt2_platform_data = {
 212         .channel_offset = 0x30,
 213         .timer_bit = 2,
 214 };
 215
 216 static struct resource cmt2_resources[] = {
 217         [0] = {
 218                 .start  = 0x044a0030,
 219                 .end    = 0x044a003b,
 220                 .flags  = IORESOURCE_MEM,
 221         },
 222         [1] = {
 223                 .start  = evt2irq(0xf00),
 224                 .flags  = IORESOURCE_IRQ,
 225         },
 226 };
 227
 228 static struct platform_device cmt2_device = {
 229         .name           = "sh_cmt",
 230         .id             = 2,
 231         .dev = {
 232                 .platform_data  = &cmt2_platform_data,
 233         },
 234         .resource       = cmt2_resources,
 235         .num_resources  = ARRAY_SIZE(cmt2_resources),
 236 };
 237
 238 static struct sh_timer_config cmt3_platform_data = {
 239         .channel_offset = 0x40,
 240         .timer_bit = 3,
 241 };
 242
 243 static struct resource cmt3_resources[] = {
 244         [0] = {
 245                 .start  = 0x044a0040,
 246                 .end    = 0x044a004b,
 247                 .flags  = IORESOURCE_MEM,
 248         },
 249         [1] = {
 250                 .start  = evt2irq(0xf00),
 251                 .flags  = IORESOURCE_IRQ,
 252         },
 253 };
 254
 255 static struct platform_device cmt3_device = {
 256         .name           = "sh_cmt",
 257         .id             = 3,
 258         .dev = {
 259                 .platform_data  = &cmt3_platform_data,
 260         },
 261         .resource       = cmt3_resources,
 262         .num_resources  = ARRAY_SIZE(cmt3_resources),
 263 };
 264
 265 static struct sh_timer_config cmt4_platform_data = {
 266         .channel_offset = 0x50,
 267         .timer_bit = 4,
 268 };
 269
 270 static struct resource cmt4_resources[] = {
 271         [0] = {
 272                 .start  = 0x044a0050,
 273                 .end    = 0x044a005b,
 274                 .flags  = IORESOURCE_MEM,
 275         },
 276         [1] = {
 277                 .start  = evt2irq(0xf00),
 278                 .flags  = IORESOURCE_IRQ,
 279         },
 280 };
 281
 282 static struct platform_device cmt4_device = {
 283         .name           = "sh_cmt",
 284         .id             = 4,
 285         .dev = {
 286                 .platform_data  = &cmt4_platform_data,
 287         },
 288         .resource       = cmt4_resources,
 289         .num_resources  = ARRAY_SIZE(cmt4_resources),
 290 };
 291
 292 static struct sh_timer_config tmu0_platform_data = {
 293         .channel_offset = 0x02,
 294         .timer_bit = 0,
 295         .clockevent_rating = 200,
 296 };
 297
 298 static struct resource tmu0_resources[] = {
 299         [0] = {
 300                 .start  = 0xa412fe94,
 301                 .end    = 0xa412fe9f,
 302                 .flags  = IORESOURCE_MEM,
 303         },
 304         [1] = {
 305                 .start  = evt2irq(0x400),
 306                 .flags  = IORESOURCE_IRQ,
 307         },
 308 };
 309
 310 static struct platform_device tmu0_device = {
 311         .name           = "sh_tmu",
 312         .id             = 0,
 313         .dev = {
 314                 .platform_data  = &tmu0_platform_data,
 315         },
 316         .resource       = tmu0_resources,
 317         .num_resources  = ARRAY_SIZE(tmu0_resources),
 318 };
 319
 320 static struct sh_timer_config tmu1_platform_data = {
 321         .channel_offset = 0xe,
 322         .timer_bit = 1,
 323         .clocksource_rating = 200,
 324 };
 325
 326 static struct resource tmu1_resources[] = {
 327         [0] = {
 328                 .start  = 0xa412fea0,
 329                 .end    = 0xa412feab,
 330                 .flags  = IORESOURCE_MEM,
 331         },
 332         [1] = {
 333                 .start  = evt2irq(0x420),
 334                 .flags  = IORESOURCE_IRQ,
 335         },
 336 };
 337
 338 static struct platform_device tmu1_device = {
 339         .name           = "sh_tmu",
 340         .id             = 1,
 341         .dev = {
 342                 .platform_data  = &tmu1_platform_data,
 343         },
 344         .resource       = tmu1_resources,
 345         .num_resources  = ARRAY_SIZE(tmu1_resources),
 346 };
 347
 348 static struct sh_timer_config tmu2_platform_data = {
 349         .channel_offset = 0x1a,
 350         .timer_bit = 2,
 351 };
 352
 353 static struct resource tmu2_resources[] = {
 354         [0] = {
 355                 .start  = 0xa412feac,
 356                 .end    = 0xa412feb5,
 357                 .flags  = IORESOURCE_MEM,
 358         },
 359         [1] = {
 360                 .start  = evt2irq(0x440),
 361                 .flags  = IORESOURCE_IRQ,
 362         },
 363 };
 364
 365 static struct platform_device tmu2_device = {
 366         .name           = "sh_tmu",
 367         .id             = 2,
 368         .dev = {
 369                 .platform_data  = &tmu2_platform_data,
 370         },
 371         .resource       = tmu2_resources,
 372         .num_resources  = ARRAY_SIZE(tmu2_resources),
 373 };
 374
 375 static struct platform_device *sh7720_devices[] __initdata = {
 376         &scif0_device,
 377         &scif1_device,
 378         &cmt0_device,
 379         &cmt1_device,
 380         &cmt2_device,
 381         &cmt3_device,
 382         &cmt4_device,
 383         &tmu0_device,
 384         &tmu1_device,
 385         &tmu2_device,
 386         &rtc_device,
 387         &usb_ohci_device,
 388         &usbf_device,
 389 };
 390
 391 static int __init sh7720_devices_setup(void)
 392 {
 393         return platform_add_devices(sh7720_devices,
 394                                     ARRAY_SIZE(sh7720_devices));
 395 }
 396 arch_initcall(sh7720_devices_setup);
 397
 398 static struct platform_device *sh7720_early_devices[] __initdata = {
 399         &scif0_device,
 400         &scif1_device,
 401         &cmt0_device,
 402         &cmt1_device,
 403         &cmt2_device,
 404         &cmt3_device,
 405         &cmt4_device,
 406         &tmu0_device,
 407         &tmu1_device,
 408         &tmu2_device,
 409 };
 410
 411 void __init plat_early_device_setup(void)
 412 {
 413         early_platform_add_devices(sh7720_early_devices,
 414                                    ARRAY_SIZE(sh7720_early_devices));
 415 }
 416
 417 enum {
 418         UNUSED = 0,
 419
 420         /* interrupt sources */
 421         TMU0, TMU1, TMU2, RTC,
 422         WDT, REF_RCMI, SIM,
 423         IRQ0, IRQ1, IRQ2, IRQ3,
 424         USBF_SPD, TMU_SUNI, IRQ5, IRQ4,
 425         DMAC1, LCDC, SSL,
 426         ADC, DMAC2, USBFI, CMT,
 427         SCIF0, SCIF1,
 428         PINT07, PINT815, TPU, IIC,
 429         SIOF0, SIOF1, MMC, PCC,
 430         USBHI, AFEIF,
 431         H_UDI,
 432 };
 433
 434 static struct intc_vect vectors[] __initdata = {
 435         /* IRQ0->5 are handled in setup-sh3.c */
 436         INTC_VECT(TMU0, 0x400),       INTC_VECT(TMU1, 0x420),
 437         INTC_VECT(TMU2, 0x440),       INTC_VECT(RTC, 0x480),
 438         INTC_VECT(RTC, 0x4a0),        INTC_VECT(RTC, 0x4c0),
 439         INTC_VECT(SIM, 0x4e0),        INTC_VECT(SIM, 0x500),
 440         INTC_VECT(SIM, 0x520),        INTC_VECT(SIM, 0x540),
 441         INTC_VECT(WDT, 0x560),        INTC_VECT(REF_RCMI, 0x580),
 442         /* H_UDI cannot be masked */  INTC_VECT(TMU_SUNI, 0x6c0),
 443         INTC_VECT(USBF_SPD, 0x6e0),   INTC_VECT(DMAC1, 0x800),
 444         INTC_VECT(DMAC1, 0x820),      INTC_VECT(DMAC1, 0x840),
 445         INTC_VECT(DMAC1, 0x860),      INTC_VECT(LCDC, 0x900),
 446 #if defined(CONFIG_CPU_SUBTYPE_SH7720)
 447         INTC_VECT(SSL, 0x980),
 448 #endif
 449         INTC_VECT(USBFI, 0xa20),      INTC_VECT(USBFI, 0xa40),
 450         INTC_VECT(USBHI, 0xa60),
 451         INTC_VECT(DMAC2, 0xb80),      INTC_VECT(DMAC2, 0xba0),
 452         INTC_VECT(ADC, 0xbe0),        INTC_VECT(SCIF0, 0xc00),
 453         INTC_VECT(SCIF1, 0xc20),      INTC_VECT(PINT07, 0xc80),
 454         INTC_VECT(PINT815, 0xca0),    INTC_VECT(SIOF0, 0xd00),
 455         INTC_VECT(SIOF1, 0xd20),      INTC_VECT(TPU, 0xd80),
 456         INTC_VECT(TPU, 0xda0),        INTC_VECT(TPU, 0xdc0),
 457         INTC_VECT(TPU, 0xde0),        INTC_VECT(IIC, 0xe00),
 458         INTC_VECT(MMC, 0xe80),        INTC_VECT(MMC, 0xea0),
 459         INTC_VECT(MMC, 0xec0),        INTC_VECT(MMC, 0xee0),
 460         INTC_VECT(CMT, 0xf00),        INTC_VECT(PCC, 0xf60),
 461         INTC_VECT(AFEIF, 0xfe0),
 462 };
 463
 464 static struct intc_prio_reg prio_registers[] __initdata = {
 465         { 0xA414FEE2UL, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
 466         { 0xA414FEE4UL, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, SIM, 0 } },
 467         { 0xA4140016UL, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
 468         { 0xA4140018UL, 0, 16, 4, /* IPRD */ { USBF_SPD, TMU_SUNI, IRQ5, IRQ4 } },
 469         { 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, SSL } },
 470         { 0xA4080000UL, 0, 16, 4, /* IPRF */ { ADC, DMAC2, USBFI, CMT } },
 471         { 0xA4080002UL, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, 0, 0 } },
 472         { 0xA4080004UL, 0, 16, 4, /* IPRH */ { PINT07, PINT815, TPU, IIC } },
 473         { 0xA4080006UL, 0, 16, 4, /* IPRI */ { SIOF0, SIOF1, MMC, PCC } },
 474         { 0xA4080008UL, 0, 16, 4, /* IPRJ */ { 0, USBHI, 0, AFEIF } },
 475 };
 476
 477 static DECLARE_INTC_DESC(intc_desc, "sh7720", vectors, NULL,
 478                 NULL, prio_registers, NULL);
 479
 480 void __init plat_irq_setup(void)
 481 {
 482         register_intc_controller(&intc_desc);
 483         plat_irq_setup_sh3();
 484 }