2 * Setup code for SH7720, SH7721.
4 * Copyright (C) 2007 Markus Brunner, Mark Jonas
5 * Copyright (C) 2009 Paul Mundt
7 * Based on arch/sh/kernel/cpu/sh4/setup-sh7750.c:
9 * Copyright (C) 2006 Paul Mundt
10 * Copyright (C) 2006 Jamie Lenehan
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file "COPYING" in the main directory of this archive
16 #include <linux/platform_device.h>
17 #include <linux/init.h>
18 #include <linux/serial.h>
20 #include <linux/serial_sci.h>
21 #include <linux/sh_timer.h>
22 #include <linux/sh_intc.h>
23 #include <linux/usb/ohci_pdriver.h>
25 #include <cpu/serial.h>
27 static struct resource rtc_resources[] = {
30 .end = 0xa413fec0 + 0x28 - 1,
31 .flags = IORESOURCE_IO,
34 /* Shared Period/Carry/Alarm IRQ */
35 .start = evt2irq(0x480),
36 .flags = IORESOURCE_IRQ,
40 static struct sh_rtc_platform_info rtc_info = {
41 .capabilities = RTC_CAP_4_DIGIT_YEAR,
44 static struct platform_device rtc_device = {
47 .num_resources = ARRAY_SIZE(rtc_resources),
48 .resource = rtc_resources,
50 .platform_data = &rtc_info,
54 static struct plat_sci_port scif0_platform_data = {
55 .flags = UPF_BOOT_AUTOCONF,
56 .scscr = SCSCR_RE | SCSCR_TE,
58 .ops = &sh7720_sci_port_ops,
59 .regtype = SCIx_SH7705_SCIF_REGTYPE,
62 static struct resource scif0_resources[] = {
63 DEFINE_RES_MEM(0xa4430000, 0x100),
64 DEFINE_RES_IRQ(evt2irq(0xc00)),
67 static struct platform_device scif0_device = {
70 .resource = scif0_resources,
71 .num_resources = ARRAY_SIZE(scif0_resources),
73 .platform_data = &scif0_platform_data,
77 static struct plat_sci_port scif1_platform_data = {
78 .flags = UPF_BOOT_AUTOCONF,
79 .scscr = SCSCR_RE | SCSCR_TE,
81 .ops = &sh7720_sci_port_ops,
82 .regtype = SCIx_SH7705_SCIF_REGTYPE,
85 static struct resource scif1_resources[] = {
86 DEFINE_RES_MEM(0xa4438000, 0x100),
87 DEFINE_RES_IRQ(evt2irq(0xc20)),
90 static struct platform_device scif1_device = {
93 .resource = scif1_resources,
94 .num_resources = ARRAY_SIZE(scif1_resources),
96 .platform_data = &scif1_platform_data,
100 static struct resource usb_ohci_resources[] = {
104 .flags = IORESOURCE_MEM,
107 .start = evt2irq(0xa60),
108 .end = evt2irq(0xa60),
109 .flags = IORESOURCE_IRQ,
113 static u64 usb_ohci_dma_mask = 0xffffffffUL;
115 static struct usb_ohci_pdata usb_ohci_pdata;
117 static struct platform_device usb_ohci_device = {
118 .name = "ohci-platform",
121 .dma_mask = &usb_ohci_dma_mask,
122 .coherent_dma_mask = 0xffffffff,
123 .platform_data = &usb_ohci_pdata,
125 .num_resources = ARRAY_SIZE(usb_ohci_resources),
126 .resource = usb_ohci_resources,
129 static struct resource usbf_resources[] = {
134 .flags = IORESOURCE_MEM,
138 .start = evt2irq(0xa20),
139 .end = evt2irq(0xa20),
140 .flags = IORESOURCE_IRQ,
144 static struct platform_device usbf_device = {
149 .coherent_dma_mask = 0xffffffff,
151 .num_resources = ARRAY_SIZE(usbf_resources),
152 .resource = usbf_resources,
155 static struct sh_timer_config cmt0_platform_data = {
156 .channel_offset = 0x10,
158 .clockevent_rating = 125,
159 .clocksource_rating = 125,
162 static struct resource cmt0_resources[] = {
166 .flags = IORESOURCE_MEM,
169 .start = evt2irq(0xf00),
170 .flags = IORESOURCE_IRQ,
174 static struct platform_device cmt0_device = {
178 .platform_data = &cmt0_platform_data,
180 .resource = cmt0_resources,
181 .num_resources = ARRAY_SIZE(cmt0_resources),
184 static struct sh_timer_config cmt1_platform_data = {
185 .channel_offset = 0x20,
189 static struct resource cmt1_resources[] = {
193 .flags = IORESOURCE_MEM,
196 .start = evt2irq(0xf00),
197 .flags = IORESOURCE_IRQ,
201 static struct platform_device cmt1_device = {
205 .platform_data = &cmt1_platform_data,
207 .resource = cmt1_resources,
208 .num_resources = ARRAY_SIZE(cmt1_resources),
211 static struct sh_timer_config cmt2_platform_data = {
212 .channel_offset = 0x30,
216 static struct resource cmt2_resources[] = {
220 .flags = IORESOURCE_MEM,
223 .start = evt2irq(0xf00),
224 .flags = IORESOURCE_IRQ,
228 static struct platform_device cmt2_device = {
232 .platform_data = &cmt2_platform_data,
234 .resource = cmt2_resources,
235 .num_resources = ARRAY_SIZE(cmt2_resources),
238 static struct sh_timer_config cmt3_platform_data = {
239 .channel_offset = 0x40,
243 static struct resource cmt3_resources[] = {
247 .flags = IORESOURCE_MEM,
250 .start = evt2irq(0xf00),
251 .flags = IORESOURCE_IRQ,
255 static struct platform_device cmt3_device = {
259 .platform_data = &cmt3_platform_data,
261 .resource = cmt3_resources,
262 .num_resources = ARRAY_SIZE(cmt3_resources),
265 static struct sh_timer_config cmt4_platform_data = {
266 .channel_offset = 0x50,
270 static struct resource cmt4_resources[] = {
274 .flags = IORESOURCE_MEM,
277 .start = evt2irq(0xf00),
278 .flags = IORESOURCE_IRQ,
282 static struct platform_device cmt4_device = {
286 .platform_data = &cmt4_platform_data,
288 .resource = cmt4_resources,
289 .num_resources = ARRAY_SIZE(cmt4_resources),
292 static struct sh_timer_config tmu0_platform_data = {
293 .channel_offset = 0x02,
295 .clockevent_rating = 200,
298 static struct resource tmu0_resources[] = {
302 .flags = IORESOURCE_MEM,
305 .start = evt2irq(0x400),
306 .flags = IORESOURCE_IRQ,
310 static struct platform_device tmu0_device = {
314 .platform_data = &tmu0_platform_data,
316 .resource = tmu0_resources,
317 .num_resources = ARRAY_SIZE(tmu0_resources),
320 static struct sh_timer_config tmu1_platform_data = {
321 .channel_offset = 0xe,
323 .clocksource_rating = 200,
326 static struct resource tmu1_resources[] = {
330 .flags = IORESOURCE_MEM,
333 .start = evt2irq(0x420),
334 .flags = IORESOURCE_IRQ,
338 static struct platform_device tmu1_device = {
342 .platform_data = &tmu1_platform_data,
344 .resource = tmu1_resources,
345 .num_resources = ARRAY_SIZE(tmu1_resources),
348 static struct sh_timer_config tmu2_platform_data = {
349 .channel_offset = 0x1a,
353 static struct resource tmu2_resources[] = {
357 .flags = IORESOURCE_MEM,
360 .start = evt2irq(0x440),
361 .flags = IORESOURCE_IRQ,
365 static struct platform_device tmu2_device = {
369 .platform_data = &tmu2_platform_data,
371 .resource = tmu2_resources,
372 .num_resources = ARRAY_SIZE(tmu2_resources),
375 static struct platform_device *sh7720_devices[] __initdata = {
391 static int __init sh7720_devices_setup(void)
393 return platform_add_devices(sh7720_devices,
394 ARRAY_SIZE(sh7720_devices));
396 arch_initcall(sh7720_devices_setup);
398 static struct platform_device *sh7720_early_devices[] __initdata = {
411 void __init plat_early_device_setup(void)
413 early_platform_add_devices(sh7720_early_devices,
414 ARRAY_SIZE(sh7720_early_devices));
420 /* interrupt sources */
421 TMU0, TMU1, TMU2, RTC,
423 IRQ0, IRQ1, IRQ2, IRQ3,
424 USBF_SPD, TMU_SUNI, IRQ5, IRQ4,
426 ADC, DMAC2, USBFI, CMT,
428 PINT07, PINT815, TPU, IIC,
429 SIOF0, SIOF1, MMC, PCC,
434 static struct intc_vect vectors[] __initdata = {
435 /* IRQ0->5 are handled in setup-sh3.c */
436 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
437 INTC_VECT(TMU2, 0x440), INTC_VECT(RTC, 0x480),
438 INTC_VECT(RTC, 0x4a0), INTC_VECT(RTC, 0x4c0),
439 INTC_VECT(SIM, 0x4e0), INTC_VECT(SIM, 0x500),
440 INTC_VECT(SIM, 0x520), INTC_VECT(SIM, 0x540),
441 INTC_VECT(WDT, 0x560), INTC_VECT(REF_RCMI, 0x580),
442 /* H_UDI cannot be masked */ INTC_VECT(TMU_SUNI, 0x6c0),
443 INTC_VECT(USBF_SPD, 0x6e0), INTC_VECT(DMAC1, 0x800),
444 INTC_VECT(DMAC1, 0x820), INTC_VECT(DMAC1, 0x840),
445 INTC_VECT(DMAC1, 0x860), INTC_VECT(LCDC, 0x900),
446 #if defined(CONFIG_CPU_SUBTYPE_SH7720)
447 INTC_VECT(SSL, 0x980),
449 INTC_VECT(USBFI, 0xa20), INTC_VECT(USBFI, 0xa40),
450 INTC_VECT(USBHI, 0xa60),
451 INTC_VECT(DMAC2, 0xb80), INTC_VECT(DMAC2, 0xba0),
452 INTC_VECT(ADC, 0xbe0), INTC_VECT(SCIF0, 0xc00),
453 INTC_VECT(SCIF1, 0xc20), INTC_VECT(PINT07, 0xc80),
454 INTC_VECT(PINT815, 0xca0), INTC_VECT(SIOF0, 0xd00),
455 INTC_VECT(SIOF1, 0xd20), INTC_VECT(TPU, 0xd80),
456 INTC_VECT(TPU, 0xda0), INTC_VECT(TPU, 0xdc0),
457 INTC_VECT(TPU, 0xde0), INTC_VECT(IIC, 0xe00),
458 INTC_VECT(MMC, 0xe80), INTC_VECT(MMC, 0xea0),
459 INTC_VECT(MMC, 0xec0), INTC_VECT(MMC, 0xee0),
460 INTC_VECT(CMT, 0xf00), INTC_VECT(PCC, 0xf60),
461 INTC_VECT(AFEIF, 0xfe0),
464 static struct intc_prio_reg prio_registers[] __initdata = {
465 { 0xA414FEE2UL, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
466 { 0xA414FEE4UL, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, SIM, 0 } },
467 { 0xA4140016UL, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
468 { 0xA4140018UL, 0, 16, 4, /* IPRD */ { USBF_SPD, TMU_SUNI, IRQ5, IRQ4 } },
469 { 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, SSL } },
470 { 0xA4080000UL, 0, 16, 4, /* IPRF */ { ADC, DMAC2, USBFI, CMT } },
471 { 0xA4080002UL, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, 0, 0 } },
472 { 0xA4080004UL, 0, 16, 4, /* IPRH */ { PINT07, PINT815, TPU, IIC } },
473 { 0xA4080006UL, 0, 16, 4, /* IPRI */ { SIOF0, SIOF1, MMC, PCC } },
474 { 0xA4080008UL, 0, 16, 4, /* IPRJ */ { 0, USBHI, 0, AFEIF } },
477 static DECLARE_INTC_DESC(intc_desc, "sh7720", vectors, NULL,
478 NULL, prio_registers, NULL);
480 void __init plat_irq_setup(void)
482 register_intc_controller(&intc_desc);
483 plat_irq_setup_sh3();