2 * SH3 Setup code for SH7706, SH7707, SH7708, SH7709
4 * Copyright (C) 2007 Magnus Damm
5 * Copyright (C) 2009 Paul Mundt
7 * Based on setup-sh7709.c
9 * Copyright (C) 2006 Paul Mundt
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
15 #include <linux/init.h>
17 #include <linux/irq.h>
18 #include <linux/platform_device.h>
19 #include <linux/serial.h>
20 #include <linux/serial_sci.h>
21 #include <linux/sh_timer.h>
26 /* interrupt sources */
27 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
29 DMAC, SCIF0, SCIF2, SCI, ADC_ADI,
35 static struct intc_vect vectors[] __initdata = {
36 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
37 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
38 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
39 INTC_VECT(RTC, 0x4c0),
40 INTC_VECT(SCI, 0x4e0), INTC_VECT(SCI, 0x500),
41 INTC_VECT(SCI, 0x520), INTC_VECT(SCI, 0x540),
42 INTC_VECT(WDT, 0x560),
43 INTC_VECT(REF, 0x580),
44 INTC_VECT(REF, 0x5a0),
45 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
46 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
47 defined(CONFIG_CPU_SUBTYPE_SH7709)
48 /* IRQ0->5 are handled in setup-sh3.c */
49 INTC_VECT(DMAC, 0x800), INTC_VECT(DMAC, 0x820),
50 INTC_VECT(DMAC, 0x840), INTC_VECT(DMAC, 0x860),
51 INTC_VECT(ADC_ADI, 0x980),
52 INTC_VECT(SCIF2, 0x900), INTC_VECT(SCIF2, 0x920),
53 INTC_VECT(SCIF2, 0x940), INTC_VECT(SCIF2, 0x960),
55 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
56 defined(CONFIG_CPU_SUBTYPE_SH7709)
57 INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720),
58 INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0),
59 INTC_VECT(SCIF0, 0x8c0), INTC_VECT(SCIF0, 0x8e0),
61 #if defined(CONFIG_CPU_SUBTYPE_SH7707)
62 INTC_VECT(LCDC, 0x9a0),
63 INTC_VECT(PCC0, 0x9c0), INTC_VECT(PCC1, 0x9e0),
67 static struct intc_prio_reg prio_registers[] __initdata = {
68 { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
69 { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, SCI, 0 } },
70 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
71 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
72 defined(CONFIG_CPU_SUBTYPE_SH7709)
73 { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
74 { 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },
75 { 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC, 0, SCIF2, ADC_ADI } },
77 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
78 defined(CONFIG_CPU_SUBTYPE_SH7709)
79 { 0xa4000018, 0, 16, 4, /* IPRD */ { PINT07, PINT815, } },
80 { 0xa400001a, 0, 16, 4, /* IPRE */ { 0, SCIF0 } },
82 #if defined(CONFIG_CPU_SUBTYPE_SH7707)
83 { 0xa400001c, 0, 16, 4, /* IPRF */ { 0, LCDC, PCC0, PCC1, } },
87 static DECLARE_INTC_DESC(intc_desc, "sh770x", vectors, NULL,
88 NULL, prio_registers, NULL);
90 static struct resource rtc_resources[] = {
93 .end = 0xfffffec0 + 0x1e,
94 .flags = IORESOURCE_IO,
98 .flags = IORESOURCE_IRQ,
102 static struct platform_device rtc_device = {
105 .num_resources = ARRAY_SIZE(rtc_resources),
106 .resource = rtc_resources,
109 static struct plat_sci_port scif0_platform_data = {
110 .mapbase = 0xfffffe80,
111 .flags = UPF_BOOT_AUTOCONF,
112 .scscr = SCSCR_TE | SCSCR_RE,
113 .scbrr_algo_id = SCBRR_ALGO_2,
115 .irqs = { 23, 23, 23, 0 },
118 static struct platform_device scif0_device = {
122 .platform_data = &scif0_platform_data,
125 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
126 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
127 defined(CONFIG_CPU_SUBTYPE_SH7709)
128 static struct plat_sci_port scif1_platform_data = {
129 .mapbase = 0xa4000150,
130 .flags = UPF_BOOT_AUTOCONF,
131 .scscr = SCSCR_TE | SCSCR_RE,
132 .scbrr_algo_id = SCBRR_ALGO_2,
134 .irqs = { 56, 56, 56, 56 },
137 static struct platform_device scif1_device = {
141 .platform_data = &scif1_platform_data,
145 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
146 defined(CONFIG_CPU_SUBTYPE_SH7709)
147 static struct plat_sci_port scif2_platform_data = {
148 .mapbase = 0xa4000140,
149 .flags = UPF_BOOT_AUTOCONF,
150 .scscr = SCSCR_TE | SCSCR_RE,
151 .scbrr_algo_id = SCBRR_ALGO_2,
153 .irqs = { 52, 52, 52, 52 },
156 static struct platform_device scif2_device = {
160 .platform_data = &scif2_platform_data,
165 static struct sh_timer_config tmu0_platform_data = {
166 .channel_offset = 0x02,
168 .clockevent_rating = 200,
171 static struct resource tmu0_resources[] = {
175 .flags = IORESOURCE_MEM,
179 .flags = IORESOURCE_IRQ,
183 static struct platform_device tmu0_device = {
187 .platform_data = &tmu0_platform_data,
189 .resource = tmu0_resources,
190 .num_resources = ARRAY_SIZE(tmu0_resources),
193 static struct sh_timer_config tmu1_platform_data = {
194 .channel_offset = 0xe,
196 .clocksource_rating = 200,
199 static struct resource tmu1_resources[] = {
203 .flags = IORESOURCE_MEM,
207 .flags = IORESOURCE_IRQ,
211 static struct platform_device tmu1_device = {
215 .platform_data = &tmu1_platform_data,
217 .resource = tmu1_resources,
218 .num_resources = ARRAY_SIZE(tmu1_resources),
221 static struct sh_timer_config tmu2_platform_data = {
222 .channel_offset = 0x1a,
226 static struct resource tmu2_resources[] = {
230 .flags = IORESOURCE_MEM,
234 .flags = IORESOURCE_IRQ,
238 static struct platform_device tmu2_device = {
242 .platform_data = &tmu2_platform_data,
244 .resource = tmu2_resources,
245 .num_resources = ARRAY_SIZE(tmu2_resources),
248 static struct platform_device *sh770x_devices[] __initdata = {
250 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
251 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
252 defined(CONFIG_CPU_SUBTYPE_SH7709)
255 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
256 defined(CONFIG_CPU_SUBTYPE_SH7709)
265 static int __init sh770x_devices_setup(void)
267 return platform_add_devices(sh770x_devices,
268 ARRAY_SIZE(sh770x_devices));
270 arch_initcall(sh770x_devices_setup);
272 static struct platform_device *sh770x_early_devices[] __initdata = {
274 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
275 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
276 defined(CONFIG_CPU_SUBTYPE_SH7709)
279 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
280 defined(CONFIG_CPU_SUBTYPE_SH7709)
288 void __init plat_early_device_setup(void)
290 early_platform_add_devices(sh770x_early_devices,
291 ARRAY_SIZE(sh770x_early_devices));
294 void __init plat_irq_setup(void)
296 register_intc_controller(&intc_desc);
297 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
298 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
299 defined(CONFIG_CPU_SUBTYPE_SH7709)
300 plat_irq_setup_sh3();