4 * Copyright (C) 2006 Yoshinori Sato
5 * Copyright (C) 2009 Paul Mundt
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
11 #include <linux/platform_device.h>
12 #include <linux/init.h>
13 #include <linux/serial.h>
14 #include <linux/serial_sci.h>
15 #include <linux/sh_eth.h>
16 #include <linux/sh_timer.h>
22 /* interrupt sources */
23 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
24 WDT, EDMAC, CMT0, CMT1,
27 DMAC0, DMAC1, DMAC2, DMAC3,
31 static struct intc_vect vectors[] __initdata = {
32 INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
33 INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
34 INTC_IRQ(IRQ4, 80), INTC_IRQ(IRQ5, 81),
35 INTC_IRQ(IRQ6, 82), INTC_IRQ(IRQ7, 83),
36 INTC_IRQ(WDT, 84), INTC_IRQ(EDMAC, 85),
37 INTC_IRQ(CMT0, 86), INTC_IRQ(CMT1, 87),
38 INTC_IRQ(SCIF0, 88), INTC_IRQ(SCIF0, 89),
39 INTC_IRQ(SCIF0, 90), INTC_IRQ(SCIF0, 91),
40 INTC_IRQ(SCIF1, 92), INTC_IRQ(SCIF1, 93),
41 INTC_IRQ(SCIF1, 94), INTC_IRQ(SCIF1, 95),
42 INTC_IRQ(SCIF2, 96), INTC_IRQ(SCIF2, 97),
43 INTC_IRQ(SCIF2, 98), INTC_IRQ(SCIF2, 99),
44 INTC_IRQ(HIF_HIFI, 100), INTC_IRQ(HIF_HIFBI, 101),
45 INTC_IRQ(DMAC0, 104), INTC_IRQ(DMAC1, 105),
46 INTC_IRQ(DMAC2, 106), INTC_IRQ(DMAC3, 107),
50 static struct intc_prio_reg prio_registers[] __initdata = {
51 { 0xf8140006, 0, 16, 4, /* IPRA */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
52 { 0xf8140008, 0, 16, 4, /* IPRB */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
53 { 0xf8080000, 0, 16, 4, /* IPRC */ { WDT, EDMAC, CMT0, CMT1 } },
54 { 0xf8080002, 0, 16, 4, /* IPRD */ { SCIF0, SCIF1, SCIF2 } },
55 { 0xf8080004, 0, 16, 4, /* IPRE */ { HIF_HIFI, HIF_HIFBI } },
56 { 0xf8080006, 0, 16, 4, /* IPRF */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
57 { 0xf8080008, 0, 16, 4, /* IPRG */ { SIOF } },
60 static DECLARE_INTC_DESC(intc_desc, "sh7619", vectors, NULL,
61 NULL, prio_registers, NULL);
63 static struct plat_sci_port scif0_platform_data = {
64 .flags = UPF_BOOT_AUTOCONF,
65 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
69 static struct resource scif0_resources[] = {
70 DEFINE_RES_MEM(0xf8400000, 0x100),
74 static struct platform_device scif0_device = {
77 .resource = scif0_resources,
78 .num_resources = ARRAY_SIZE(scif0_resources),
80 .platform_data = &scif0_platform_data,
84 static struct plat_sci_port scif1_platform_data = {
85 .flags = UPF_BOOT_AUTOCONF,
86 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
90 static struct resource scif1_resources[] = {
91 DEFINE_RES_MEM(0xf8410000, 0x100),
95 static struct platform_device scif1_device = {
98 .resource = scif1_resources,
99 .num_resources = ARRAY_SIZE(scif1_resources),
101 .platform_data = &scif1_platform_data,
105 static struct plat_sci_port scif2_platform_data = {
106 .flags = UPF_BOOT_AUTOCONF,
107 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
111 static struct resource scif2_resources[] = {
112 DEFINE_RES_MEM(0xf8420000, 0x100),
116 static struct platform_device scif2_device = {
119 .resource = scif2_resources,
120 .num_resources = ARRAY_SIZE(scif2_resources),
122 .platform_data = &scif2_platform_data,
126 static struct sh_eth_plat_data eth_platform_data = {
128 .edmac_endian = EDMAC_LITTLE_ENDIAN,
129 .phy_interface = PHY_INTERFACE_MODE_MII,
132 static struct resource eth_resources[] = {
136 .flags = IORESOURCE_MEM,
141 .flags = IORESOURCE_IRQ,
145 static struct platform_device eth_device = {
146 .name = "sh7619-ether",
149 .platform_data = ð_platform_data,
151 .num_resources = ARRAY_SIZE(eth_resources),
152 .resource = eth_resources,
155 static struct sh_timer_config cmt0_platform_data = {
156 .channel_offset = 0x02,
158 .clockevent_rating = 125,
159 .clocksource_rating = 0, /* disabled due to code generation issues */
162 static struct resource cmt0_resources[] = {
166 .flags = IORESOURCE_MEM,
170 .flags = IORESOURCE_IRQ,
174 static struct platform_device cmt0_device = {
178 .platform_data = &cmt0_platform_data,
180 .resource = cmt0_resources,
181 .num_resources = ARRAY_SIZE(cmt0_resources),
184 static struct sh_timer_config cmt1_platform_data = {
185 .channel_offset = 0x08,
187 .clockevent_rating = 125,
188 .clocksource_rating = 0, /* disabled due to code generation issues */
191 static struct resource cmt1_resources[] = {
195 .flags = IORESOURCE_MEM,
199 .flags = IORESOURCE_IRQ,
203 static struct platform_device cmt1_device = {
207 .platform_data = &cmt1_platform_data,
209 .resource = cmt1_resources,
210 .num_resources = ARRAY_SIZE(cmt1_resources),
213 static struct platform_device *sh7619_devices[] __initdata = {
222 static int __init sh7619_devices_setup(void)
224 return platform_add_devices(sh7619_devices,
225 ARRAY_SIZE(sh7619_devices));
227 arch_initcall(sh7619_devices_setup);
229 void __init plat_irq_setup(void)
231 register_intc_controller(&intc_desc);
234 static struct platform_device *sh7619_early_devices[] __initdata = {
242 #define STBCR3 0xf80a0000
244 void __init plat_early_device_setup(void)
246 /* enable CMT clock */
247 __raw_writeb(__raw_readb(STBCR3) & ~0x10, STBCR3);
249 early_platform_add_devices(sh7619_early_devices,
250 ARRAY_SIZE(sh7619_early_devices));