2 * Renesas System Solutions Asia Pte. Ltd - Migo-R
4 * Copyright (C) 2008 Magnus Damm
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/init.h>
11 #include <linux/platform_device.h>
12 #include <linux/interrupt.h>
13 #include <linux/input.h>
14 #include <linux/input/sh_keysc.h>
15 #include <linux/mmc/host.h>
16 #include <linux/mmc/sh_mobile_sdhi.h>
17 #include <linux/mtd/physmap.h>
18 #include <linux/mtd/nand.h>
19 #include <linux/i2c.h>
20 #include <linux/smc91x.h>
21 #include <linux/delay.h>
22 #include <linux/clk.h>
23 #include <linux/gpio.h>
24 #include <video/sh_mobile_lcdc.h>
25 #include <media/sh_mobile_ceu.h>
26 #include <media/ov772x.h>
27 #include <media/tw9910.h>
28 #include <asm/clock.h>
29 #include <asm/machvec.h>
31 #include <asm/suspend.h>
32 #include <mach/migor.h>
33 #include <cpu/sh7722.h>
35 /* Address IRQ Size Bus Description
36 * 0x00000000 64MB 16 NOR Flash (SP29PL256N)
37 * 0x0c000000 64MB 64 SDRAM (2xK4M563233G)
38 * 0x10000000 IRQ0 16 Ethernet (SMC91C111)
39 * 0x14000000 IRQ4 16 USB 2.0 Host Controller (M66596)
40 * 0x18000000 8GB 8 NAND Flash (K9K8G08U0A)
43 static struct smc91x_platdata smc91x_info = {
44 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
47 static struct resource smc91x_eth_resources[] = {
52 .flags = IORESOURCE_MEM,
55 .start = 32, /* IRQ0 */
56 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
60 static struct platform_device smc91x_eth_device = {
62 .num_resources = ARRAY_SIZE(smc91x_eth_resources),
63 .resource = smc91x_eth_resources,
65 .platform_data = &smc91x_info,
69 static struct sh_keysc_info sh_keysc_info = {
70 .mode = SH_KEYSC_MODE_2, /* KEYOUT0->4, KEYIN1->5 */
74 0, KEY_UP, KEY_DOWN, KEY_LEFT, KEY_RIGHT, KEY_ENTER,
75 0, KEY_F, KEY_C, KEY_D, KEY_H, KEY_1,
76 0, KEY_2, KEY_3, KEY_4, KEY_5, KEY_6,
77 0, KEY_7, KEY_8, KEY_9, KEY_S, KEY_0,
78 0, KEY_P, KEY_STOP, KEY_REWIND, KEY_PLAY, KEY_FASTFORWARD,
82 static struct resource sh_keysc_resources[] = {
86 .flags = IORESOURCE_MEM,
90 .flags = IORESOURCE_IRQ,
94 static struct platform_device sh_keysc_device = {
96 .id = 0, /* "keysc0" clock */
97 .num_resources = ARRAY_SIZE(sh_keysc_resources),
98 .resource = sh_keysc_resources,
100 .platform_data = &sh_keysc_info,
103 .hwblk_id = HWBLK_KEYSC,
107 static struct mtd_partition migor_nor_flash_partitions[] =
112 .size = (1 * 1024 * 1024),
113 .mask_flags = MTD_WRITEABLE, /* Read-only */
117 .offset = MTDPART_OFS_APPEND,
118 .size = (15 * 1024 * 1024),
122 .offset = MTDPART_OFS_APPEND,
123 .size = MTDPART_SIZ_FULL,
127 static struct physmap_flash_data migor_nor_flash_data = {
129 .parts = migor_nor_flash_partitions,
130 .nr_parts = ARRAY_SIZE(migor_nor_flash_partitions),
133 static struct resource migor_nor_flash_resources[] = {
138 .flags = IORESOURCE_MEM,
142 static struct platform_device migor_nor_flash_device = {
143 .name = "physmap-flash",
144 .resource = migor_nor_flash_resources,
145 .num_resources = ARRAY_SIZE(migor_nor_flash_resources),
147 .platform_data = &migor_nor_flash_data,
151 static struct mtd_partition migor_nand_flash_partitions[] = {
155 .size = 512 * 1024 * 1024,
159 .offset = MTDPART_OFS_APPEND,
160 .size = 512 * 1024 * 1024,
164 static void migor_nand_flash_cmd_ctl(struct mtd_info *mtd, int cmd,
167 struct nand_chip *chip = mtd->priv;
169 if (cmd == NAND_CMD_NONE)
173 writeb(cmd, chip->IO_ADDR_W + 0x00400000);
174 else if (ctrl & NAND_ALE)
175 writeb(cmd, chip->IO_ADDR_W + 0x00800000);
177 writeb(cmd, chip->IO_ADDR_W);
180 static int migor_nand_flash_ready(struct mtd_info *mtd)
182 return gpio_get_value(GPIO_PTA1); /* NAND_RBn */
185 static struct platform_nand_data migor_nand_flash_data = {
188 .partitions = migor_nand_flash_partitions,
189 .nr_partitions = ARRAY_SIZE(migor_nand_flash_partitions),
191 .part_probe_types = (const char *[]) { "cmdlinepart", NULL },
194 .dev_ready = migor_nand_flash_ready,
195 .cmd_ctrl = migor_nand_flash_cmd_ctl,
199 static struct resource migor_nand_flash_resources[] = {
201 .name = "NAND Flash",
204 .flags = IORESOURCE_MEM,
208 static struct platform_device migor_nand_flash_device = {
210 .resource = migor_nand_flash_resources,
211 .num_resources = ARRAY_SIZE(migor_nand_flash_resources),
213 .platform_data = &migor_nand_flash_data,
217 static const struct fb_videomode migor_lcd_modes[] = {
219 #if defined(CONFIG_SH_MIGOR_RTA_WVGA)
227 #elif defined(CONFIG_SH_MIGOR_QVGA)
234 .sync = FB_SYNC_HOR_HIGH_ACT,
242 static struct sh_mobile_lcdc_info sh_mobile_lcdc_info = {
243 #if defined(CONFIG_SH_MIGOR_RTA_WVGA)
244 .clock_source = LCDC_CLK_BUS,
246 .chan = LCDC_CHAN_MAINLCD,
248 .interface_type = RGB16,
250 .lcd_cfg = migor_lcd_modes,
251 .num_cfg = ARRAY_SIZE(migor_lcd_modes),
252 .lcd_size_cfg = { /* 7.0 inch */
257 #elif defined(CONFIG_SH_MIGOR_QVGA)
258 .clock_source = LCDC_CLK_PERIPHERAL,
260 .chan = LCDC_CHAN_MAINLCD,
262 .interface_type = SYS16A,
264 .lcd_cfg = migor_lcd_modes,
265 .num_cfg = ARRAY_SIZE(migor_lcd_modes),
266 .lcd_size_cfg = { /* 2.4 inch */
271 .setup_sys = migor_lcd_qvga_setup,
274 .ldmt2r = 0x06000a09,
275 .ldmt3r = 0x180e3418,
276 /* set 1s delay to encourage fsync() */
277 .deferred_io_msec = 1000,
283 static struct resource migor_lcdc_resources[] = {
286 .start = 0xfe940000, /* P4-only space */
288 .flags = IORESOURCE_MEM,
292 .flags = IORESOURCE_IRQ,
296 static struct platform_device migor_lcdc_device = {
297 .name = "sh_mobile_lcdc_fb",
298 .num_resources = ARRAY_SIZE(migor_lcdc_resources),
299 .resource = migor_lcdc_resources,
301 .platform_data = &sh_mobile_lcdc_info,
304 .hwblk_id = HWBLK_LCDC,
308 static struct clk *camera_clk;
309 static DEFINE_MUTEX(camera_lock);
311 static void camera_power_on(int is_tw)
313 mutex_lock(&camera_lock);
315 /* Use 10 MHz VIO_CKO instead of 24 MHz to work
316 * around signal quality issues on Panel Board V2.1.
318 camera_clk = clk_get(NULL, "video_clk");
319 clk_set_rate(camera_clk, 10000000);
320 clk_enable(camera_clk); /* start VIO_CKO */
322 /* use VIO_RST to take camera out of reset */
325 gpio_set_value(GPIO_PTT2, 0);
326 gpio_set_value(GPIO_PTT0, 0);
328 gpio_set_value(GPIO_PTT0, 1);
330 gpio_set_value(GPIO_PTT3, 0);
332 gpio_set_value(GPIO_PTT3, 1);
333 mdelay(10); /* wait to let chip come out of reset */
336 static void camera_power_off(void)
338 clk_disable(camera_clk); /* stop VIO_CKO */
341 gpio_set_value(GPIO_PTT3, 0);
342 mutex_unlock(&camera_lock);
345 static int ov7725_power(struct device *dev, int mode)
355 static int tw9910_power(struct device *dev, int mode)
365 static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
366 .flags = SH_CEU_FLAG_USE_8BIT_BUS,
369 static struct resource migor_ceu_resources[] = {
374 .flags = IORESOURCE_MEM,
378 .flags = IORESOURCE_IRQ,
381 /* place holder for contiguous memory */
385 static struct platform_device migor_ceu_device = {
386 .name = "sh_mobile_ceu",
387 .id = 0, /* "ceu0" clock */
388 .num_resources = ARRAY_SIZE(migor_ceu_resources),
389 .resource = migor_ceu_resources,
391 .platform_data = &sh_mobile_ceu_info,
394 .hwblk_id = HWBLK_CEU,
398 static struct resource sdhi_cn9_resources[] = {
403 .flags = IORESOURCE_MEM,
407 .flags = IORESOURCE_IRQ,
411 static struct sh_mobile_sdhi_info sh7724_sdhi_data = {
412 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
413 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
414 .tmio_caps = MMC_CAP_SDIO_IRQ,
417 static struct platform_device sdhi_cn9_device = {
418 .name = "sh_mobile_sdhi",
419 .num_resources = ARRAY_SIZE(sdhi_cn9_resources),
420 .resource = sdhi_cn9_resources,
422 .platform_data = &sh7724_sdhi_data,
425 .hwblk_id = HWBLK_SDHI,
429 static struct i2c_board_info migor_i2c_devices[] = {
431 I2C_BOARD_INFO("rs5c372b", 0x32),
434 I2C_BOARD_INFO("migor_ts", 0x51),
435 .irq = 38, /* IRQ6 */
438 I2C_BOARD_INFO("wm8978", 0x1a),
442 static struct i2c_board_info migor_i2c_camera[] = {
444 I2C_BOARD_INFO("ov772x", 0x21),
447 I2C_BOARD_INFO("tw9910", 0x45),
451 static struct ov772x_camera_info ov7725_info;
453 static struct soc_camera_link ov7725_link = {
454 .power = ov7725_power,
455 .board_info = &migor_i2c_camera[0],
457 .priv = &ov7725_info,
460 static struct tw9910_video_info tw9910_info = {
461 .buswidth = SOCAM_DATAWIDTH_8,
462 .mpout = TW9910_MPO_FIELD,
465 static struct soc_camera_link tw9910_link = {
466 .power = tw9910_power,
467 .board_info = &migor_i2c_camera[1],
469 .priv = &tw9910_info,
472 static struct platform_device migor_camera[] = {
474 .name = "soc-camera-pdrv",
477 .platform_data = &ov7725_link,
480 .name = "soc-camera-pdrv",
483 .platform_data = &tw9910_link,
488 static struct platform_device *migor_devices[] __initdata = {
493 &migor_nor_flash_device,
494 &migor_nand_flash_device,
500 extern char migor_sdram_enter_start;
501 extern char migor_sdram_enter_end;
502 extern char migor_sdram_leave_start;
503 extern char migor_sdram_leave_end;
505 static int __init migor_devices_setup(void)
507 /* register board specific self-refresh code */
508 sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF,
509 &migor_sdram_enter_start,
510 &migor_sdram_enter_end,
511 &migor_sdram_leave_start,
512 &migor_sdram_leave_end);
513 /* Let D11 LED show STATUS0 */
514 gpio_request(GPIO_FN_STATUS0, NULL);
516 /* Lit D12 LED show PDSTATUS */
517 gpio_request(GPIO_FN_PDSTATUS, NULL);
519 /* SMC91C111 - Enable IRQ0, Setup CS4 for 16-bit fast access */
520 gpio_request(GPIO_FN_IRQ0, NULL);
521 __raw_writel(0x00003400, BSC_CS4BCR);
522 __raw_writel(0x00110080, BSC_CS4WCR);
525 gpio_request(GPIO_FN_KEYOUT0, NULL);
526 gpio_request(GPIO_FN_KEYOUT1, NULL);
527 gpio_request(GPIO_FN_KEYOUT2, NULL);
528 gpio_request(GPIO_FN_KEYOUT3, NULL);
529 gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
530 gpio_request(GPIO_FN_KEYIN1, NULL);
531 gpio_request(GPIO_FN_KEYIN2, NULL);
532 gpio_request(GPIO_FN_KEYIN3, NULL);
533 gpio_request(GPIO_FN_KEYIN4, NULL);
534 gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
537 gpio_request(GPIO_FN_CS6A_CE2B, NULL);
538 __raw_writel((__raw_readl(BSC_CS6ABCR) & ~0x0600) | 0x0200, BSC_CS6ABCR);
539 gpio_request(GPIO_PTA1, NULL);
540 gpio_direction_input(GPIO_PTA1);
543 gpio_request(GPIO_FN_SDHICD, NULL);
544 gpio_request(GPIO_FN_SDHIWP, NULL);
545 gpio_request(GPIO_FN_SDHID3, NULL);
546 gpio_request(GPIO_FN_SDHID2, NULL);
547 gpio_request(GPIO_FN_SDHID1, NULL);
548 gpio_request(GPIO_FN_SDHID0, NULL);
549 gpio_request(GPIO_FN_SDHICMD, NULL);
550 gpio_request(GPIO_FN_SDHICLK, NULL);
553 gpio_request(GPIO_FN_IRQ6, NULL);
556 #ifdef CONFIG_SH_MIGOR_QVGA /* LCDC - QVGA - Enable SYS Interface signals */
557 gpio_request(GPIO_FN_LCDD17, NULL);
558 gpio_request(GPIO_FN_LCDD16, NULL);
559 gpio_request(GPIO_FN_LCDD15, NULL);
560 gpio_request(GPIO_FN_LCDD14, NULL);
561 gpio_request(GPIO_FN_LCDD13, NULL);
562 gpio_request(GPIO_FN_LCDD12, NULL);
563 gpio_request(GPIO_FN_LCDD11, NULL);
564 gpio_request(GPIO_FN_LCDD10, NULL);
565 gpio_request(GPIO_FN_LCDD8, NULL);
566 gpio_request(GPIO_FN_LCDD7, NULL);
567 gpio_request(GPIO_FN_LCDD6, NULL);
568 gpio_request(GPIO_FN_LCDD5, NULL);
569 gpio_request(GPIO_FN_LCDD4, NULL);
570 gpio_request(GPIO_FN_LCDD3, NULL);
571 gpio_request(GPIO_FN_LCDD2, NULL);
572 gpio_request(GPIO_FN_LCDD1, NULL);
573 gpio_request(GPIO_FN_LCDRS, NULL);
574 gpio_request(GPIO_FN_LCDCS, NULL);
575 gpio_request(GPIO_FN_LCDRD, NULL);
576 gpio_request(GPIO_FN_LCDWR, NULL);
577 gpio_request(GPIO_PTH2, NULL); /* LCD_DON */
578 gpio_direction_output(GPIO_PTH2, 1);
580 #ifdef CONFIG_SH_MIGOR_RTA_WVGA /* LCDC - WVGA - Enable RGB Interface signals */
581 gpio_request(GPIO_FN_LCDD15, NULL);
582 gpio_request(GPIO_FN_LCDD14, NULL);
583 gpio_request(GPIO_FN_LCDD13, NULL);
584 gpio_request(GPIO_FN_LCDD12, NULL);
585 gpio_request(GPIO_FN_LCDD11, NULL);
586 gpio_request(GPIO_FN_LCDD10, NULL);
587 gpio_request(GPIO_FN_LCDD9, NULL);
588 gpio_request(GPIO_FN_LCDD8, NULL);
589 gpio_request(GPIO_FN_LCDD7, NULL);
590 gpio_request(GPIO_FN_LCDD6, NULL);
591 gpio_request(GPIO_FN_LCDD5, NULL);
592 gpio_request(GPIO_FN_LCDD4, NULL);
593 gpio_request(GPIO_FN_LCDD3, NULL);
594 gpio_request(GPIO_FN_LCDD2, NULL);
595 gpio_request(GPIO_FN_LCDD1, NULL);
596 gpio_request(GPIO_FN_LCDD0, NULL);
597 gpio_request(GPIO_FN_LCDLCLK, NULL);
598 gpio_request(GPIO_FN_LCDDCK, NULL);
599 gpio_request(GPIO_FN_LCDVEPWC, NULL);
600 gpio_request(GPIO_FN_LCDVCPWC, NULL);
601 gpio_request(GPIO_FN_LCDVSYN, NULL);
602 gpio_request(GPIO_FN_LCDHSYN, NULL);
603 gpio_request(GPIO_FN_LCDDISP, NULL);
604 gpio_request(GPIO_FN_LCDDON, NULL);
608 gpio_request(GPIO_FN_VIO_CLK2, NULL);
609 gpio_request(GPIO_FN_VIO_VD2, NULL);
610 gpio_request(GPIO_FN_VIO_HD2, NULL);
611 gpio_request(GPIO_FN_VIO_FLD, NULL);
612 gpio_request(GPIO_FN_VIO_CKO, NULL);
613 gpio_request(GPIO_FN_VIO_D15, NULL);
614 gpio_request(GPIO_FN_VIO_D14, NULL);
615 gpio_request(GPIO_FN_VIO_D13, NULL);
616 gpio_request(GPIO_FN_VIO_D12, NULL);
617 gpio_request(GPIO_FN_VIO_D11, NULL);
618 gpio_request(GPIO_FN_VIO_D10, NULL);
619 gpio_request(GPIO_FN_VIO_D9, NULL);
620 gpio_request(GPIO_FN_VIO_D8, NULL);
622 gpio_request(GPIO_PTT3, NULL); /* VIO_RST */
623 gpio_direction_output(GPIO_PTT3, 0);
624 gpio_request(GPIO_PTT2, NULL); /* TV_IN_EN */
625 gpio_direction_output(GPIO_PTT2, 1);
626 gpio_request(GPIO_PTT0, NULL); /* CAM_EN */
627 #ifdef CONFIG_SH_MIGOR_RTA_WVGA
628 gpio_direction_output(GPIO_PTT0, 0);
630 gpio_direction_output(GPIO_PTT0, 1);
632 __raw_writew(__raw_readw(PORT_MSELCRB) | 0x2000, PORT_MSELCRB); /* D15->D8 */
634 platform_resource_setup_memory(&migor_ceu_device, "ceu", 4 << 20);
637 gpio_request(GPIO_FN_SIUBOLR, NULL);
638 gpio_request(GPIO_FN_SIUBOBT, NULL);
639 gpio_request(GPIO_FN_SIUBISLD, NULL);
640 gpio_request(GPIO_FN_SIUBOSLD, NULL);
641 gpio_request(GPIO_FN_SIUMCKB, NULL);
644 * The original driver sets SIUB OLR/OBT, ILR/IBT, and SIUA OLR/OBT to
645 * output. Need only SIUB, set to output for master mode (table 34.2)
647 __raw_writew(__raw_readw(PORT_MSELCRA) | 1, PORT_MSELCRA);
649 i2c_register_board_info(0, migor_i2c_devices,
650 ARRAY_SIZE(migor_i2c_devices));
652 return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices));
654 arch_initcall(migor_devices_setup);
656 /* Return the board specific boot mode pin configuration */
657 static int migor_mode_pins(void)
659 /* MD0=1, MD1=1, MD2=0: Clock Mode 3
660 * MD3=0: 16-bit Area0 Bus Width
661 * MD5=1: Little Endian
662 * TSTMD=1, MD8=0: Test Mode Disabled
664 return MODE_PIN0 | MODE_PIN1 | MODE_PIN5;
670 static struct sh_machine_vector mv_migor __initmv = {
672 .mv_mode_pins = migor_mode_pins,