1 // SPDX-License-Identifier: GPL-2.0
3 * Access to PCI I/O memory from user space programs.
5 * Copyright IBM Corp. 2014
6 * Author(s): Alexey Ishchuk <aishchuk@linux.vnet.ibm.com>
8 #include <linux/kernel.h>
9 #include <linux/syscalls.h>
10 #include <linux/init.h>
12 #include <linux/errno.h>
13 #include <linux/pci.h>
14 #include <asm/pci_io.h>
15 #include <asm/pci_debug.h>
17 static inline void zpci_err_mmio(u8 cc, u8 status, u64 offset)
23 } data = {offset, cc, status};
25 zpci_err_hex(&data, sizeof(data));
28 static inline int __pcistb_mio_inuser(
29 void __iomem *ioaddr, const void __user *src,
36 "0: .insn rsy,0xeb00000000d4,%[len],%[ioaddr],%[src]\n"
40 EX_TABLE(0b, 2b) EX_TABLE(1b, 2b)
41 : [cc] "+d" (cc), [len] "+d" (len)
42 : [ioaddr] "a" (ioaddr), [src] "Q" (*((u8 __force *)src))
44 *status = len >> 24 & 0xff;
48 static inline int __pcistg_mio_inuser(
49 void __iomem *ioaddr, const void __user *src,
52 union register_pair ioaddr_len = {.even = (u64 __force)ioaddr, .odd = ulen};
59 * copy 0 < @len <= 8 bytes from @src into the right most bytes of
60 * a register, then store it to PCI at @ioaddr while in secondary
61 * address space. pcistg then uses the user mappings.
65 "0: llgc %[tmp],0(%[src])\n"
66 " sllg %[val],%[val],8\n"
68 " ogr %[val],%[tmp]\n"
70 "1: .insn rre,0xb9d40000,%[val],%[ioaddr_len]\n"
74 EX_TABLE(0b, 3b) EX_TABLE(1b, 3b) EX_TABLE(2b, 3b)
76 [src] "+a" (src), [cnt] "+d" (cnt),
77 [val] "+d" (val), [tmp] "=d" (tmp),
78 [cc] "+d" (cc), [ioaddr_len] "+&d" (ioaddr_len.pair)
80 *status = ioaddr_len.odd >> 24 & 0xff;
82 /* did we read everything from user memory? */
89 static inline int __memcpy_toio_inuser(void __iomem *dst,
90 const void __user *src, size_t n)
99 size = zpci_get_max_write_size((u64 __force) dst,
100 (u64 __force) src, n,
101 ZPCI_MAX_WRITE_SIZE);
102 if (size > 8) /* main path */
103 rc = __pcistb_mio_inuser(dst, src, size, &status);
105 rc = __pcistg_mio_inuser(dst, src, size, &status);
113 zpci_err_mmio(rc, status, (__force u64) dst);
117 SYSCALL_DEFINE3(s390_pci_mmio_write, unsigned long, mmio_addr,
118 const void __user *, user_buffer, size_t, length)
121 void __iomem *io_addr;
123 struct vm_area_struct *vma;
128 if (!zpci_is_enabled())
131 if (length <= 0 || PAGE_SIZE - (mmio_addr & ~PAGE_MASK) < length)
135 * We only support write access to MIO capable devices if we are on
136 * a MIO enabled system. Otherwise we would have to check for every
137 * address if it is a special ZPCI_ADDR and would have to do
138 * a pfn lookup which we don't need for MIO capable devices. Currently
139 * ISM devices are the only devices without MIO support and there is no
140 * known need for accessing these from userspace.
142 if (static_branch_likely(&have_mio)) {
143 ret = __memcpy_toio_inuser((void __iomem *) mmio_addr,
150 buf = kmalloc(length, GFP_KERNEL);
157 if (copy_from_user(buf, user_buffer, length))
160 mmap_read_lock(current->mm);
162 vma = vma_lookup(current->mm, mmio_addr);
164 goto out_unlock_mmap;
165 if (!(vma->vm_flags & (VM_IO | VM_PFNMAP)))
166 goto out_unlock_mmap;
168 if (!(vma->vm_flags & VM_WRITE))
169 goto out_unlock_mmap;
171 ret = follow_pte(vma->vm_mm, mmio_addr, &ptep, &ptl);
173 goto out_unlock_mmap;
175 io_addr = (void __iomem *)((pte_pfn(*ptep) << PAGE_SHIFT) |
176 (mmio_addr & ~PAGE_MASK));
178 if ((unsigned long) io_addr < ZPCI_IOMAP_ADDR_BASE)
181 ret = zpci_memcpy_toio(io_addr, buf, length);
183 pte_unmap_unlock(ptep, ptl);
185 mmap_read_unlock(current->mm);
187 if (buf != local_buf)
192 static inline int __pcilg_mio_inuser(
193 void __user *dst, const void __iomem *ioaddr,
194 u64 ulen, u8 *status)
196 union register_pair ioaddr_len = {.even = (u64 __force)ioaddr, .odd = ulen};
198 int shift = ulen * 8;
203 * read 0 < @len <= 8 bytes from the PCI memory mapped at @ioaddr (in
204 * user space) into a register using pcilg then store these bytes at
209 "0: .insn rre,0xb9d60000,%[val],%[ioaddr_len]\n"
214 "2: ahi %[shift],-8\n"
215 " srlg %[tmp],%[val],0(%[shift])\n"
216 "3: stc %[tmp],0(%[dst])\n"
220 EX_TABLE(0b, 4b) EX_TABLE(1b, 4b) EX_TABLE(3b, 4b)
222 [ioaddr_len] "+&d" (ioaddr_len.pair),
223 [cc] "+d" (cc), [val] "=d" (val),
224 [dst] "+a" (dst), [cnt] "+d" (cnt), [tmp] "=d" (tmp),
228 /* did we write everything to the user space buffer? */
232 *status = ioaddr_len.odd >> 24 & 0xff;
236 static inline int __memcpy_fromio_inuser(void __user *dst,
237 const void __iomem *src,
244 size = zpci_get_max_write_size((u64 __force) src,
245 (u64 __force) dst, n,
247 rc = __pcilg_mio_inuser(dst, src, size, &status);
255 zpci_err_mmio(rc, status, (__force u64) dst);
259 SYSCALL_DEFINE3(s390_pci_mmio_read, unsigned long, mmio_addr,
260 void __user *, user_buffer, size_t, length)
263 void __iomem *io_addr;
265 struct vm_area_struct *vma;
270 if (!zpci_is_enabled())
273 if (length <= 0 || PAGE_SIZE - (mmio_addr & ~PAGE_MASK) < length)
277 * We only support read access to MIO capable devices if we are on
278 * a MIO enabled system. Otherwise we would have to check for every
279 * address if it is a special ZPCI_ADDR and would have to do
280 * a pfn lookup which we don't need for MIO capable devices. Currently
281 * ISM devices are the only devices without MIO support and there is no
282 * known need for accessing these from userspace.
284 if (static_branch_likely(&have_mio)) {
285 ret = __memcpy_fromio_inuser(
286 user_buffer, (const void __iomem *)mmio_addr,
292 buf = kmalloc(length, GFP_KERNEL);
299 mmap_read_lock(current->mm);
301 vma = vma_lookup(current->mm, mmio_addr);
303 goto out_unlock_mmap;
304 if (!(vma->vm_flags & (VM_IO | VM_PFNMAP)))
305 goto out_unlock_mmap;
307 if (!(vma->vm_flags & VM_WRITE))
308 goto out_unlock_mmap;
310 ret = follow_pte(vma->vm_mm, mmio_addr, &ptep, &ptl);
312 goto out_unlock_mmap;
314 io_addr = (void __iomem *)((pte_pfn(*ptep) << PAGE_SHIFT) |
315 (mmio_addr & ~PAGE_MASK));
317 if ((unsigned long) io_addr < ZPCI_IOMAP_ADDR_BASE) {
321 ret = zpci_memcpy_fromio(buf, io_addr, length);
324 pte_unmap_unlock(ptep, ptl);
326 mmap_read_unlock(current->mm);
328 if (!ret && copy_to_user(user_buffer, buf, length))
331 if (buf != local_buf)