1 // SPDX-License-Identifier: GPL-2.0
3 * BPF Jit compiler for s390.
5 * Minimum build requirements:
7 * - HAVE_MARCH_Z196_FEATURES: laal, laalg
8 * - HAVE_MARCH_Z10_FEATURES: msfi, cgrj, clgrj
9 * - HAVE_MARCH_Z9_109_FEATURES: alfi, llilf, clfi, oilf, nilf
12 * Copyright IBM Corp. 2012,2015
14 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
15 * Michael Holzheu <holzheu@linux.vnet.ibm.com>
18 #define KMSG_COMPONENT "bpf_jit"
19 #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
21 #include <linux/netdevice.h>
22 #include <linux/filter.h>
23 #include <linux/init.h>
24 #include <linux/bpf.h>
26 #include <linux/kernel.h>
27 #include <asm/cacheflush.h>
28 #include <asm/extable.h>
30 #include <asm/facility.h>
31 #include <asm/nospec-branch.h>
32 #include <asm/set_memory.h>
33 #include <asm/text-patching.h>
37 u32 seen; /* Flags to remember seen eBPF instructions */
38 u32 seen_reg[16]; /* Array to remember which registers are used */
39 u32 *addrs; /* Array with relative instruction addresses */
40 u8 *prg_buf; /* Start of program */
41 int size; /* Size of program and literal pool */
42 int size_prg; /* Size of program */
43 int prg; /* Current position in program */
44 int lit32_start; /* Start of 32-bit literal pool */
45 int lit32; /* Current position in 32-bit literal pool */
46 int lit64_start; /* Start of 64-bit literal pool */
47 int lit64; /* Current position in 64-bit literal pool */
48 int base_ip; /* Base address for literal pool */
49 int exit_ip; /* Address of exit */
50 int r1_thunk_ip; /* Address of expoline thunk for 'br %r1' */
51 int r14_thunk_ip; /* Address of expoline thunk for 'br %r14' */
52 int tail_call_start; /* Tail call start offset */
53 int excnt; /* Number of exception table entries */
54 int prologue_plt_ret; /* Return address for prologue hotpatch PLT */
55 int prologue_plt; /* Start of prologue hotpatch PLT */
58 #define SEEN_MEM BIT(0) /* use mem[] for temporary storage */
59 #define SEEN_LITERAL BIT(1) /* code uses literals */
60 #define SEEN_FUNC BIT(2) /* calls C functions */
61 #define SEEN_STACK (SEEN_FUNC | SEEN_MEM)
66 #define REG_W0 (MAX_BPF_JIT_REG + 0) /* Work register 1 (even) */
67 #define REG_W1 (MAX_BPF_JIT_REG + 1) /* Work register 2 (odd) */
68 #define REG_L (MAX_BPF_JIT_REG + 2) /* Literal pool register */
69 #define REG_15 (MAX_BPF_JIT_REG + 3) /* Register 15 */
70 #define REG_0 REG_W0 /* Register 0 */
71 #define REG_1 REG_W1 /* Register 1 */
72 #define REG_2 BPF_REG_1 /* Register 2 */
73 #define REG_3 BPF_REG_2 /* Register 3 */
74 #define REG_4 BPF_REG_3 /* Register 4 */
75 #define REG_7 BPF_REG_6 /* Register 7 */
76 #define REG_8 BPF_REG_7 /* Register 8 */
77 #define REG_14 BPF_REG_0 /* Register 14 */
80 * Mapping of BPF registers to s390 registers
82 static const int reg2hex[] = {
85 /* Function parameters */
91 /* Call saved registers */
96 /* BPF stack pointer */
98 /* Register for blinding */
100 /* Work registers for s390x backend */
107 static inline u32 reg(u32 dst_reg, u32 src_reg)
109 return reg2hex[dst_reg] << 4 | reg2hex[src_reg];
112 static inline u32 reg_high(u32 reg)
114 return reg2hex[reg] << 4;
117 static inline void reg_set_seen(struct bpf_jit *jit, u32 b1)
119 u32 r1 = reg2hex[b1];
121 if (r1 >= 6 && r1 <= 15 && !jit->seen_reg[r1])
122 jit->seen_reg[r1] = 1;
125 #define REG_SET_SEEN(b1) \
127 reg_set_seen(jit, b1); \
130 #define REG_SEEN(b1) jit->seen_reg[reg2hex[(b1)]]
133 * EMIT macros for code generation
139 *(u16 *) (jit->prg_buf + jit->prg) = (op); \
143 #define EMIT2(op, b1, b2) \
145 _EMIT2((op) | reg(b1, b2)); \
153 *(u32 *) (jit->prg_buf + jit->prg) = (op); \
157 #define EMIT4(op, b1, b2) \
159 _EMIT4((op) | reg(b1, b2)); \
164 #define EMIT4_RRF(op, b1, b2, b3) \
166 _EMIT4((op) | reg_high(b3) << 8 | reg(b1, b2)); \
172 #define _EMIT4_DISP(op, disp) \
174 unsigned int __disp = (disp) & 0xfff; \
175 _EMIT4((op) | __disp); \
178 #define EMIT4_DISP(op, b1, b2, disp) \
180 _EMIT4_DISP((op) | reg_high(b1) << 16 | \
181 reg_high(b2) << 8, (disp)); \
186 #define EMIT4_IMM(op, b1, imm) \
188 unsigned int __imm = (imm) & 0xffff; \
189 _EMIT4((op) | reg_high(b1) << 16 | __imm); \
193 #define EMIT4_PCREL(op, pcrel) \
195 long __pcrel = ((pcrel) >> 1) & 0xffff; \
196 _EMIT4((op) | __pcrel); \
199 #define EMIT4_PCREL_RIC(op, mask, target) \
201 int __rel = ((target) - jit->prg) / 2; \
202 _EMIT4((op) | (mask) << 20 | (__rel & 0xffff)); \
205 #define _EMIT6(op1, op2) \
207 if (jit->prg_buf) { \
208 *(u32 *) (jit->prg_buf + jit->prg) = (op1); \
209 *(u16 *) (jit->prg_buf + jit->prg + 4) = (op2); \
214 #define _EMIT6_DISP(op1, op2, disp) \
216 unsigned int __disp = (disp) & 0xfff; \
217 _EMIT6((op1) | __disp, op2); \
220 #define _EMIT6_DISP_LH(op1, op2, disp) \
222 u32 _disp = (u32) (disp); \
223 unsigned int __disp_h = _disp & 0xff000; \
224 unsigned int __disp_l = _disp & 0x00fff; \
225 _EMIT6((op1) | __disp_l, (op2) | __disp_h >> 4); \
228 #define EMIT6_DISP_LH(op1, op2, b1, b2, b3, disp) \
230 _EMIT6_DISP_LH((op1) | reg(b1, b2) << 16 | \
231 reg_high(b3) << 8, op2, disp); \
237 #define EMIT6_PCREL_RIEB(op1, op2, b1, b2, mask, target) \
239 unsigned int rel = (int)((target) - jit->prg) / 2; \
240 _EMIT6((op1) | reg(b1, b2) << 16 | (rel & 0xffff), \
241 (op2) | (mask) << 12); \
246 #define EMIT6_PCREL_RIEC(op1, op2, b1, imm, mask, target) \
248 unsigned int rel = (int)((target) - jit->prg) / 2; \
249 _EMIT6((op1) | (reg_high(b1) | (mask)) << 16 | \
250 (rel & 0xffff), (op2) | ((imm) & 0xff) << 8); \
252 BUILD_BUG_ON(((unsigned long) (imm)) > 0xff); \
255 #define EMIT6_PCREL(op1, op2, b1, b2, i, off, mask) \
257 int rel = (addrs[(i) + (off) + 1] - jit->prg) / 2; \
258 _EMIT6((op1) | reg(b1, b2) << 16 | (rel & 0xffff), (op2) | (mask));\
263 #define EMIT6_PCREL_RILB(op, b, target) \
265 unsigned int rel = (int)((target) - jit->prg) / 2; \
266 _EMIT6((op) | reg_high(b) << 16 | rel >> 16, rel & 0xffff);\
270 #define EMIT6_PCREL_RIL(op, target) \
272 unsigned int rel = (int)((target) - jit->prg) / 2; \
273 _EMIT6((op) | rel >> 16, rel & 0xffff); \
276 #define EMIT6_PCREL_RILC(op, mask, target) \
278 EMIT6_PCREL_RIL((op) | (mask) << 20, (target)); \
281 #define _EMIT6_IMM(op, imm) \
283 unsigned int __imm = (imm); \
284 _EMIT6((op) | (__imm >> 16), __imm & 0xffff); \
287 #define EMIT6_IMM(op, b1, imm) \
289 _EMIT6_IMM((op) | reg_high(b1) << 16, imm); \
293 #define _EMIT_CONST_U32(val) \
298 *(u32 *)(jit->prg_buf + jit->lit32) = (u32)(val);\
303 #define EMIT_CONST_U32(val) \
305 jit->seen |= SEEN_LITERAL; \
306 _EMIT_CONST_U32(val) - jit->base_ip; \
309 #define _EMIT_CONST_U64(val) \
314 *(u64 *)(jit->prg_buf + jit->lit64) = (u64)(val);\
319 #define EMIT_CONST_U64(val) \
321 jit->seen |= SEEN_LITERAL; \
322 _EMIT_CONST_U64(val) - jit->base_ip; \
325 #define EMIT_ZERO(b1) \
327 if (!fp->aux->verifier_zext) { \
328 /* llgfr %dst,%dst (zero extend to 64 bit) */ \
329 EMIT4(0xb9160000, b1, b1); \
335 * Return whether this is the first pass. The first pass is special, since we
336 * don't know any sizes yet, and thus must be conservative.
338 static bool is_first_pass(struct bpf_jit *jit)
340 return jit->size == 0;
344 * Return whether this is the code generation pass. The code generation pass is
345 * special, since we should change as little as possible.
347 static bool is_codegen_pass(struct bpf_jit *jit)
353 * Return whether "rel" can be encoded as a short PC-relative offset
355 static bool is_valid_rel(int rel)
357 return rel >= -65536 && rel <= 65534;
361 * Return whether "off" can be reached using a short PC-relative offset
363 static bool can_use_rel(struct bpf_jit *jit, int off)
365 return is_valid_rel(off - jit->prg);
369 * Return whether given displacement can be encoded using
370 * Long-Displacement Facility
372 static bool is_valid_ldisp(int disp)
374 return disp >= -524288 && disp <= 524287;
378 * Return whether the next 32-bit literal pool entry can be referenced using
379 * Long-Displacement Facility
381 static bool can_use_ldisp_for_lit32(struct bpf_jit *jit)
383 return is_valid_ldisp(jit->lit32 - jit->base_ip);
387 * Return whether the next 64-bit literal pool entry can be referenced using
388 * Long-Displacement Facility
390 static bool can_use_ldisp_for_lit64(struct bpf_jit *jit)
392 return is_valid_ldisp(jit->lit64 - jit->base_ip);
396 * Fill whole space with illegal instructions
398 static void jit_fill_hole(void *area, unsigned int size)
400 memset(area, 0, size);
404 * Save registers from "rs" (register start) to "re" (register end) on stack
406 static void save_regs(struct bpf_jit *jit, u32 rs, u32 re)
408 u32 off = STK_OFF_R6 + (rs - 6) * 8;
411 /* stg %rs,off(%r15) */
412 _EMIT6(0xe300f000 | rs << 20 | off, 0x0024);
414 /* stmg %rs,%re,off(%r15) */
415 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0024, off);
419 * Restore registers from "rs" (register start) to "re" (register end) on stack
421 static void restore_regs(struct bpf_jit *jit, u32 rs, u32 re, u32 stack_depth)
423 u32 off = STK_OFF_R6 + (rs - 6) * 8;
425 if (jit->seen & SEEN_STACK)
426 off += STK_OFF + stack_depth;
429 /* lg %rs,off(%r15) */
430 _EMIT6(0xe300f000 | rs << 20 | off, 0x0004);
432 /* lmg %rs,%re,off(%r15) */
433 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0004, off);
437 * Return first seen register (from start)
439 static int get_start(struct bpf_jit *jit, int start)
443 for (i = start; i <= 15; i++) {
444 if (jit->seen_reg[i])
451 * Return last seen register (from start) (gap >= 2)
453 static int get_end(struct bpf_jit *jit, int start)
457 for (i = start; i < 15; i++) {
458 if (!jit->seen_reg[i] && !jit->seen_reg[i + 1])
461 return jit->seen_reg[15] ? 15 : 14;
465 #define REGS_RESTORE 0
467 * Save and restore clobbered registers (6-15) on stack.
468 * We save/restore registers in chunks with gap >= 2 registers.
470 static void save_restore_regs(struct bpf_jit *jit, int op, u32 stack_depth)
472 const int last = 15, save_restore_size = 6;
475 if (is_first_pass(jit)) {
477 * We don't know yet which registers are used. Reserve space
480 jit->prg += (last - re + 1) * save_restore_size;
485 rs = get_start(jit, re);
488 re = get_end(jit, rs + 1);
490 save_regs(jit, rs, re);
492 restore_regs(jit, rs, re, stack_depth);
494 } while (re <= last);
497 static void bpf_skip(struct bpf_jit *jit, int size)
499 if (size >= 6 && !is_valid_rel(size)) {
501 EMIT6_PCREL_RIL(0xc0f4000000, size);
503 } else if (size >= 4 && is_valid_rel(size)) {
505 EMIT4_PCREL(0xa7f40000, size);
516 * PLT for hotpatchable calls. The calling convention is the same as for the
517 * ftrace hotpatch trampolines: %r0 is return address, %r1 is clobbered.
519 extern const char bpf_plt[];
520 extern const char bpf_plt_ret[];
521 extern const char bpf_plt_target[];
522 extern const char bpf_plt_end[];
523 #define BPF_PLT_SIZE 32
525 ".pushsection .rodata\n"
528 " lgrl %r0,bpf_plt_ret\n"
529 " lgrl %r1,bpf_plt_target\n"
532 "bpf_plt_ret: .quad 0\n"
533 "bpf_plt_target: .quad 0\n"
538 static void bpf_jit_plt(void *plt, void *ret, void *target)
540 memcpy(plt, bpf_plt, BPF_PLT_SIZE);
541 *(void **)((char *)plt + (bpf_plt_ret - bpf_plt)) = ret;
542 *(void **)((char *)plt + (bpf_plt_target - bpf_plt)) = target;
546 * Emit function prologue
548 * Save registers and create stack frame if necessary.
549 * See stack frame layout description in "bpf_jit.h"!
551 static void bpf_jit_prologue(struct bpf_jit *jit, struct bpf_prog *fp,
554 /* No-op for hotpatching */
555 /* brcl 0,prologue_plt */
556 EMIT6_PCREL_RILC(0xc0040000, 0, jit->prologue_plt);
557 jit->prologue_plt_ret = jit->prg;
559 if (fp->aux->func_idx == 0) {
560 /* Initialize the tail call counter in the main program. */
561 /* xc STK_OFF_TCCNT(4,%r15),STK_OFF_TCCNT(%r15) */
562 _EMIT6(0xd703f000 | STK_OFF_TCCNT, 0xf000 | STK_OFF_TCCNT);
565 * Skip the tail call counter initialization in subprograms.
566 * Insert nops in order to have tail_call_start at a
567 * predictable offset.
571 /* Tail calls have to skip above initialization */
572 jit->tail_call_start = jit->prg;
574 save_restore_regs(jit, REGS_SAVE, stack_depth);
575 /* Setup literal pool */
576 if (is_first_pass(jit) || (jit->seen & SEEN_LITERAL)) {
577 if (!is_first_pass(jit) &&
578 is_valid_ldisp(jit->size - (jit->prg + 2))) {
580 EMIT2(0x0d00, REG_L, REG_0);
581 jit->base_ip = jit->prg;
583 /* larl %l,lit32_start */
584 EMIT6_PCREL_RILB(0xc0000000, REG_L, jit->lit32_start);
585 jit->base_ip = jit->lit32_start;
588 /* Setup stack and backchain */
589 if (is_first_pass(jit) || (jit->seen & SEEN_STACK)) {
590 if (is_first_pass(jit) || (jit->seen & SEEN_FUNC))
591 /* lgr %w1,%r15 (backchain) */
592 EMIT4(0xb9040000, REG_W1, REG_15);
593 /* la %bfp,STK_160_UNUSED(%r15) (BPF frame pointer) */
594 EMIT4_DISP(0x41000000, BPF_REG_FP, REG_15, STK_160_UNUSED);
595 /* aghi %r15,-STK_OFF */
596 EMIT4_IMM(0xa70b0000, REG_15, -(STK_OFF + stack_depth));
597 if (is_first_pass(jit) || (jit->seen & SEEN_FUNC))
598 /* stg %w1,152(%r15) (backchain) */
599 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1, REG_0,
605 * Emit an expoline for a jump that follows
607 static void emit_expoline(struct bpf_jit *jit)
610 EMIT6_PCREL_RIL(0xc6000000, jit->prg + 10);
612 EMIT4_PCREL(0xa7f40000, 0);
616 * Emit __s390_indirect_jump_r1 thunk if necessary
618 static void emit_r1_thunk(struct bpf_jit *jit)
620 if (nospec_uses_trampoline()) {
621 jit->r1_thunk_ip = jit->prg;
629 * Call r1 either directly or via __s390_indirect_jump_r1 thunk
631 static void call_r1(struct bpf_jit *jit)
633 if (nospec_uses_trampoline())
634 /* brasl %r14,__s390_indirect_jump_r1 */
635 EMIT6_PCREL_RILB(0xc0050000, REG_14, jit->r1_thunk_ip);
638 EMIT2(0x0d00, REG_14, REG_1);
644 static void bpf_jit_epilogue(struct bpf_jit *jit, u32 stack_depth)
646 jit->exit_ip = jit->prg;
647 /* Load exit code: lgr %r2,%b0 */
648 EMIT4(0xb9040000, REG_2, BPF_REG_0);
649 /* Restore registers */
650 save_restore_regs(jit, REGS_RESTORE, stack_depth);
651 if (nospec_uses_trampoline()) {
652 jit->r14_thunk_ip = jit->prg;
653 /* Generate __s390_indirect_jump_r14 thunk */
659 if (is_first_pass(jit) || (jit->seen & SEEN_FUNC))
662 jit->prg = ALIGN(jit->prg, 8);
663 jit->prologue_plt = jit->prg;
665 bpf_jit_plt(jit->prg_buf + jit->prg,
666 jit->prg_buf + jit->prologue_plt_ret, NULL);
667 jit->prg += BPF_PLT_SIZE;
670 static int get_probe_mem_regno(const u8 *insn)
673 * insn must point to llgc, llgh, llgf or lg, which have destination
674 * register at the same position.
676 if (insn[0] != 0xe3) /* common llgc, llgh, llgf and lg prefix */
678 if (insn[5] != 0x90 && /* llgc */
679 insn[5] != 0x91 && /* llgh */
680 insn[5] != 0x16 && /* llgf */
681 insn[5] != 0x04) /* lg */
686 bool ex_handler_bpf(const struct exception_table_entry *x, struct pt_regs *regs)
688 regs->psw.addr = extable_fixup(x);
689 regs->gprs[x->data] = 0;
693 static int bpf_jit_probe_mem(struct bpf_jit *jit, struct bpf_prog *fp,
694 int probe_prg, int nop_prg)
696 struct exception_table_entry *ex;
702 if (!fp->aux->extable)
703 /* Do nothing during early JIT passes. */
705 insn = jit->prg_buf + probe_prg;
706 reg = get_probe_mem_regno(insn);
707 if (WARN_ON_ONCE(reg < 0))
708 /* JIT bug - unexpected probe instruction. */
710 if (WARN_ON_ONCE(probe_prg + insn_length(*insn) != nop_prg))
711 /* JIT bug - gap between probe and nop instructions. */
713 for (i = 0; i < 2; i++) {
714 if (WARN_ON_ONCE(jit->excnt >= fp->aux->num_exentries))
715 /* Verifier bug - not enough entries. */
717 ex = &fp->aux->extable[jit->excnt];
718 /* Add extable entries for probe and nop instructions. */
719 prg = i == 0 ? probe_prg : nop_prg;
720 delta = jit->prg_buf + prg - (u8 *)&ex->insn;
721 if (WARN_ON_ONCE(delta < INT_MIN || delta > INT_MAX))
722 /* JIT bug - code and extable must be close. */
726 * Always land on the nop. Note that extable infrastructure
727 * ignores fixup field, it is handled by ex_handler_bpf().
729 delta = jit->prg_buf + nop_prg - (u8 *)&ex->fixup;
730 if (WARN_ON_ONCE(delta < INT_MIN || delta > INT_MAX))
731 /* JIT bug - landing pad and extable must be close. */
734 ex->type = EX_TYPE_BPF;
742 * Sign-extend the register if necessary
744 static int sign_extend(struct bpf_jit *jit, int r, u8 size, u8 flags)
746 if (!(flags & BTF_FMODEL_SIGNED_ARG))
752 EMIT4(0xb9060000, r, r);
756 EMIT4(0xb9070000, r, r);
760 EMIT4(0xb9140000, r, r);
770 * Compile one eBPF instruction into s390x code
772 * NOTE: Use noinline because for gcov (-fprofile-arcs) gcc allocates a lot of
773 * stack space for the large switch statement.
775 static noinline int bpf_jit_insn(struct bpf_jit *jit, struct bpf_prog *fp,
776 int i, bool extra_pass, u32 stack_depth)
778 struct bpf_insn *insn = &fp->insnsi[i];
779 u32 dst_reg = insn->dst_reg;
780 u32 src_reg = insn->src_reg;
781 int last, insn_count = 1;
782 u32 *addrs = jit->addrs;
790 if (BPF_CLASS(insn->code) == BPF_LDX &&
791 BPF_MODE(insn->code) == BPF_PROBE_MEM)
792 probe_prg = jit->prg;
794 switch (insn->code) {
798 case BPF_ALU | BPF_MOV | BPF_X: /* dst = (u32) src */
799 /* llgfr %dst,%src */
800 EMIT4(0xb9160000, dst_reg, src_reg);
801 if (insn_is_zext(&insn[1]))
804 case BPF_ALU64 | BPF_MOV | BPF_X: /* dst = src */
806 EMIT4(0xb9040000, dst_reg, src_reg);
808 case BPF_ALU | BPF_MOV | BPF_K: /* dst = (u32) imm */
810 EMIT6_IMM(0xc00f0000, dst_reg, imm);
811 if (insn_is_zext(&insn[1]))
814 case BPF_ALU64 | BPF_MOV | BPF_K: /* dst = imm */
816 EMIT6_IMM(0xc0010000, dst_reg, imm);
821 case BPF_LD | BPF_IMM | BPF_DW: /* dst = (u64) imm */
823 /* 16 byte instruction that uses two 'struct bpf_insn' */
826 imm64 = (u64)(u32) insn[0].imm | ((u64)(u32) insn[1].imm) << 32;
828 EMIT6_PCREL_RILB(0xc4080000, dst_reg, _EMIT_CONST_U64(imm64));
835 case BPF_ALU | BPF_ADD | BPF_X: /* dst = (u32) dst + (u32) src */
837 EMIT2(0x1a00, dst_reg, src_reg);
840 case BPF_ALU64 | BPF_ADD | BPF_X: /* dst = dst + src */
842 EMIT4(0xb9080000, dst_reg, src_reg);
844 case BPF_ALU | BPF_ADD | BPF_K: /* dst = (u32) dst + (u32) imm */
847 EMIT6_IMM(0xc20b0000, dst_reg, imm);
851 case BPF_ALU64 | BPF_ADD | BPF_K: /* dst = dst + imm */
855 EMIT6_IMM(0xc2080000, dst_reg, imm);
860 case BPF_ALU | BPF_SUB | BPF_X: /* dst = (u32) dst - (u32) src */
862 EMIT2(0x1b00, dst_reg, src_reg);
865 case BPF_ALU64 | BPF_SUB | BPF_X: /* dst = dst - src */
867 EMIT4(0xb9090000, dst_reg, src_reg);
869 case BPF_ALU | BPF_SUB | BPF_K: /* dst = (u32) dst - (u32) imm */
872 EMIT6_IMM(0xc20b0000, dst_reg, -imm);
876 case BPF_ALU64 | BPF_SUB | BPF_K: /* dst = dst - imm */
879 if (imm == -0x80000000) {
880 /* algfi %dst,0x80000000 */
881 EMIT6_IMM(0xc20a0000, dst_reg, 0x80000000);
884 EMIT6_IMM(0xc2080000, dst_reg, -imm);
890 case BPF_ALU | BPF_MUL | BPF_X: /* dst = (u32) dst * (u32) src */
892 EMIT4(0xb2520000, dst_reg, src_reg);
895 case BPF_ALU64 | BPF_MUL | BPF_X: /* dst = dst * src */
897 EMIT4(0xb90c0000, dst_reg, src_reg);
899 case BPF_ALU | BPF_MUL | BPF_K: /* dst = (u32) dst * (u32) imm */
902 EMIT6_IMM(0xc2010000, dst_reg, imm);
906 case BPF_ALU64 | BPF_MUL | BPF_K: /* dst = dst * imm */
910 EMIT6_IMM(0xc2000000, dst_reg, imm);
915 case BPF_ALU | BPF_DIV | BPF_X: /* dst = (u32) dst / (u32) src */
916 case BPF_ALU | BPF_MOD | BPF_X: /* dst = (u32) dst % (u32) src */
918 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
921 EMIT4_IMM(0xa7080000, REG_W0, 0);
923 EMIT2(0x1800, REG_W1, dst_reg);
925 EMIT4(0xb9970000, REG_W0, src_reg);
927 EMIT4(0xb9160000, dst_reg, rc_reg);
928 if (insn_is_zext(&insn[1]))
932 case BPF_ALU64 | BPF_DIV | BPF_X: /* dst = dst / src */
933 case BPF_ALU64 | BPF_MOD | BPF_X: /* dst = dst % src */
935 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
938 EMIT4_IMM(0xa7090000, REG_W0, 0);
940 EMIT4(0xb9040000, REG_W1, dst_reg);
942 EMIT4(0xb9870000, REG_W0, src_reg);
944 EMIT4(0xb9040000, dst_reg, rc_reg);
947 case BPF_ALU | BPF_DIV | BPF_K: /* dst = (u32) dst / (u32) imm */
948 case BPF_ALU | BPF_MOD | BPF_K: /* dst = (u32) dst % (u32) imm */
950 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
953 if (BPF_OP(insn->code) == BPF_MOD)
955 EMIT4_IMM(0xa7090000, dst_reg, 0);
961 EMIT4_IMM(0xa7080000, REG_W0, 0);
963 EMIT2(0x1800, REG_W1, dst_reg);
964 if (!is_first_pass(jit) && can_use_ldisp_for_lit32(jit)) {
965 /* dl %w0,<d(imm)>(%l) */
966 EMIT6_DISP_LH(0xe3000000, 0x0097, REG_W0, REG_0, REG_L,
967 EMIT_CONST_U32(imm));
970 EMIT6_PCREL_RILB(0xc40c0000, dst_reg,
971 _EMIT_CONST_U32(imm));
972 jit->seen |= SEEN_LITERAL;
974 EMIT4(0xb9970000, REG_W0, dst_reg);
977 EMIT4(0xb9160000, dst_reg, rc_reg);
978 if (insn_is_zext(&insn[1]))
982 case BPF_ALU64 | BPF_DIV | BPF_K: /* dst = dst / imm */
983 case BPF_ALU64 | BPF_MOD | BPF_K: /* dst = dst % imm */
985 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;
988 if (BPF_OP(insn->code) == BPF_MOD)
990 EMIT4_IMM(0xa7090000, dst_reg, 0);
994 EMIT4_IMM(0xa7090000, REG_W0, 0);
996 EMIT4(0xb9040000, REG_W1, dst_reg);
997 if (!is_first_pass(jit) && can_use_ldisp_for_lit64(jit)) {
998 /* dlg %w0,<d(imm)>(%l) */
999 EMIT6_DISP_LH(0xe3000000, 0x0087, REG_W0, REG_0, REG_L,
1000 EMIT_CONST_U64(imm));
1003 EMIT6_PCREL_RILB(0xc4080000, dst_reg,
1004 _EMIT_CONST_U64(imm));
1005 jit->seen |= SEEN_LITERAL;
1007 EMIT4(0xb9870000, REG_W0, dst_reg);
1010 EMIT4(0xb9040000, dst_reg, rc_reg);
1016 case BPF_ALU | BPF_AND | BPF_X: /* dst = (u32) dst & (u32) src */
1018 EMIT2(0x1400, dst_reg, src_reg);
1021 case BPF_ALU64 | BPF_AND | BPF_X: /* dst = dst & src */
1023 EMIT4(0xb9800000, dst_reg, src_reg);
1025 case BPF_ALU | BPF_AND | BPF_K: /* dst = (u32) dst & (u32) imm */
1027 EMIT6_IMM(0xc00b0000, dst_reg, imm);
1030 case BPF_ALU64 | BPF_AND | BPF_K: /* dst = dst & imm */
1031 if (!is_first_pass(jit) && can_use_ldisp_for_lit64(jit)) {
1032 /* ng %dst,<d(imm)>(%l) */
1033 EMIT6_DISP_LH(0xe3000000, 0x0080,
1034 dst_reg, REG_0, REG_L,
1035 EMIT_CONST_U64(imm));
1038 EMIT6_PCREL_RILB(0xc4080000, REG_W0,
1039 _EMIT_CONST_U64(imm));
1040 jit->seen |= SEEN_LITERAL;
1042 EMIT4(0xb9800000, dst_reg, REG_W0);
1048 case BPF_ALU | BPF_OR | BPF_X: /* dst = (u32) dst | (u32) src */
1050 EMIT2(0x1600, dst_reg, src_reg);
1053 case BPF_ALU64 | BPF_OR | BPF_X: /* dst = dst | src */
1055 EMIT4(0xb9810000, dst_reg, src_reg);
1057 case BPF_ALU | BPF_OR | BPF_K: /* dst = (u32) dst | (u32) imm */
1059 EMIT6_IMM(0xc00d0000, dst_reg, imm);
1062 case BPF_ALU64 | BPF_OR | BPF_K: /* dst = dst | imm */
1063 if (!is_first_pass(jit) && can_use_ldisp_for_lit64(jit)) {
1064 /* og %dst,<d(imm)>(%l) */
1065 EMIT6_DISP_LH(0xe3000000, 0x0081,
1066 dst_reg, REG_0, REG_L,
1067 EMIT_CONST_U64(imm));
1070 EMIT6_PCREL_RILB(0xc4080000, REG_W0,
1071 _EMIT_CONST_U64(imm));
1072 jit->seen |= SEEN_LITERAL;
1074 EMIT4(0xb9810000, dst_reg, REG_W0);
1080 case BPF_ALU | BPF_XOR | BPF_X: /* dst = (u32) dst ^ (u32) src */
1082 EMIT2(0x1700, dst_reg, src_reg);
1085 case BPF_ALU64 | BPF_XOR | BPF_X: /* dst = dst ^ src */
1087 EMIT4(0xb9820000, dst_reg, src_reg);
1089 case BPF_ALU | BPF_XOR | BPF_K: /* dst = (u32) dst ^ (u32) imm */
1092 EMIT6_IMM(0xc0070000, dst_reg, imm);
1096 case BPF_ALU64 | BPF_XOR | BPF_K: /* dst = dst ^ imm */
1097 if (!is_first_pass(jit) && can_use_ldisp_for_lit64(jit)) {
1098 /* xg %dst,<d(imm)>(%l) */
1099 EMIT6_DISP_LH(0xe3000000, 0x0082,
1100 dst_reg, REG_0, REG_L,
1101 EMIT_CONST_U64(imm));
1104 EMIT6_PCREL_RILB(0xc4080000, REG_W0,
1105 _EMIT_CONST_U64(imm));
1106 jit->seen |= SEEN_LITERAL;
1108 EMIT4(0xb9820000, dst_reg, REG_W0);
1114 case BPF_ALU | BPF_LSH | BPF_X: /* dst = (u32) dst << (u32) src */
1115 /* sll %dst,0(%src) */
1116 EMIT4_DISP(0x89000000, dst_reg, src_reg, 0);
1119 case BPF_ALU64 | BPF_LSH | BPF_X: /* dst = dst << src */
1120 /* sllg %dst,%dst,0(%src) */
1121 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, src_reg, 0);
1123 case BPF_ALU | BPF_LSH | BPF_K: /* dst = (u32) dst << (u32) imm */
1125 /* sll %dst,imm(%r0) */
1126 EMIT4_DISP(0x89000000, dst_reg, REG_0, imm);
1130 case BPF_ALU64 | BPF_LSH | BPF_K: /* dst = dst << imm */
1133 /* sllg %dst,%dst,imm(%r0) */
1134 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, REG_0, imm);
1139 case BPF_ALU | BPF_RSH | BPF_X: /* dst = (u32) dst >> (u32) src */
1140 /* srl %dst,0(%src) */
1141 EMIT4_DISP(0x88000000, dst_reg, src_reg, 0);
1144 case BPF_ALU64 | BPF_RSH | BPF_X: /* dst = dst >> src */
1145 /* srlg %dst,%dst,0(%src) */
1146 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, src_reg, 0);
1148 case BPF_ALU | BPF_RSH | BPF_K: /* dst = (u32) dst >> (u32) imm */
1150 /* srl %dst,imm(%r0) */
1151 EMIT4_DISP(0x88000000, dst_reg, REG_0, imm);
1155 case BPF_ALU64 | BPF_RSH | BPF_K: /* dst = dst >> imm */
1158 /* srlg %dst,%dst,imm(%r0) */
1159 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, REG_0, imm);
1164 case BPF_ALU | BPF_ARSH | BPF_X: /* ((s32) dst) >>= src */
1165 /* sra %dst,%dst,0(%src) */
1166 EMIT4_DISP(0x8a000000, dst_reg, src_reg, 0);
1169 case BPF_ALU64 | BPF_ARSH | BPF_X: /* ((s64) dst) >>= src */
1170 /* srag %dst,%dst,0(%src) */
1171 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, src_reg, 0);
1173 case BPF_ALU | BPF_ARSH | BPF_K: /* ((s32) dst >> imm */
1175 /* sra %dst,imm(%r0) */
1176 EMIT4_DISP(0x8a000000, dst_reg, REG_0, imm);
1180 case BPF_ALU64 | BPF_ARSH | BPF_K: /* ((s64) dst) >>= imm */
1183 /* srag %dst,%dst,imm(%r0) */
1184 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, REG_0, imm);
1189 case BPF_ALU | BPF_NEG: /* dst = (u32) -dst */
1191 EMIT2(0x1300, dst_reg, dst_reg);
1194 case BPF_ALU64 | BPF_NEG: /* dst = -dst */
1195 /* lcgr %dst,%dst */
1196 EMIT4(0xb9030000, dst_reg, dst_reg);
1201 case BPF_ALU | BPF_END | BPF_FROM_BE:
1202 /* s390 is big endian, therefore only clear high order bytes */
1204 case 16: /* dst = (u16) cpu_to_be16(dst) */
1205 /* llghr %dst,%dst */
1206 EMIT4(0xb9850000, dst_reg, dst_reg);
1207 if (insn_is_zext(&insn[1]))
1210 case 32: /* dst = (u32) cpu_to_be32(dst) */
1211 if (!fp->aux->verifier_zext)
1212 /* llgfr %dst,%dst */
1213 EMIT4(0xb9160000, dst_reg, dst_reg);
1215 case 64: /* dst = (u64) cpu_to_be64(dst) */
1219 case BPF_ALU | BPF_END | BPF_FROM_LE:
1221 case 16: /* dst = (u16) cpu_to_le16(dst) */
1222 /* lrvr %dst,%dst */
1223 EMIT4(0xb91f0000, dst_reg, dst_reg);
1224 /* srl %dst,16(%r0) */
1225 EMIT4_DISP(0x88000000, dst_reg, REG_0, 16);
1226 /* llghr %dst,%dst */
1227 EMIT4(0xb9850000, dst_reg, dst_reg);
1228 if (insn_is_zext(&insn[1]))
1231 case 32: /* dst = (u32) cpu_to_le32(dst) */
1232 /* lrvr %dst,%dst */
1233 EMIT4(0xb91f0000, dst_reg, dst_reg);
1234 if (!fp->aux->verifier_zext)
1235 /* llgfr %dst,%dst */
1236 EMIT4(0xb9160000, dst_reg, dst_reg);
1238 case 64: /* dst = (u64) cpu_to_le64(dst) */
1239 /* lrvgr %dst,%dst */
1240 EMIT4(0xb90f0000, dst_reg, dst_reg);
1245 * BPF_NOSPEC (speculation barrier)
1247 case BPF_ST | BPF_NOSPEC:
1252 case BPF_STX | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = src_reg */
1253 /* stcy %src,off(%dst) */
1254 EMIT6_DISP_LH(0xe3000000, 0x0072, src_reg, dst_reg, REG_0, off);
1255 jit->seen |= SEEN_MEM;
1257 case BPF_STX | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = src */
1258 /* sthy %src,off(%dst) */
1259 EMIT6_DISP_LH(0xe3000000, 0x0070, src_reg, dst_reg, REG_0, off);
1260 jit->seen |= SEEN_MEM;
1262 case BPF_STX | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = src */
1263 /* sty %src,off(%dst) */
1264 EMIT6_DISP_LH(0xe3000000, 0x0050, src_reg, dst_reg, REG_0, off);
1265 jit->seen |= SEEN_MEM;
1267 case BPF_STX | BPF_MEM | BPF_DW: /* (u64 *)(dst + off) = src */
1268 /* stg %src,off(%dst) */
1269 EMIT6_DISP_LH(0xe3000000, 0x0024, src_reg, dst_reg, REG_0, off);
1270 jit->seen |= SEEN_MEM;
1272 case BPF_ST | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = imm */
1274 EMIT4_IMM(0xa7080000, REG_W0, (u8) imm);
1275 /* stcy %w0,off(dst) */
1276 EMIT6_DISP_LH(0xe3000000, 0x0072, REG_W0, dst_reg, REG_0, off);
1277 jit->seen |= SEEN_MEM;
1279 case BPF_ST | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = imm */
1281 EMIT4_IMM(0xa7080000, REG_W0, (u16) imm);
1282 /* sthy %w0,off(dst) */
1283 EMIT6_DISP_LH(0xe3000000, 0x0070, REG_W0, dst_reg, REG_0, off);
1284 jit->seen |= SEEN_MEM;
1286 case BPF_ST | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = imm */
1288 EMIT6_IMM(0xc00f0000, REG_W0, (u32) imm);
1289 /* sty %w0,off(%dst) */
1290 EMIT6_DISP_LH(0xe3000000, 0x0050, REG_W0, dst_reg, REG_0, off);
1291 jit->seen |= SEEN_MEM;
1293 case BPF_ST | BPF_MEM | BPF_DW: /* *(u64 *)(dst + off) = imm */
1295 EMIT6_IMM(0xc0010000, REG_W0, imm);
1296 /* stg %w0,off(%dst) */
1297 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W0, dst_reg, REG_0, off);
1298 jit->seen |= SEEN_MEM;
1303 case BPF_STX | BPF_ATOMIC | BPF_DW:
1304 case BPF_STX | BPF_ATOMIC | BPF_W:
1306 bool is32 = BPF_SIZE(insn->code) == BPF_W;
1308 switch (insn->imm) {
1309 /* {op32|op64} {%w0|%src},%src,off(%dst) */
1310 #define EMIT_ATOMIC(op32, op64) do { \
1311 EMIT6_DISP_LH(0xeb000000, is32 ? (op32) : (op64), \
1312 (insn->imm & BPF_FETCH) ? src_reg : REG_W0, \
1313 src_reg, dst_reg, off); \
1314 if (is32 && (insn->imm & BPF_FETCH)) \
1315 EMIT_ZERO(src_reg); \
1318 case BPF_ADD | BPF_FETCH:
1320 EMIT_ATOMIC(0x00fa, 0x00ea);
1323 case BPF_AND | BPF_FETCH:
1325 EMIT_ATOMIC(0x00f4, 0x00e4);
1328 case BPF_OR | BPF_FETCH:
1330 EMIT_ATOMIC(0x00f6, 0x00e6);
1333 case BPF_XOR | BPF_FETCH:
1335 EMIT_ATOMIC(0x00f7, 0x00e7);
1339 /* {ly|lg} %w0,off(%dst) */
1340 EMIT6_DISP_LH(0xe3000000,
1341 is32 ? 0x0058 : 0x0004, REG_W0, REG_0,
1343 /* 0: {csy|csg} %w0,%src,off(%dst) */
1344 EMIT6_DISP_LH(0xeb000000, is32 ? 0x0014 : 0x0030,
1345 REG_W0, src_reg, dst_reg, off);
1347 EMIT4_PCREL_RIC(0xa7040000, 4, jit->prg - 6);
1348 /* {llgfr|lgr} %src,%w0 */
1349 EMIT4(is32 ? 0xb9160000 : 0xb9040000, src_reg, REG_W0);
1350 if (is32 && insn_is_zext(&insn[1]))
1354 /* 0: {csy|csg} %b0,%src,off(%dst) */
1355 EMIT6_DISP_LH(0xeb000000, is32 ? 0x0014 : 0x0030,
1356 BPF_REG_0, src_reg, dst_reg, off);
1359 pr_err("Unknown atomic operation %02x\n", insn->imm);
1363 jit->seen |= SEEN_MEM;
1369 case BPF_LDX | BPF_MEM | BPF_B: /* dst = *(u8 *)(ul) (src + off) */
1370 case BPF_LDX | BPF_PROBE_MEM | BPF_B:
1371 /* llgc %dst,0(off,%src) */
1372 EMIT6_DISP_LH(0xe3000000, 0x0090, dst_reg, src_reg, REG_0, off);
1373 jit->seen |= SEEN_MEM;
1374 if (insn_is_zext(&insn[1]))
1377 case BPF_LDX | BPF_MEM | BPF_H: /* dst = *(u16 *)(ul) (src + off) */
1378 case BPF_LDX | BPF_PROBE_MEM | BPF_H:
1379 /* llgh %dst,0(off,%src) */
1380 EMIT6_DISP_LH(0xe3000000, 0x0091, dst_reg, src_reg, REG_0, off);
1381 jit->seen |= SEEN_MEM;
1382 if (insn_is_zext(&insn[1]))
1385 case BPF_LDX | BPF_MEM | BPF_W: /* dst = *(u32 *)(ul) (src + off) */
1386 case BPF_LDX | BPF_PROBE_MEM | BPF_W:
1387 /* llgf %dst,off(%src) */
1388 jit->seen |= SEEN_MEM;
1389 EMIT6_DISP_LH(0xe3000000, 0x0016, dst_reg, src_reg, REG_0, off);
1390 if (insn_is_zext(&insn[1]))
1393 case BPF_LDX | BPF_MEM | BPF_DW: /* dst = *(u64 *)(ul) (src + off) */
1394 case BPF_LDX | BPF_PROBE_MEM | BPF_DW:
1395 /* lg %dst,0(off,%src) */
1396 jit->seen |= SEEN_MEM;
1397 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg, src_reg, REG_0, off);
1402 case BPF_JMP | BPF_CALL:
1404 const struct btf_func_model *m;
1405 bool func_addr_fixed;
1409 ret = bpf_jit_get_func_addr(fp, insn, extra_pass,
1410 &func, &func_addr_fixed);
1414 REG_SET_SEEN(BPF_REG_5);
1415 jit->seen |= SEEN_FUNC;
1417 * Copy the tail call counter to where the callee expects it.
1419 * Note 1: The callee can increment the tail call counter, but
1420 * we do not load it back, since the x86 JIT does not do this
1423 * Note 2: We assume that the verifier does not let us call the
1424 * main program, which clears the tail call counter on entry.
1426 /* mvc STK_OFF_TCCNT(4,%r15),N(%r15) */
1427 _EMIT6(0xd203f000 | STK_OFF_TCCNT,
1428 0xf000 | (STK_OFF_TCCNT + STK_OFF + stack_depth));
1430 /* Sign-extend the kfunc arguments. */
1431 if (insn->src_reg == BPF_PSEUDO_KFUNC_CALL) {
1432 m = bpf_jit_find_kfunc_model(fp, insn);
1436 for (j = 0; j < m->nr_args; j++) {
1437 if (sign_extend(jit, BPF_REG_1 + j,
1445 EMIT6_PCREL_RILB(0xc4080000, REG_W1, _EMIT_CONST_U64(func));
1448 /* lgr %b0,%r2: load return value into %b0 */
1449 EMIT4(0xb9040000, BPF_REG_0, REG_2);
1452 case BPF_JMP | BPF_TAIL_CALL: {
1453 int patch_1_clrj, patch_2_clij, patch_3_brc;
1457 * B1: pointer to ctx
1458 * B2: pointer to bpf_array
1459 * B3: index in bpf_array
1461 * if (index >= array->map.max_entries)
1465 /* llgf %w1,map.max_entries(%b2) */
1466 EMIT6_DISP_LH(0xe3000000, 0x0016, REG_W1, REG_0, BPF_REG_2,
1467 offsetof(struct bpf_array, map.max_entries));
1468 /* if ((u32)%b3 >= (u32)%w1) goto out; */
1469 /* clrj %b3,%w1,0xa,out */
1470 patch_1_clrj = jit->prg;
1471 EMIT6_PCREL_RIEB(0xec000000, 0x0077, BPF_REG_3, REG_W1, 0xa,
1475 * if (tail_call_cnt++ >= MAX_TAIL_CALL_CNT)
1479 if (jit->seen & SEEN_STACK)
1480 off = STK_OFF_TCCNT + STK_OFF + stack_depth;
1482 off = STK_OFF_TCCNT;
1484 EMIT4_IMM(0xa7080000, REG_W0, 1);
1485 /* laal %w1,%w0,off(%r15) */
1486 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W1, REG_W0, REG_15, off);
1487 /* clij %w1,MAX_TAIL_CALL_CNT-1,0x2,out */
1488 patch_2_clij = jit->prg;
1489 EMIT6_PCREL_RIEC(0xec000000, 0x007f, REG_W1, MAX_TAIL_CALL_CNT - 1,
1493 * prog = array->ptrs[index];
1498 /* llgfr %r1,%b3: %r1 = (u32) index */
1499 EMIT4(0xb9160000, REG_1, BPF_REG_3);
1500 /* sllg %r1,%r1,3: %r1 *= 8 */
1501 EMIT6_DISP_LH(0xeb000000, 0x000d, REG_1, REG_1, REG_0, 3);
1502 /* ltg %r1,prog(%b2,%r1) */
1503 EMIT6_DISP_LH(0xe3000000, 0x0002, REG_1, BPF_REG_2,
1504 REG_1, offsetof(struct bpf_array, ptrs));
1506 patch_3_brc = jit->prg;
1507 EMIT4_PCREL_RIC(0xa7040000, 8, jit->prg);
1510 * Restore registers before calling function
1512 save_restore_regs(jit, REGS_RESTORE, stack_depth);
1515 * goto *(prog->bpf_func + tail_call_start);
1518 /* lg %r1,bpf_func(%r1) */
1519 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_1, REG_1, REG_0,
1520 offsetof(struct bpf_prog, bpf_func));
1521 if (nospec_uses_trampoline()) {
1522 jit->seen |= SEEN_FUNC;
1523 /* aghi %r1,tail_call_start */
1524 EMIT4_IMM(0xa70b0000, REG_1, jit->tail_call_start);
1525 /* brcl 0xf,__s390_indirect_jump_r1 */
1526 EMIT6_PCREL_RILC(0xc0040000, 0xf, jit->r1_thunk_ip);
1528 /* bc 0xf,tail_call_start(%r1) */
1529 _EMIT4(0x47f01000 + jit->tail_call_start);
1533 *(u16 *)(jit->prg_buf + patch_1_clrj + 2) =
1534 (jit->prg - patch_1_clrj) >> 1;
1535 *(u16 *)(jit->prg_buf + patch_2_clij + 2) =
1536 (jit->prg - patch_2_clij) >> 1;
1537 *(u16 *)(jit->prg_buf + patch_3_brc + 2) =
1538 (jit->prg - patch_3_brc) >> 1;
1542 case BPF_JMP | BPF_EXIT: /* return b0 */
1543 last = (i == fp->len - 1) ? 1 : 0;
1546 if (!is_first_pass(jit) && can_use_rel(jit, jit->exit_ip))
1547 /* brc 0xf, <exit> */
1548 EMIT4_PCREL_RIC(0xa7040000, 0xf, jit->exit_ip);
1550 /* brcl 0xf, <exit> */
1551 EMIT6_PCREL_RILC(0xc0040000, 0xf, jit->exit_ip);
1554 * Branch relative (number of skipped instructions) to offset on
1557 * Condition code to mask mapping:
1559 * CC | Description | Mask
1560 * ------------------------------
1561 * 0 | Operands equal | 8
1562 * 1 | First operand low | 4
1563 * 2 | First operand high | 2
1566 * For s390x relative branches: ip = ip + off_bytes
1567 * For BPF relative branches: insn = insn + off_insns + 1
1569 * For example for s390x with offset 0 we jump to the branch
1570 * instruction itself (loop) and for BPF with offset 0 we
1571 * branch to the instruction behind the branch.
1573 case BPF_JMP | BPF_JA: /* if (true) */
1574 mask = 0xf000; /* j */
1576 case BPF_JMP | BPF_JSGT | BPF_K: /* ((s64) dst > (s64) imm) */
1577 case BPF_JMP32 | BPF_JSGT | BPF_K: /* ((s32) dst > (s32) imm) */
1578 mask = 0x2000; /* jh */
1580 case BPF_JMP | BPF_JSLT | BPF_K: /* ((s64) dst < (s64) imm) */
1581 case BPF_JMP32 | BPF_JSLT | BPF_K: /* ((s32) dst < (s32) imm) */
1582 mask = 0x4000; /* jl */
1584 case BPF_JMP | BPF_JSGE | BPF_K: /* ((s64) dst >= (s64) imm) */
1585 case BPF_JMP32 | BPF_JSGE | BPF_K: /* ((s32) dst >= (s32) imm) */
1586 mask = 0xa000; /* jhe */
1588 case BPF_JMP | BPF_JSLE | BPF_K: /* ((s64) dst <= (s64) imm) */
1589 case BPF_JMP32 | BPF_JSLE | BPF_K: /* ((s32) dst <= (s32) imm) */
1590 mask = 0xc000; /* jle */
1592 case BPF_JMP | BPF_JGT | BPF_K: /* (dst_reg > imm) */
1593 case BPF_JMP32 | BPF_JGT | BPF_K: /* ((u32) dst_reg > (u32) imm) */
1594 mask = 0x2000; /* jh */
1596 case BPF_JMP | BPF_JLT | BPF_K: /* (dst_reg < imm) */
1597 case BPF_JMP32 | BPF_JLT | BPF_K: /* ((u32) dst_reg < (u32) imm) */
1598 mask = 0x4000; /* jl */
1600 case BPF_JMP | BPF_JGE | BPF_K: /* (dst_reg >= imm) */
1601 case BPF_JMP32 | BPF_JGE | BPF_K: /* ((u32) dst_reg >= (u32) imm) */
1602 mask = 0xa000; /* jhe */
1604 case BPF_JMP | BPF_JLE | BPF_K: /* (dst_reg <= imm) */
1605 case BPF_JMP32 | BPF_JLE | BPF_K: /* ((u32) dst_reg <= (u32) imm) */
1606 mask = 0xc000; /* jle */
1608 case BPF_JMP | BPF_JNE | BPF_K: /* (dst_reg != imm) */
1609 case BPF_JMP32 | BPF_JNE | BPF_K: /* ((u32) dst_reg != (u32) imm) */
1610 mask = 0x7000; /* jne */
1612 case BPF_JMP | BPF_JEQ | BPF_K: /* (dst_reg == imm) */
1613 case BPF_JMP32 | BPF_JEQ | BPF_K: /* ((u32) dst_reg == (u32) imm) */
1614 mask = 0x8000; /* je */
1616 case BPF_JMP | BPF_JSET | BPF_K: /* (dst_reg & imm) */
1617 case BPF_JMP32 | BPF_JSET | BPF_K: /* ((u32) dst_reg & (u32) imm) */
1618 mask = 0x7000; /* jnz */
1619 if (BPF_CLASS(insn->code) == BPF_JMP32) {
1620 /* llilf %w1,imm (load zero extend imm) */
1621 EMIT6_IMM(0xc00f0000, REG_W1, imm);
1623 EMIT2(0x1400, REG_W1, dst_reg);
1625 /* lgfi %w1,imm (load sign extend imm) */
1626 EMIT6_IMM(0xc0010000, REG_W1, imm);
1628 EMIT4(0xb9800000, REG_W1, dst_reg);
1632 case BPF_JMP | BPF_JSGT | BPF_X: /* ((s64) dst > (s64) src) */
1633 case BPF_JMP32 | BPF_JSGT | BPF_X: /* ((s32) dst > (s32) src) */
1634 mask = 0x2000; /* jh */
1636 case BPF_JMP | BPF_JSLT | BPF_X: /* ((s64) dst < (s64) src) */
1637 case BPF_JMP32 | BPF_JSLT | BPF_X: /* ((s32) dst < (s32) src) */
1638 mask = 0x4000; /* jl */
1640 case BPF_JMP | BPF_JSGE | BPF_X: /* ((s64) dst >= (s64) src) */
1641 case BPF_JMP32 | BPF_JSGE | BPF_X: /* ((s32) dst >= (s32) src) */
1642 mask = 0xa000; /* jhe */
1644 case BPF_JMP | BPF_JSLE | BPF_X: /* ((s64) dst <= (s64) src) */
1645 case BPF_JMP32 | BPF_JSLE | BPF_X: /* ((s32) dst <= (s32) src) */
1646 mask = 0xc000; /* jle */
1648 case BPF_JMP | BPF_JGT | BPF_X: /* (dst > src) */
1649 case BPF_JMP32 | BPF_JGT | BPF_X: /* ((u32) dst > (u32) src) */
1650 mask = 0x2000; /* jh */
1652 case BPF_JMP | BPF_JLT | BPF_X: /* (dst < src) */
1653 case BPF_JMP32 | BPF_JLT | BPF_X: /* ((u32) dst < (u32) src) */
1654 mask = 0x4000; /* jl */
1656 case BPF_JMP | BPF_JGE | BPF_X: /* (dst >= src) */
1657 case BPF_JMP32 | BPF_JGE | BPF_X: /* ((u32) dst >= (u32) src) */
1658 mask = 0xa000; /* jhe */
1660 case BPF_JMP | BPF_JLE | BPF_X: /* (dst <= src) */
1661 case BPF_JMP32 | BPF_JLE | BPF_X: /* ((u32) dst <= (u32) src) */
1662 mask = 0xc000; /* jle */
1664 case BPF_JMP | BPF_JNE | BPF_X: /* (dst != src) */
1665 case BPF_JMP32 | BPF_JNE | BPF_X: /* ((u32) dst != (u32) src) */
1666 mask = 0x7000; /* jne */
1668 case BPF_JMP | BPF_JEQ | BPF_X: /* (dst == src) */
1669 case BPF_JMP32 | BPF_JEQ | BPF_X: /* ((u32) dst == (u32) src) */
1670 mask = 0x8000; /* je */
1672 case BPF_JMP | BPF_JSET | BPF_X: /* (dst & src) */
1673 case BPF_JMP32 | BPF_JSET | BPF_X: /* ((u32) dst & (u32) src) */
1675 bool is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32;
1677 mask = 0x7000; /* jnz */
1678 /* nrk or ngrk %w1,%dst,%src */
1679 EMIT4_RRF((is_jmp32 ? 0xb9f40000 : 0xb9e40000),
1680 REG_W1, dst_reg, src_reg);
1683 is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32;
1684 /* cfi or cgfi %dst,imm */
1685 EMIT6_IMM(is_jmp32 ? 0xc20d0000 : 0xc20c0000,
1687 if (!is_first_pass(jit) &&
1688 can_use_rel(jit, addrs[i + off + 1])) {
1690 EMIT4_PCREL_RIC(0xa7040000,
1691 mask >> 12, addrs[i + off + 1]);
1694 EMIT6_PCREL_RILC(0xc0040000,
1695 mask >> 12, addrs[i + off + 1]);
1699 /* lgfi %w1,imm (load sign extend imm) */
1701 EMIT6_IMM(0xc0010000, src_reg, imm);
1704 is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32;
1705 if (!is_first_pass(jit) &&
1706 can_use_rel(jit, addrs[i + off + 1])) {
1707 /* crj or cgrj %dst,%src,mask,off */
1708 EMIT6_PCREL(0xec000000, (is_jmp32 ? 0x0076 : 0x0064),
1709 dst_reg, src_reg, i, off, mask);
1711 /* cr or cgr %dst,%src */
1713 EMIT2(0x1900, dst_reg, src_reg);
1715 EMIT4(0xb9200000, dst_reg, src_reg);
1717 EMIT6_PCREL_RILC(0xc0040000,
1718 mask >> 12, addrs[i + off + 1]);
1722 is_jmp32 = BPF_CLASS(insn->code) == BPF_JMP32;
1723 if (!is_first_pass(jit) &&
1724 can_use_rel(jit, addrs[i + off + 1])) {
1725 /* clrj or clgrj %dst,%src,mask,off */
1726 EMIT6_PCREL(0xec000000, (is_jmp32 ? 0x0077 : 0x0065),
1727 dst_reg, src_reg, i, off, mask);
1729 /* clr or clgr %dst,%src */
1731 EMIT2(0x1500, dst_reg, src_reg);
1733 EMIT4(0xb9210000, dst_reg, src_reg);
1735 EMIT6_PCREL_RILC(0xc0040000,
1736 mask >> 12, addrs[i + off + 1]);
1740 if (!is_first_pass(jit) &&
1741 can_use_rel(jit, addrs[i + off + 1])) {
1743 EMIT4_PCREL_RIC(0xa7040000,
1744 mask >> 12, addrs[i + off + 1]);
1747 EMIT6_PCREL_RILC(0xc0040000,
1748 mask >> 12, addrs[i + off + 1]);
1752 default: /* too complex, give up */
1753 pr_err("Unknown opcode %02x\n", insn->code);
1757 if (probe_prg != -1) {
1759 * Handlers of certain exceptions leave psw.addr pointing to
1760 * the instruction directly after the failing one. Therefore,
1761 * create two exception table entries and also add a nop in
1762 * case two probing instructions come directly after each
1768 err = bpf_jit_probe_mem(jit, fp, probe_prg, nop_prg);
1777 * Return whether new i-th instruction address does not violate any invariant
1779 static bool bpf_is_new_addr_sane(struct bpf_jit *jit, int i)
1781 /* On the first pass anything goes */
1782 if (is_first_pass(jit))
1785 /* The codegen pass must not change anything */
1786 if (is_codegen_pass(jit))
1787 return jit->addrs[i] == jit->prg;
1789 /* Passes in between must not increase code size */
1790 return jit->addrs[i] >= jit->prg;
1794 * Update the address of i-th instruction
1796 static int bpf_set_addr(struct bpf_jit *jit, int i)
1800 if (is_codegen_pass(jit)) {
1801 delta = jit->prg - jit->addrs[i];
1803 bpf_skip(jit, -delta);
1805 if (WARN_ON_ONCE(!bpf_is_new_addr_sane(jit, i)))
1807 jit->addrs[i] = jit->prg;
1812 * Compile eBPF program into s390x code
1814 static int bpf_jit_prog(struct bpf_jit *jit, struct bpf_prog *fp,
1815 bool extra_pass, u32 stack_depth)
1817 int i, insn_count, lit32_size, lit64_size;
1819 jit->lit32 = jit->lit32_start;
1820 jit->lit64 = jit->lit64_start;
1824 bpf_jit_prologue(jit, fp, stack_depth);
1825 if (bpf_set_addr(jit, 0) < 0)
1827 for (i = 0; i < fp->len; i += insn_count) {
1828 insn_count = bpf_jit_insn(jit, fp, i, extra_pass, stack_depth);
1831 /* Next instruction address */
1832 if (bpf_set_addr(jit, i + insn_count) < 0)
1835 bpf_jit_epilogue(jit, stack_depth);
1837 lit32_size = jit->lit32 - jit->lit32_start;
1838 lit64_size = jit->lit64 - jit->lit64_start;
1839 jit->lit32_start = jit->prg;
1841 jit->lit32_start = ALIGN(jit->lit32_start, 4);
1842 jit->lit64_start = jit->lit32_start + lit32_size;
1844 jit->lit64_start = ALIGN(jit->lit64_start, 8);
1845 jit->size = jit->lit64_start + lit64_size;
1846 jit->size_prg = jit->prg;
1848 if (WARN_ON_ONCE(fp->aux->extable &&
1849 jit->excnt != fp->aux->num_exentries))
1850 /* Verifier bug - too many entries. */
1856 bool bpf_jit_needs_zext(void)
1861 struct s390_jit_data {
1862 struct bpf_binary_header *header;
1867 static struct bpf_binary_header *bpf_jit_alloc(struct bpf_jit *jit,
1868 struct bpf_prog *fp)
1870 struct bpf_binary_header *header;
1874 /* We need two entries per insn. */
1875 fp->aux->num_exentries *= 2;
1877 code_size = roundup(jit->size,
1878 __alignof__(struct exception_table_entry));
1879 extable_size = fp->aux->num_exentries *
1880 sizeof(struct exception_table_entry);
1881 header = bpf_jit_binary_alloc(code_size + extable_size, &jit->prg_buf,
1885 fp->aux->extable = (struct exception_table_entry *)
1886 (jit->prg_buf + code_size);
1891 * Compile eBPF program "fp"
1893 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *fp)
1895 u32 stack_depth = round_up(fp->aux->stack_depth, 8);
1896 struct bpf_prog *tmp, *orig_fp = fp;
1897 struct bpf_binary_header *header;
1898 struct s390_jit_data *jit_data;
1899 bool tmp_blinded = false;
1900 bool extra_pass = false;
1904 if (WARN_ON_ONCE(bpf_plt_end - bpf_plt != BPF_PLT_SIZE))
1907 if (!fp->jit_requested)
1910 tmp = bpf_jit_blind_constants(fp);
1912 * If blinding was requested and we failed during blinding,
1913 * we must fall back to the interpreter.
1922 jit_data = fp->aux->jit_data;
1924 jit_data = kzalloc(sizeof(*jit_data), GFP_KERNEL);
1929 fp->aux->jit_data = jit_data;
1931 if (jit_data->ctx.addrs) {
1932 jit = jit_data->ctx;
1933 header = jit_data->header;
1935 pass = jit_data->pass + 1;
1939 memset(&jit, 0, sizeof(jit));
1940 jit.addrs = kvcalloc(fp->len + 1, sizeof(*jit.addrs), GFP_KERNEL);
1941 if (jit.addrs == NULL) {
1946 * Three initial passes:
1947 * - 1/2: Determine clobbered registers
1948 * - 3: Calculate program size and addrs array
1950 for (pass = 1; pass <= 3; pass++) {
1951 if (bpf_jit_prog(&jit, fp, extra_pass, stack_depth)) {
1957 * Final pass: Allocate and generate program
1959 header = bpf_jit_alloc(&jit, fp);
1965 if (bpf_jit_prog(&jit, fp, extra_pass, stack_depth)) {
1966 bpf_jit_binary_free(header);
1970 if (bpf_jit_enable > 1) {
1971 bpf_jit_dump(fp->len, jit.size, pass, jit.prg_buf);
1972 print_fn_code(jit.prg_buf, jit.size_prg);
1974 if (!fp->is_func || extra_pass) {
1975 bpf_jit_binary_lock_ro(header);
1977 jit_data->header = header;
1978 jit_data->ctx = jit;
1979 jit_data->pass = pass;
1981 fp->bpf_func = (void *) jit.prg_buf;
1983 fp->jited_len = jit.size;
1985 if (!fp->is_func || extra_pass) {
1986 bpf_prog_fill_jited_linfo(fp, jit.addrs + 1);
1990 fp->aux->jit_data = NULL;
1994 bpf_jit_prog_release_other(fp, fp == orig_fp ?
1999 bool bpf_jit_supports_kfunc_call(void)
2004 int bpf_arch_text_poke(void *ip, enum bpf_text_poke_type t,
2005 void *old_addr, void *new_addr)
2011 char expected_plt[BPF_PLT_SIZE];
2012 char current_plt[BPF_PLT_SIZE];
2016 /* Verify the branch to be patched. */
2017 err = copy_from_kernel_nofault(&insn, ip, sizeof(insn));
2020 if (insn.opc != (0xc004 | (old_addr ? 0xf0 : 0)))
2023 if (t == BPF_MOD_JUMP &&
2024 insn.disp == ((char *)new_addr - (char *)ip) >> 1) {
2026 * The branch already points to the destination,
2030 /* Verify the PLT. */
2031 plt = (char *)ip + (insn.disp << 1);
2032 err = copy_from_kernel_nofault(current_plt, plt, BPF_PLT_SIZE);
2035 bpf_jit_plt(expected_plt, (char *)ip + 6, old_addr);
2036 if (memcmp(current_plt, expected_plt, BPF_PLT_SIZE))
2038 /* Adjust the call address. */
2039 s390_kernel_write(plt + (bpf_plt_target - bpf_plt),
2040 &new_addr, sizeof(void *));
2043 /* Adjust the mask of the branch. */
2044 insn.opc = 0xc004 | (new_addr ? 0xf0 : 0);
2045 s390_kernel_write((char *)ip + 1, (char *)&insn.opc + 1, 1);
2047 /* Make the new code visible to the other CPUs. */
2048 text_poke_sync_lock();
2053 struct bpf_tramp_jit {
2054 struct bpf_jit common;
2055 int orig_stack_args_off;/* Offset of arguments placed on stack by the
2056 * func_addr's original caller
2058 int stack_size; /* Trampoline stack size */
2059 int stack_args_off; /* Offset of stack arguments for calling
2060 * func_addr, has to be at the top
2062 int reg_args_off; /* Offset of register arguments for calling
2065 int ip_off; /* For bpf_get_func_ip(), has to be at
2068 int arg_cnt_off; /* For bpf_get_func_arg_cnt(), has to be at
2071 int bpf_args_off; /* Offset of BPF_PROG context, which consists
2072 * of BPF arguments followed by return value
2074 int retval_off; /* Offset of return value (see above) */
2075 int r7_r8_off; /* Offset of saved %r7 and %r8, which are used
2076 * for __bpf_prog_enter() return value and
2077 * func_addr respectively
2079 int r14_off; /* Offset of saved %r14 */
2080 int run_ctx_off; /* Offset of struct bpf_tramp_run_ctx */
2081 int do_fexit; /* do_fexit: label */
2084 static void load_imm64(struct bpf_jit *jit, int dst_reg, u64 val)
2086 /* llihf %dst_reg,val_hi */
2087 EMIT6_IMM(0xc00e0000, dst_reg, (val >> 32));
2088 /* oilf %rdst_reg,val_lo */
2089 EMIT6_IMM(0xc00d0000, dst_reg, val);
2092 static int invoke_bpf_prog(struct bpf_tramp_jit *tjit,
2093 const struct btf_func_model *m,
2094 struct bpf_tramp_link *tlink, bool save_ret)
2096 struct bpf_jit *jit = &tjit->common;
2097 int cookie_off = tjit->run_ctx_off +
2098 offsetof(struct bpf_tramp_run_ctx, bpf_cookie);
2099 struct bpf_prog *p = tlink->link.prog;
2103 * run_ctx.cookie = tlink->cookie;
2106 /* %r0 = tlink->cookie */
2107 load_imm64(jit, REG_W0, tlink->cookie);
2108 /* stg %r0,cookie_off(%r15) */
2109 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W0, REG_0, REG_15, cookie_off);
2112 * if ((start = __bpf_prog_enter(p, &run_ctx)) == 0)
2116 /* %r1 = __bpf_prog_enter */
2117 load_imm64(jit, REG_1, (u64)bpf_trampoline_enter(p));
2119 load_imm64(jit, REG_2, (u64)p);
2120 /* la %r3,run_ctx_off(%r15) */
2121 EMIT4_DISP(0x41000000, REG_3, REG_15, tjit->run_ctx_off);
2125 EMIT4(0xb9020000, REG_7, REG_2);
2128 EMIT6_PCREL_RILC(0xc0040000, 8, 0);
2131 * retval = bpf_func(args, p->insnsi);
2134 /* %r1 = p->bpf_func */
2135 load_imm64(jit, REG_1, (u64)p->bpf_func);
2136 /* la %r2,bpf_args_off(%r15) */
2137 EMIT4_DISP(0x41000000, REG_2, REG_15, tjit->bpf_args_off);
2138 /* %r3 = p->insnsi */
2140 load_imm64(jit, REG_3, (u64)p->insnsi);
2143 /* stg %r2,retval_off(%r15) */
2145 if (sign_extend(jit, REG_2, m->ret_size, m->ret_flags))
2147 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_2, REG_0, REG_15,
2153 *(u32 *)&jit->prg_buf[patch + 2] = (jit->prg - patch) >> 1;
2156 * __bpf_prog_exit(p, start, &run_ctx);
2159 /* %r1 = __bpf_prog_exit */
2160 load_imm64(jit, REG_1, (u64)bpf_trampoline_exit(p));
2162 load_imm64(jit, REG_2, (u64)p);
2164 EMIT4(0xb9040000, REG_3, REG_7);
2165 /* la %r4,run_ctx_off(%r15) */
2166 EMIT4_DISP(0x41000000, REG_4, REG_15, tjit->run_ctx_off);
2173 static int alloc_stack(struct bpf_tramp_jit *tjit, size_t size)
2175 int stack_offset = tjit->stack_size;
2177 tjit->stack_size += size;
2178 return stack_offset;
2181 /* ABI uses %r2 - %r6 for parameter passing. */
2182 #define MAX_NR_REG_ARGS 5
2184 /* The "L" field of the "mvc" instruction is 8 bits. */
2185 #define MAX_MVC_SIZE 256
2186 #define MAX_NR_STACK_ARGS (MAX_MVC_SIZE / sizeof(u64))
2188 /* -mfentry generates a 6-byte nop on s390x. */
2189 #define S390X_PATCH_SIZE 6
2191 static int __arch_prepare_bpf_trampoline(struct bpf_tramp_image *im,
2192 struct bpf_tramp_jit *tjit,
2193 const struct btf_func_model *m,
2195 struct bpf_tramp_links *tlinks,
2198 struct bpf_tramp_links *fmod_ret = &tlinks[BPF_TRAMP_MODIFY_RETURN];
2199 struct bpf_tramp_links *fentry = &tlinks[BPF_TRAMP_FENTRY];
2200 struct bpf_tramp_links *fexit = &tlinks[BPF_TRAMP_FEXIT];
2201 int nr_bpf_args, nr_reg_args, nr_stack_args;
2202 struct bpf_jit *jit = &tjit->common;
2203 int arg, bpf_arg_off;
2206 /* Support as many stack arguments as "mvc" instruction can handle. */
2207 nr_reg_args = min_t(int, m->nr_args, MAX_NR_REG_ARGS);
2208 nr_stack_args = m->nr_args - nr_reg_args;
2209 if (nr_stack_args > MAX_NR_STACK_ARGS)
2212 /* Return to %r14, since func_addr and %r0 are not available. */
2213 if (!func_addr && !(flags & BPF_TRAMP_F_ORIG_STACK))
2214 flags |= BPF_TRAMP_F_SKIP_FRAME;
2217 * Compute how many arguments we need to pass to BPF programs.
2218 * BPF ABI mirrors that of x86_64: arguments that are 16 bytes or
2219 * smaller are packed into 1 or 2 registers; larger arguments are
2220 * passed via pointers.
2221 * In s390x ABI, arguments that are 8 bytes or smaller are packed into
2222 * a register; larger arguments are passed via pointers.
2223 * We need to deal with this difference.
2226 for (i = 0; i < m->nr_args; i++) {
2227 if (m->arg_size[i] <= 8)
2229 else if (m->arg_size[i] <= 16)
2236 * Calculate the stack layout.
2239 /* Reserve STACK_FRAME_OVERHEAD bytes for the callees. */
2240 tjit->stack_size = STACK_FRAME_OVERHEAD;
2241 tjit->stack_args_off = alloc_stack(tjit, nr_stack_args * sizeof(u64));
2242 tjit->reg_args_off = alloc_stack(tjit, nr_reg_args * sizeof(u64));
2243 tjit->ip_off = alloc_stack(tjit, sizeof(u64));
2244 tjit->arg_cnt_off = alloc_stack(tjit, sizeof(u64));
2245 tjit->bpf_args_off = alloc_stack(tjit, nr_bpf_args * sizeof(u64));
2246 tjit->retval_off = alloc_stack(tjit, sizeof(u64));
2247 tjit->r7_r8_off = alloc_stack(tjit, 2 * sizeof(u64));
2248 tjit->r14_off = alloc_stack(tjit, sizeof(u64));
2249 tjit->run_ctx_off = alloc_stack(tjit,
2250 sizeof(struct bpf_tramp_run_ctx));
2251 /* The caller has already reserved STACK_FRAME_OVERHEAD bytes. */
2252 tjit->stack_size -= STACK_FRAME_OVERHEAD;
2253 tjit->orig_stack_args_off = tjit->stack_size + STACK_FRAME_OVERHEAD;
2255 /* aghi %r15,-stack_size */
2256 EMIT4_IMM(0xa70b0000, REG_15, -tjit->stack_size);
2257 /* stmg %r2,%rN,fwd_reg_args_off(%r15) */
2259 EMIT6_DISP_LH(0xeb000000, 0x0024, REG_2,
2260 REG_2 + (nr_reg_args - 1), REG_15,
2261 tjit->reg_args_off);
2262 for (i = 0, j = 0; i < m->nr_args; i++) {
2263 if (i < MAX_NR_REG_ARGS)
2266 arg = tjit->orig_stack_args_off +
2267 (i - MAX_NR_REG_ARGS) * sizeof(u64);
2268 bpf_arg_off = tjit->bpf_args_off + j * sizeof(u64);
2269 if (m->arg_size[i] <= 8) {
2270 if (i < MAX_NR_REG_ARGS)
2271 /* stg %arg,bpf_arg_off(%r15) */
2272 EMIT6_DISP_LH(0xe3000000, 0x0024, arg,
2273 REG_0, REG_15, bpf_arg_off);
2275 /* mvc bpf_arg_off(8,%r15),arg(%r15) */
2276 _EMIT6(0xd207f000 | bpf_arg_off,
2280 if (i < MAX_NR_REG_ARGS) {
2281 /* mvc bpf_arg_off(16,%r15),0(%arg) */
2282 _EMIT6(0xd20ff000 | bpf_arg_off,
2283 reg2hex[arg] << 12);
2285 /* lg %r1,arg(%r15) */
2286 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_1, REG_0,
2288 /* mvc bpf_arg_off(16,%r15),0(%r1) */
2289 _EMIT6(0xd20ff000 | bpf_arg_off, 0x1000);
2294 /* stmg %r7,%r8,r7_r8_off(%r15) */
2295 EMIT6_DISP_LH(0xeb000000, 0x0024, REG_7, REG_8, REG_15,
2297 /* stg %r14,r14_off(%r15) */
2298 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_14, REG_0, REG_15, tjit->r14_off);
2300 if (flags & BPF_TRAMP_F_ORIG_STACK) {
2302 * The ftrace trampoline puts the return address (which is the
2303 * address of the original function + S390X_PATCH_SIZE) into
2304 * %r0; see ftrace_shared_hotpatch_trampoline_br and
2305 * ftrace_init_nop() for details.
2309 EMIT4(0xb9040000, REG_8, REG_0);
2311 /* %r8 = func_addr + S390X_PATCH_SIZE */
2312 load_imm64(jit, REG_8, (u64)func_addr + S390X_PATCH_SIZE);
2317 * arg_cnt = m->nr_args;
2320 if (flags & BPF_TRAMP_F_IP_ARG) {
2321 /* %r0 = func_addr */
2322 load_imm64(jit, REG_0, (u64)func_addr);
2323 /* stg %r0,ip_off(%r15) */
2324 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_0, REG_0, REG_15,
2327 /* lghi %r0,nr_bpf_args */
2328 EMIT4_IMM(0xa7090000, REG_0, nr_bpf_args);
2329 /* stg %r0,arg_cnt_off(%r15) */
2330 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_0, REG_0, REG_15,
2333 if (flags & BPF_TRAMP_F_CALL_ORIG) {
2335 * __bpf_tramp_enter(im);
2338 /* %r1 = __bpf_tramp_enter */
2339 load_imm64(jit, REG_1, (u64)__bpf_tramp_enter);
2341 load_imm64(jit, REG_2, (u64)im);
2346 for (i = 0; i < fentry->nr_links; i++)
2347 if (invoke_bpf_prog(tjit, m, fentry->links[i],
2348 flags & BPF_TRAMP_F_RET_FENTRY_RET))
2351 if (fmod_ret->nr_links) {
2356 /* xc retval_off(8,%r15),retval_off(%r15) */
2357 _EMIT6(0xd707f000 | tjit->retval_off,
2358 0xf000 | tjit->retval_off);
2360 for (i = 0; i < fmod_ret->nr_links; i++) {
2361 if (invoke_bpf_prog(tjit, m, fmod_ret->links[i], true))
2369 /* ltg %r0,retval_off(%r15) */
2370 EMIT6_DISP_LH(0xe3000000, 0x0002, REG_0, REG_0, REG_15,
2372 /* brcl 7,do_fexit */
2373 EMIT6_PCREL_RILC(0xc0040000, 7, tjit->do_fexit);
2377 if (flags & BPF_TRAMP_F_CALL_ORIG) {
2379 * retval = func_addr(args);
2382 /* lmg %r2,%rN,reg_args_off(%r15) */
2384 EMIT6_DISP_LH(0xeb000000, 0x0004, REG_2,
2385 REG_2 + (nr_reg_args - 1), REG_15,
2386 tjit->reg_args_off);
2387 /* mvc stack_args_off(N,%r15),orig_stack_args_off(%r15) */
2390 (nr_stack_args * sizeof(u64) - 1) << 16 |
2391 tjit->stack_args_off,
2392 0xf000 | tjit->orig_stack_args_off);
2394 EMIT4(0xb9040000, REG_1, REG_8);
2397 /* stg %r2,retval_off(%r15) */
2398 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_2, REG_0, REG_15,
2401 im->ip_after_call = jit->prg_buf + jit->prg;
2404 * The following nop will be patched by bpf_tramp_image_put().
2407 /* brcl 0,im->ip_epilogue */
2408 EMIT6_PCREL_RILC(0xc0040000, 0, (u64)im->ip_epilogue);
2412 tjit->do_fexit = jit->prg;
2413 for (i = 0; i < fexit->nr_links; i++)
2414 if (invoke_bpf_prog(tjit, m, fexit->links[i], false))
2417 if (flags & BPF_TRAMP_F_CALL_ORIG) {
2418 im->ip_epilogue = jit->prg_buf + jit->prg;
2421 * __bpf_tramp_exit(im);
2424 /* %r1 = __bpf_tramp_exit */
2425 load_imm64(jit, REG_1, (u64)__bpf_tramp_exit);
2427 load_imm64(jit, REG_2, (u64)im);
2432 /* lmg %r2,%rN,reg_args_off(%r15) */
2433 if ((flags & BPF_TRAMP_F_RESTORE_REGS) && nr_reg_args)
2434 EMIT6_DISP_LH(0xeb000000, 0x0004, REG_2,
2435 REG_2 + (nr_reg_args - 1), REG_15,
2436 tjit->reg_args_off);
2438 if (!(flags & BPF_TRAMP_F_SKIP_FRAME))
2439 EMIT4(0xb9040000, REG_1, REG_8);
2440 /* lmg %r7,%r8,r7_r8_off(%r15) */
2441 EMIT6_DISP_LH(0xeb000000, 0x0004, REG_7, REG_8, REG_15,
2443 /* lg %r14,r14_off(%r15) */
2444 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_14, REG_0, REG_15, tjit->r14_off);
2445 /* lg %r2,retval_off(%r15) */
2446 if (flags & (BPF_TRAMP_F_CALL_ORIG | BPF_TRAMP_F_RET_FENTRY_RET))
2447 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_2, REG_0, REG_15,
2449 /* aghi %r15,stack_size */
2450 EMIT4_IMM(0xa70b0000, REG_15, tjit->stack_size);
2451 /* Emit an expoline for the following indirect jump. */
2452 if (nospec_uses_trampoline())
2454 if (flags & BPF_TRAMP_F_SKIP_FRAME)
2466 int arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, void *image,
2467 void *image_end, const struct btf_func_model *m,
2468 u32 flags, struct bpf_tramp_links *tlinks,
2471 struct bpf_tramp_jit tjit;
2475 for (i = 0; i < 2; i++) {
2477 /* Compute offsets, check whether the code fits. */
2478 memset(&tjit, 0, sizeof(tjit));
2480 /* Generate the code. */
2481 tjit.common.prg = 0;
2482 tjit.common.prg_buf = image;
2484 ret = __arch_prepare_bpf_trampoline(im, &tjit, m, flags,
2488 if (tjit.common.prg > (char *)image_end - (char *)image)
2490 * Use the same error code as for exceeding
2491 * BPF_MAX_TRAMP_LINKS.
2499 bool bpf_jit_supports_subprog_tailcalls(void)