arch/riscv/mm/dma-noncoherent.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * RISC-V specific functions to support DMA for non-coherent devices
   4  *
   5  * Copyright (c) 2021 Western Digital Corporation or its affiliates.
   6  */
   7
   8 #include <linux/dma-direct.h>
   9 #include <linux/dma-map-ops.h>
  10 #include <linux/mm.h>
  11 #include <asm/cacheflush.h>
  12 #include <soc/sifive/sifive_ccache.h>
  13
  14 static bool noncoherent_supported;
  15
  16 void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
  17                               enum dma_data_direction dir)
  18 {
  19         void *vaddr;
  20
  21         if (sifive_ccache_handle_noncoherent()) {
  22                 sifive_ccache_flush_range(paddr, size);
  23                 return;
  24         }
  25
  26         vaddr = phys_to_virt(paddr);
  27         switch (dir) {
  28         case DMA_TO_DEVICE:
  29                 ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size);
  30                 break;
  31         case DMA_FROM_DEVICE:
  32                 ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size);
  33                 break;
  34         case DMA_BIDIRECTIONAL:
  35                 ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size);
  36                 break;
  37         default:
  38                 break;
  39         }
  40 }
  41
  42 void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
  43                            enum dma_data_direction dir)
  44 {
  45         void *vaddr;
  46
  47         if (sifive_ccache_handle_noncoherent()) {
  48                 sifive_ccache_flush_range(paddr, size);
  49                 return;
  50         }
  51
  52         vaddr = phys_to_virt(paddr);
  53         switch (dir) {
  54         case DMA_TO_DEVICE:
  55                 break;
  56         case DMA_FROM_DEVICE:
  57         case DMA_BIDIRECTIONAL:
  58                 ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size);
  59                 break;
  60         default:
  61                 break;
  62         }
  63 }
  64
  65 void *arch_dma_set_uncached(void *addr, size_t size)
  66 {
  67         if (sifive_ccache_handle_noncoherent())
  68                 return sifive_ccache_set_uncached(addr, size);
  69
  70         return addr;
  71 }
  72
  73 void arch_dma_clear_uncached(void *addr, size_t size)
  74 {
  75         if (sifive_ccache_handle_noncoherent())
  76                 sifive_ccache_clear_uncached(addr, size);
  77 }
  78
  79 void arch_dma_prep_coherent(struct page *page, size_t size)
  80 {
  81         void *flush_addr = page_address(page);
  82
  83         if (sifive_ccache_handle_noncoherent()) {
  84                 memset(flush_addr, 0, size);
  85                 sifive_ccache_flush_range(__pa(flush_addr), size);
  86                 return;
  87         }
  88
  89         ALT_CMO_OP(flush, flush_addr, size, riscv_cbom_block_size);
  90 }
  91
  92 void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
  93                 const struct iommu_ops *iommu, bool coherent)
  94 {
  95         WARN_TAINT(!coherent && riscv_cbom_block_size > ARCH_DMA_MINALIGN,
  96                    TAINT_CPU_OUT_OF_SPEC,
  97                    "%s %s: ARCH_DMA_MINALIGN smaller than riscv,cbom-block-size (%d < %d)",
  98                    dev_driver_string(dev), dev_name(dev),
  99                    ARCH_DMA_MINALIGN, riscv_cbom_block_size);
 100
 101         WARN_TAINT(!coherent && !noncoherent_supported, TAINT_CPU_OUT_OF_SPEC,
 102                    "%s %s: device non-coherent but no non-coherent operations supported",
 103                    dev_driver_string(dev), dev_name(dev));
 104
 105         dev->dma_coherent = coherent;
 106 }
 107
 108 void riscv_noncoherent_supported(void)
 109 {
 110         WARN(!riscv_cbom_block_size,
 111              "Non-coherent DMA support enabled without a block size\n");
 112         noncoherent_supported = true;
 113 }