1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017 Andes Technology Corporation
4 * Rick Chen, Andes Technology Corporation <rick@andestech.com>
9 void invalidate_icache_all(void)
11 asm volatile ("fence.i" ::: "memory");
14 void flush_dcache_all(void)
16 asm volatile ("fence" :::"memory");
18 void flush_dcache_range(unsigned long start, unsigned long end)
23 void invalidate_icache_range(unsigned long start, unsigned long end)
26 * RISC-V does not have an instruction for invalidating parts of the
27 * instruction cache. Invalidate all of it instead.
29 invalidate_icache_all();
32 void invalidate_dcache_range(unsigned long start, unsigned long end)
37 void cache_flush(void)
39 invalidate_icache_all();
43 void flush_cache(unsigned long addr, unsigned long size)
45 invalidate_icache_all();
49 __weak void icache_enable(void)
53 __weak void icache_disable(void)
57 __weak int icache_status(void)
62 __weak void dcache_enable(void)
66 __weak void dcache_disable(void)
70 __weak int dcache_status(void)