arch/riscv/lib/andes_plic.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2019, Rick Chen <rick@andestech.com>
   4  *
   5  * U-Boot syscon driver for Andes's Platform Level Interrupt Controller (PLIC).
   6  * The PLIC block holds memory-mapped claim and pending registers
   7  * associated with software interrupt.
   8  */
   9
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <dm/device-internal.h>
  13 #include <dm/lists.h>
  14 #include <dm/uclass-internal.h>
  15 #include <regmap.h>
  16 #include <syscon.h>
  17 #include <asm/io.h>
  18 #include <asm/syscon.h>
  19 #include <cpu.h>
  20 #include <linux/err.h>
  21
  22 /* pending register */
  23 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4)
  24 /* enable register */
  25 #define ENABLE_REG(base, hart)  ((ulong)(base) + 0x2000 + (hart) * 0x80)
  26 /* claim register */
  27 #define CLAIM_REG(base, hart)   ((ulong)(base) + 0x200004 + (hart) * 0x1000)
  28
  29 #define ENABLE_HART_IPI         (0x80808080)
  30 #define SEND_IPI_TO_HART(hart)  (0x80 >> (hart))
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 static int enable_ipi(int hart)
  35 {
  36         unsigned int en;
  37
  38         en = ENABLE_HART_IPI >> hart;
  39         writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart));
  40
  41         return 0;
  42 }
  43
  44 static int init_plic(void)
  45 {
  46         struct udevice *dev;
  47         ofnode node;
  48         int ret;
  49         u32 reg;
  50
  51         ret = uclass_find_first_device(UCLASS_CPU, &dev);
  52         if (ret)
  53                 return ret;
  54
  55         if (ret == 0 && dev) {
  56                 ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
  57                         const char *device_type;
  58
  59                         device_type = ofnode_read_string(node, "device_type");
  60                         if (!device_type)
  61                                 continue;
  62
  63                         if (strcmp(device_type, "cpu"))
  64                                 continue;
  65
  66                         /* skip if hart is marked as not available */
  67                         if (!ofnode_is_available(node))
  68                                 continue;
  69
  70                         /* read hart ID of CPU */
  71                         ret = ofnode_read_u32(node, "reg", &reg);
  72                         if (ret == 0)
  73                                 enable_ipi(reg);
  74                 }
  75
  76                 return 0;
  77         }
  78
  79         return -ENODEV;
  80 }
  81
  82 int riscv_init_ipi(void)
  83 {
  84         long *ret = syscon_get_first_range(RISCV_SYSCON_PLIC);
  85
  86         if (IS_ERR(ret))
  87                 return PTR_ERR(ret);
  88         gd->arch.plic = ret;
  89
  90         return init_plic();
  91 }
  92
  93 int riscv_send_ipi(int hart)
  94 {
  95         unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
  96
  97         writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic,
  98                                 gd->arch.boot_hart));
  99
 100         return 0;
 101 }
 102
 103 int riscv_clear_ipi(int hart)
 104 {
 105         u32 source_id;
 106
 107         source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart));
 108         writel(source_id, (void __iomem *)CLAIM_REG(gd->arch.plic, hart));
 109
 110         return 0;
 111 }
 112
 113 int riscv_get_ipi(int hart, int *pending)
 114 {
 115         *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic,
 116                                                      gd->arch.boot_hart));
 117         *pending = !!(*pending & SEND_IPI_TO_HART(hart));
 118
 119         return 0;
 120 }
 121
 122 static const struct udevice_id andes_plic_ids[] = {
 123         { .compatible = "riscv,plic1", .data = RISCV_SYSCON_PLIC },
 124         { }
 125 };
 126
 127 U_BOOT_DRIVER(andes_plic) = {
 128         .name           = "andes_plic",
 129         .id             = UCLASS_SYSCON,
 130         .of_match       = andes_plic_ids,
 131         .flags          = DM_FLAG_PRE_RELOC,
 132 };