1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019, Rick Chen <rick@andestech.com>
5 * U-Boot syscon driver for Andes's Platform Level Interrupt Controller (PLIC).
6 * The PLIC block holds memory-mapped claim and pending registers
7 * associated with software interrupt.
12 #include <dm/device-internal.h>
14 #include <dm/uclass-internal.h>
18 #include <asm/syscon.h>
21 /* pending register */
22 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + (hart) * 8)
24 #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80)
26 #define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000)
28 #define ENABLE_HART_IPI (0x80808080)
29 #define SEND_IPI_TO_HART(hart) (0x80 >> (hart))
31 DECLARE_GLOBAL_DATA_PTR;
32 static int init_plic(void);
34 #define PLIC_BASE_GET(void) \
38 if (!gd->arch.plic) { \
39 ret = syscon_get_first_range(RISCV_SYSCON_PLIC); \
41 return PTR_ERR(ret); \
42 gd->arch.plic = ret; \
47 static int enable_ipi(int harts)
50 int en = ENABLE_HART_IPI;
52 for (i = 0; i < harts; i++) {
54 writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, i));
60 static int init_plic(void)
65 ret = uclass_find_first_device(UCLASS_CPU, &dev);
69 if (ret == 0 && dev) {
70 ret = cpu_get_count(dev);
81 int riscv_send_ipi(int hart)
85 writel(SEND_IPI_TO_HART(hart),
86 (void __iomem *)PENDING_REG(gd->arch.plic, gd->arch.boot_hart));
91 int riscv_clear_ipi(int hart)
97 source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart));
98 writel(source_id, (void __iomem *)CLAIM_REG(gd->arch.plic, hart));
103 static const struct udevice_id andes_plic_ids[] = {
104 { .compatible = "riscv,plic1", .data = RISCV_SYSCON_PLIC },
108 U_BOOT_DRIVER(andes_plic) = {
109 .name = "andes_plic",
111 .of_match = andes_plic_ids,
112 .flags = DM_FLAG_PRE_RELOC,