arch/riscv/lib/andes_plic.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2019, Rick Chen <rick@andestech.com>
   4  *
   5  * U-Boot syscon driver for Andes's Platform Level Interrupt Controller (PLIC).
   6  * The PLIC block holds memory-mapped claim and pending registers
   7  * associated with software interrupt.
   8  */
   9
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <dm/device-internal.h>
  13 #include <dm/lists.h>
  14 #include <dm/uclass-internal.h>
  15 #include <regmap.h>
  16 #include <syscon.h>
  17 #include <asm/io.h>
  18 #include <asm/syscon.h>
  19 #include <cpu.h>
  20
  21 /* pending register */
  22 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + (hart) * 8)
  23 /* enable register */
  24 #define ENABLE_REG(base, hart)  ((ulong)(base) + 0x2000 + (hart) * 0x80)
  25 /* claim register */
  26 #define CLAIM_REG(base, hart)   ((ulong)(base) + 0x200004 + (hart) * 0x1000)
  27
  28 #define ENABLE_HART_IPI         (0x80808080)
  29 #define SEND_IPI_TO_HART(hart)  (0x80 >> (hart))
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32 static int init_plic(void);
  33
  34 #define PLIC_BASE_GET(void)                                             \
  35         do {                                                            \
  36                 long *ret;                                              \
  37                                                                         \
  38                 if (!gd->arch.plic) {                                   \
  39                         ret = syscon_get_first_range(RISCV_SYSCON_PLIC); \
  40                         if (IS_ERR(ret))                                \
  41                                 return PTR_ERR(ret);                    \
  42                         gd->arch.plic = ret;                            \
  43                         init_plic();                                    \
  44                 }                                                       \
  45         } while (0)
  46
  47 static int enable_ipi(int harts)
  48 {
  49         int i;
  50         int en = ENABLE_HART_IPI;
  51
  52         for (i = 0; i < harts; i++) {
  53                 en = en >> i;
  54                 writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, i));
  55         }
  56
  57         return 0;
  58 }
  59
  60 static int init_plic(void)
  61 {
  62         struct udevice *dev;
  63         int ret;
  64
  65         ret = uclass_find_first_device(UCLASS_CPU, &dev);
  66         if (ret)
  67                 return ret;
  68
  69         if (ret == 0 && dev) {
  70                 ret = cpu_get_count(dev);
  71                 if (ret < 0)
  72                         return ret;
  73
  74                 enable_ipi(ret);
  75                 return 0;
  76         }
  77
  78         return -ENODEV;
  79 }
  80
  81 int riscv_send_ipi(int hart)
  82 {
  83         PLIC_BASE_GET();
  84
  85         writel(SEND_IPI_TO_HART(hart),
  86                (void __iomem *)PENDING_REG(gd->arch.plic, gd->arch.boot_hart));
  87
  88         return 0;
  89 }
  90
  91 int riscv_clear_ipi(int hart)
  92 {
  93         u32 source_id;
  94
  95         PLIC_BASE_GET();
  96
  97         source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart));
  98         writel(source_id, (void __iomem *)CLAIM_REG(gd->arch.plic, hart));
  99
 100         return 0;
 101 }
 102
 103 static const struct udevice_id andes_plic_ids[] = {
 104         { .compatible = "riscv,plic1", .data = RISCV_SYSCON_PLIC },
 105         { }
 106 };
 107
 108 U_BOOT_DRIVER(andes_plic) = {
 109         .name           = "andes_plic",
 110         .id             = UCLASS_SYSCON,
 111         .of_match       = andes_plic_ids,
 112         .flags          = DM_FLAG_PRE_RELOC,
 113 };