arch/riscv/lib/andes_plic.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2019, Rick Chen <rick@andestech.com>
   4  *
   5  * U-Boot syscon driver for Andes's Platform Level Interrupt Controller (PLIC).
   6  * The PLIC block holds memory-mapped claim and pending registers
   7  * associated with software interrupt.
   8  */
   9
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <dm/device-internal.h>
  13 #include <dm/lists.h>
  14 #include <dm/uclass-internal.h>
  15 #include <regmap.h>
  16 #include <syscon.h>
  17 #include <asm/io.h>
  18 #include <asm/syscon.h>
  19 #include <cpu.h>
  20 #include <linux/err.h>
  21
  22 /* pending register */
  23 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4)
  24 /* enable register */
  25 #define ENABLE_REG(base, hart)  ((ulong)(base) + 0x2000 + (hart) * 0x80)
  26 /* claim register */
  27 #define CLAIM_REG(base, hart)   ((ulong)(base) + 0x200004 + (hart) * 0x1000)
  28
  29 #define ENABLE_HART_IPI         (0x80808080)
  30 #define SEND_IPI_TO_HART(hart)  (0x80 >> (hart))
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 static int enable_ipi(int hart)
  35 {
  36         unsigned int en;
  37
  38         en = ENABLE_HART_IPI >> hart;
  39         writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart));
  40
  41         return 0;
  42 }
  43
  44 int riscv_init_ipi(void)
  45 {
  46         int ret;
  47         long *base = syscon_get_first_range(RISCV_SYSCON_PLIC);
  48         ofnode node;
  49         struct udevice *dev;
  50         u32 reg;
  51
  52         if (IS_ERR(base))
  53                 return PTR_ERR(base);
  54         gd->arch.plic = base;
  55
  56         ret = uclass_find_first_device(UCLASS_CPU, &dev);
  57         if (ret)
  58                 return ret;
  59         else if (!dev)
  60                 return -ENODEV;
  61
  62         ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
  63                 const char *device_type;
  64
  65                 device_type = ofnode_read_string(node, "device_type");
  66                 if (!device_type)
  67                         continue;
  68
  69                 if (strcmp(device_type, "cpu"))
  70                         continue;
  71
  72                 /* skip if hart is marked as not available */
  73                 if (!ofnode_is_available(node))
  74                         continue;
  75
  76                 /* read hart ID of CPU */
  77                 ret = ofnode_read_u32(node, "reg", &reg);
  78                 if (ret == 0)
  79                         enable_ipi(reg);
  80         }
  81
  82         return 0;
  83 }
  84
  85 int riscv_send_ipi(int hart)
  86 {
  87         unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
  88
  89         writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic,
  90                                 gd->arch.boot_hart));
  91
  92         return 0;
  93 }
  94
  95 int riscv_clear_ipi(int hart)
  96 {
  97         u32 source_id;
  98
  99         source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart));
 100         writel(source_id, (void __iomem *)CLAIM_REG(gd->arch.plic, hart));
 101
 102         return 0;
 103 }
 104
 105 int riscv_get_ipi(int hart, int *pending)
 106 {
 107         *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic,
 108                                                      gd->arch.boot_hart));
 109         *pending = !!(*pending & SEND_IPI_TO_HART(hart));
 110
 111         return 0;
 112 }
 113
 114 static const struct udevice_id andes_plic_ids[] = {
 115         { .compatible = "riscv,plic1", .data = RISCV_SYSCON_PLIC },
 116         { }
 117 };
 118
 119 U_BOOT_DRIVER(andes_plic) = {
 120         .name           = "andes_plic",
 121         .id             = UCLASS_SYSCON,
 122         .of_match       = andes_plic_ids,
 123         .flags          = DM_FLAG_PRE_RELOC,
 124 };