1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 Western Digital Corporation or its affiliates.
6 * Anup Patel <anup.patel@wdc.com>
9 #include <linux/bitops.h>
10 #include <linux/errno.h>
11 #include <linux/err.h>
12 #include <linux/kdebug.h>
13 #include <linux/module.h>
14 #include <linux/percpu.h>
15 #include <linux/uaccess.h>
16 #include <linux/vmalloc.h>
17 #include <linux/sched/signal.h>
19 #include <linux/kvm_host.h>
21 #include <asm/hwcap.h>
23 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = {
24 KVM_GENERIC_VCPU_STATS(),
25 STATS_DESC_COUNTER(VCPU, ecall_exit_stat),
26 STATS_DESC_COUNTER(VCPU, wfi_exit_stat),
27 STATS_DESC_COUNTER(VCPU, mmio_exit_user),
28 STATS_DESC_COUNTER(VCPU, mmio_exit_kernel),
29 STATS_DESC_COUNTER(VCPU, exits)
32 const struct kvm_stats_header kvm_vcpu_stats_header = {
33 .name_size = KVM_STATS_NAME_SIZE,
34 .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc),
35 .id_offset = sizeof(struct kvm_stats_header),
36 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
37 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
38 sizeof(kvm_vcpu_stats_desc),
41 #define KVM_RISCV_ISA_ALLOWED (riscv_isa_extension_mask(a) | \
42 riscv_isa_extension_mask(c) | \
43 riscv_isa_extension_mask(d) | \
44 riscv_isa_extension_mask(f) | \
45 riscv_isa_extension_mask(i) | \
46 riscv_isa_extension_mask(m) | \
47 riscv_isa_extension_mask(s) | \
48 riscv_isa_extension_mask(u))
50 static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu)
52 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
53 struct kvm_vcpu_csr *reset_csr = &vcpu->arch.guest_reset_csr;
54 struct kvm_cpu_context *cntx = &vcpu->arch.guest_context;
55 struct kvm_cpu_context *reset_cntx = &vcpu->arch.guest_reset_context;
57 memcpy(csr, reset_csr, sizeof(*csr));
59 memcpy(cntx, reset_cntx, sizeof(*cntx));
61 kvm_riscv_vcpu_fp_reset(vcpu);
63 kvm_riscv_vcpu_timer_reset(vcpu);
65 WRITE_ONCE(vcpu->arch.irqs_pending, 0);
66 WRITE_ONCE(vcpu->arch.irqs_pending_mask, 0);
69 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
74 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
76 struct kvm_cpu_context *cntx;
78 /* Mark this VCPU never ran */
79 vcpu->arch.ran_atleast_once = false;
81 /* Setup ISA features available to VCPU */
82 vcpu->arch.isa = riscv_isa_extension_base(NULL) & KVM_RISCV_ISA_ALLOWED;
84 /* Setup reset state of shadow SSTATUS and HSTATUS CSRs */
85 cntx = &vcpu->arch.guest_reset_context;
86 cntx->sstatus = SR_SPP | SR_SPIE;
88 cntx->hstatus |= HSTATUS_VTW;
89 cntx->hstatus |= HSTATUS_SPVP;
90 cntx->hstatus |= HSTATUS_SPV;
92 /* Setup VCPU timer */
93 kvm_riscv_vcpu_timer_init(vcpu);
96 kvm_riscv_reset_vcpu(vcpu);
101 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
105 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
107 /* Cleanup VCPU timer */
108 kvm_riscv_vcpu_timer_deinit(vcpu);
110 /* Flush the pages pre-allocated for Stage2 page table mappings */
111 kvm_riscv_stage2_flush_cache(vcpu);
114 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
116 return kvm_riscv_vcpu_has_interrupts(vcpu, 1UL << IRQ_VS_TIMER);
119 void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu)
123 void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu)
127 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
129 return (kvm_riscv_vcpu_has_interrupts(vcpu, -1UL) &&
130 !vcpu->arch.power_off && !vcpu->arch.pause);
133 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
135 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
138 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
140 return (vcpu->arch.guest_context.sstatus & SR_SPP) ? true : false;
143 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
145 return VM_FAULT_SIGBUS;
148 static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu,
149 const struct kvm_one_reg *reg)
151 unsigned long __user *uaddr =
152 (unsigned long __user *)(unsigned long)reg->addr;
153 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
155 KVM_REG_RISCV_CONFIG);
156 unsigned long reg_val;
158 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
162 case KVM_REG_RISCV_CONFIG_REG(isa):
163 reg_val = vcpu->arch.isa;
169 if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id)))
175 static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu,
176 const struct kvm_one_reg *reg)
178 unsigned long __user *uaddr =
179 (unsigned long __user *)(unsigned long)reg->addr;
180 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
182 KVM_REG_RISCV_CONFIG);
183 unsigned long reg_val;
185 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
188 if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id)))
192 case KVM_REG_RISCV_CONFIG_REG(isa):
193 if (!vcpu->arch.ran_atleast_once) {
194 vcpu->arch.isa = reg_val;
195 vcpu->arch.isa &= riscv_isa_extension_base(NULL);
196 vcpu->arch.isa &= KVM_RISCV_ISA_ALLOWED;
197 kvm_riscv_vcpu_fp_reset(vcpu);
209 static int kvm_riscv_vcpu_get_reg_core(struct kvm_vcpu *vcpu,
210 const struct kvm_one_reg *reg)
212 struct kvm_cpu_context *cntx = &vcpu->arch.guest_context;
213 unsigned long __user *uaddr =
214 (unsigned long __user *)(unsigned long)reg->addr;
215 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
218 unsigned long reg_val;
220 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
222 if (reg_num >= sizeof(struct kvm_riscv_core) / sizeof(unsigned long))
225 if (reg_num == KVM_REG_RISCV_CORE_REG(regs.pc))
226 reg_val = cntx->sepc;
227 else if (KVM_REG_RISCV_CORE_REG(regs.pc) < reg_num &&
228 reg_num <= KVM_REG_RISCV_CORE_REG(regs.t6))
229 reg_val = ((unsigned long *)cntx)[reg_num];
230 else if (reg_num == KVM_REG_RISCV_CORE_REG(mode))
231 reg_val = (cntx->sstatus & SR_SPP) ?
232 KVM_RISCV_MODE_S : KVM_RISCV_MODE_U;
236 if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id)))
242 static int kvm_riscv_vcpu_set_reg_core(struct kvm_vcpu *vcpu,
243 const struct kvm_one_reg *reg)
245 struct kvm_cpu_context *cntx = &vcpu->arch.guest_context;
246 unsigned long __user *uaddr =
247 (unsigned long __user *)(unsigned long)reg->addr;
248 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
251 unsigned long reg_val;
253 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
255 if (reg_num >= sizeof(struct kvm_riscv_core) / sizeof(unsigned long))
258 if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id)))
261 if (reg_num == KVM_REG_RISCV_CORE_REG(regs.pc))
262 cntx->sepc = reg_val;
263 else if (KVM_REG_RISCV_CORE_REG(regs.pc) < reg_num &&
264 reg_num <= KVM_REG_RISCV_CORE_REG(regs.t6))
265 ((unsigned long *)cntx)[reg_num] = reg_val;
266 else if (reg_num == KVM_REG_RISCV_CORE_REG(mode)) {
267 if (reg_val == KVM_RISCV_MODE_S)
268 cntx->sstatus |= SR_SPP;
270 cntx->sstatus &= ~SR_SPP;
277 static int kvm_riscv_vcpu_get_reg_csr(struct kvm_vcpu *vcpu,
278 const struct kvm_one_reg *reg)
280 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
281 unsigned long __user *uaddr =
282 (unsigned long __user *)(unsigned long)reg->addr;
283 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
286 unsigned long reg_val;
288 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
290 if (reg_num >= sizeof(struct kvm_riscv_csr) / sizeof(unsigned long))
293 if (reg_num == KVM_REG_RISCV_CSR_REG(sip)) {
294 kvm_riscv_vcpu_flush_interrupts(vcpu);
295 reg_val = (csr->hvip >> VSIP_TO_HVIP_SHIFT) & VSIP_VALID_MASK;
297 reg_val = ((unsigned long *)csr)[reg_num];
299 if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id)))
305 static int kvm_riscv_vcpu_set_reg_csr(struct kvm_vcpu *vcpu,
306 const struct kvm_one_reg *reg)
308 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
309 unsigned long __user *uaddr =
310 (unsigned long __user *)(unsigned long)reg->addr;
311 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
314 unsigned long reg_val;
316 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
318 if (reg_num >= sizeof(struct kvm_riscv_csr) / sizeof(unsigned long))
321 if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id)))
324 if (reg_num == KVM_REG_RISCV_CSR_REG(sip)) {
325 reg_val &= VSIP_VALID_MASK;
326 reg_val <<= VSIP_TO_HVIP_SHIFT;
329 ((unsigned long *)csr)[reg_num] = reg_val;
331 if (reg_num == KVM_REG_RISCV_CSR_REG(sip))
332 WRITE_ONCE(vcpu->arch.irqs_pending_mask, 0);
337 static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu,
338 const struct kvm_one_reg *reg)
340 if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CONFIG)
341 return kvm_riscv_vcpu_set_reg_config(vcpu, reg);
342 else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CORE)
343 return kvm_riscv_vcpu_set_reg_core(vcpu, reg);
344 else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR)
345 return kvm_riscv_vcpu_set_reg_csr(vcpu, reg);
346 else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_TIMER)
347 return kvm_riscv_vcpu_set_reg_timer(vcpu, reg);
348 else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_F)
349 return kvm_riscv_vcpu_set_reg_fp(vcpu, reg,
351 else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_D)
352 return kvm_riscv_vcpu_set_reg_fp(vcpu, reg,
358 static int kvm_riscv_vcpu_get_reg(struct kvm_vcpu *vcpu,
359 const struct kvm_one_reg *reg)
361 if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CONFIG)
362 return kvm_riscv_vcpu_get_reg_config(vcpu, reg);
363 else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CORE)
364 return kvm_riscv_vcpu_get_reg_core(vcpu, reg);
365 else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR)
366 return kvm_riscv_vcpu_get_reg_csr(vcpu, reg);
367 else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_TIMER)
368 return kvm_riscv_vcpu_get_reg_timer(vcpu, reg);
369 else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_F)
370 return kvm_riscv_vcpu_get_reg_fp(vcpu, reg,
372 else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_D)
373 return kvm_riscv_vcpu_get_reg_fp(vcpu, reg,
379 long kvm_arch_vcpu_async_ioctl(struct file *filp,
380 unsigned int ioctl, unsigned long arg)
382 struct kvm_vcpu *vcpu = filp->private_data;
383 void __user *argp = (void __user *)arg;
385 if (ioctl == KVM_INTERRUPT) {
386 struct kvm_interrupt irq;
388 if (copy_from_user(&irq, argp, sizeof(irq)))
391 if (irq.irq == KVM_INTERRUPT_SET)
392 return kvm_riscv_vcpu_set_interrupt(vcpu, IRQ_VS_EXT);
394 return kvm_riscv_vcpu_unset_interrupt(vcpu, IRQ_VS_EXT);
400 long kvm_arch_vcpu_ioctl(struct file *filp,
401 unsigned int ioctl, unsigned long arg)
403 struct kvm_vcpu *vcpu = filp->private_data;
404 void __user *argp = (void __user *)arg;
408 case KVM_SET_ONE_REG:
409 case KVM_GET_ONE_REG: {
410 struct kvm_one_reg reg;
413 if (copy_from_user(®, argp, sizeof(reg)))
416 if (ioctl == KVM_SET_ONE_REG)
417 r = kvm_riscv_vcpu_set_reg(vcpu, ®);
419 r = kvm_riscv_vcpu_get_reg(vcpu, ®);
429 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
430 struct kvm_sregs *sregs)
435 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
436 struct kvm_sregs *sregs)
441 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
446 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
451 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
452 struct kvm_translation *tr)
457 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
462 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
467 void kvm_riscv_vcpu_flush_interrupts(struct kvm_vcpu *vcpu)
469 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
470 unsigned long mask, val;
472 if (READ_ONCE(vcpu->arch.irqs_pending_mask)) {
473 mask = xchg_acquire(&vcpu->arch.irqs_pending_mask, 0);
474 val = READ_ONCE(vcpu->arch.irqs_pending) & mask;
481 void kvm_riscv_vcpu_sync_interrupts(struct kvm_vcpu *vcpu)
484 struct kvm_vcpu_arch *v = &vcpu->arch;
485 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
487 /* Read current HVIP and VSIE CSRs */
488 csr->vsie = csr_read(CSR_VSIE);
490 /* Sync-up HVIP.VSSIP bit changes does by Guest */
491 hvip = csr_read(CSR_HVIP);
492 if ((csr->hvip ^ hvip) & (1UL << IRQ_VS_SOFT)) {
493 if (hvip & (1UL << IRQ_VS_SOFT)) {
494 if (!test_and_set_bit(IRQ_VS_SOFT,
495 &v->irqs_pending_mask))
496 set_bit(IRQ_VS_SOFT, &v->irqs_pending);
498 if (!test_and_set_bit(IRQ_VS_SOFT,
499 &v->irqs_pending_mask))
500 clear_bit(IRQ_VS_SOFT, &v->irqs_pending);
505 int kvm_riscv_vcpu_set_interrupt(struct kvm_vcpu *vcpu, unsigned int irq)
507 if (irq != IRQ_VS_SOFT &&
508 irq != IRQ_VS_TIMER &&
512 set_bit(irq, &vcpu->arch.irqs_pending);
513 smp_mb__before_atomic();
514 set_bit(irq, &vcpu->arch.irqs_pending_mask);
521 int kvm_riscv_vcpu_unset_interrupt(struct kvm_vcpu *vcpu, unsigned int irq)
523 if (irq != IRQ_VS_SOFT &&
524 irq != IRQ_VS_TIMER &&
528 clear_bit(irq, &vcpu->arch.irqs_pending);
529 smp_mb__before_atomic();
530 set_bit(irq, &vcpu->arch.irqs_pending_mask);
535 bool kvm_riscv_vcpu_has_interrupts(struct kvm_vcpu *vcpu, unsigned long mask)
537 unsigned long ie = ((vcpu->arch.guest_csr.vsie & VSIP_VALID_MASK)
538 << VSIP_TO_HVIP_SHIFT) & mask;
540 return (READ_ONCE(vcpu->arch.irqs_pending) & ie) ? true : false;
543 void kvm_riscv_vcpu_power_off(struct kvm_vcpu *vcpu)
545 vcpu->arch.power_off = true;
546 kvm_make_request(KVM_REQ_SLEEP, vcpu);
550 void kvm_riscv_vcpu_power_on(struct kvm_vcpu *vcpu)
552 vcpu->arch.power_off = false;
553 kvm_vcpu_wake_up(vcpu);
556 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
557 struct kvm_mp_state *mp_state)
559 if (vcpu->arch.power_off)
560 mp_state->mp_state = KVM_MP_STATE_STOPPED;
562 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
567 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
568 struct kvm_mp_state *mp_state)
572 switch (mp_state->mp_state) {
573 case KVM_MP_STATE_RUNNABLE:
574 vcpu->arch.power_off = false;
576 case KVM_MP_STATE_STOPPED:
577 kvm_riscv_vcpu_power_off(vcpu);
586 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
587 struct kvm_guest_debug *dbg)
589 /* TODO; To be implemented later. */
593 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
595 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
597 csr_write(CSR_VSSTATUS, csr->vsstatus);
598 csr_write(CSR_VSIE, csr->vsie);
599 csr_write(CSR_VSTVEC, csr->vstvec);
600 csr_write(CSR_VSSCRATCH, csr->vsscratch);
601 csr_write(CSR_VSEPC, csr->vsepc);
602 csr_write(CSR_VSCAUSE, csr->vscause);
603 csr_write(CSR_VSTVAL, csr->vstval);
604 csr_write(CSR_HVIP, csr->hvip);
605 csr_write(CSR_VSATP, csr->vsatp);
607 kvm_riscv_stage2_update_hgatp(vcpu);
609 kvm_riscv_vcpu_timer_restore(vcpu);
611 kvm_riscv_vcpu_host_fp_save(&vcpu->arch.host_context);
612 kvm_riscv_vcpu_guest_fp_restore(&vcpu->arch.guest_context,
618 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
620 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
624 kvm_riscv_vcpu_guest_fp_save(&vcpu->arch.guest_context,
626 kvm_riscv_vcpu_host_fp_restore(&vcpu->arch.host_context);
628 csr_write(CSR_HGATP, 0);
630 csr->vsstatus = csr_read(CSR_VSSTATUS);
631 csr->vsie = csr_read(CSR_VSIE);
632 csr->vstvec = csr_read(CSR_VSTVEC);
633 csr->vsscratch = csr_read(CSR_VSSCRATCH);
634 csr->vsepc = csr_read(CSR_VSEPC);
635 csr->vscause = csr_read(CSR_VSCAUSE);
636 csr->vstval = csr_read(CSR_VSTVAL);
637 csr->hvip = csr_read(CSR_HVIP);
638 csr->vsatp = csr_read(CSR_VSATP);
641 static void kvm_riscv_check_vcpu_requests(struct kvm_vcpu *vcpu)
643 struct rcuwait *wait = kvm_arch_vcpu_get_wait(vcpu);
645 if (kvm_request_pending(vcpu)) {
646 if (kvm_check_request(KVM_REQ_SLEEP, vcpu)) {
647 rcuwait_wait_event(wait,
648 (!vcpu->arch.power_off) && (!vcpu->arch.pause),
651 if (vcpu->arch.power_off || vcpu->arch.pause) {
653 * Awaken to handle a signal, request to
656 kvm_make_request(KVM_REQ_SLEEP, vcpu);
660 if (kvm_check_request(KVM_REQ_VCPU_RESET, vcpu))
661 kvm_riscv_reset_vcpu(vcpu);
663 if (kvm_check_request(KVM_REQ_UPDATE_HGATP, vcpu))
664 kvm_riscv_stage2_update_hgatp(vcpu);
666 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
667 __kvm_riscv_hfence_gvma_all();
671 static void kvm_riscv_update_hvip(struct kvm_vcpu *vcpu)
673 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
675 csr_write(CSR_HVIP, csr->hvip);
678 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
681 struct kvm_cpu_trap trap;
682 struct kvm_run *run = vcpu->run;
684 /* Mark this VCPU ran at least once */
685 vcpu->arch.ran_atleast_once = true;
687 vcpu->arch.srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
689 /* Process MMIO value returned from user-space */
690 if (run->exit_reason == KVM_EXIT_MMIO) {
691 ret = kvm_riscv_vcpu_mmio_return(vcpu, vcpu->run);
693 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->arch.srcu_idx);
698 /* Process SBI value returned from user-space */
699 if (run->exit_reason == KVM_EXIT_RISCV_SBI) {
700 ret = kvm_riscv_vcpu_sbi_return(vcpu, vcpu->run);
702 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->arch.srcu_idx);
707 if (run->immediate_exit) {
708 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->arch.srcu_idx);
714 kvm_sigset_activate(vcpu);
717 run->exit_reason = KVM_EXIT_UNKNOWN;
719 /* Check conditions before entering the guest */
722 kvm_riscv_stage2_vmid_update(vcpu);
724 kvm_riscv_check_vcpu_requests(vcpu);
731 * Exit if we have a signal pending so that we can deliver
732 * the signal to user space.
734 if (signal_pending(current)) {
736 run->exit_reason = KVM_EXIT_INTR;
740 * Ensure we set mode to IN_GUEST_MODE after we disable
741 * interrupts and before the final VCPU requests check.
742 * See the comment in kvm_vcpu_exiting_guest_mode() and
743 * Documentation/virt/kvm/vcpu-requests.rst
745 vcpu->mode = IN_GUEST_MODE;
747 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->arch.srcu_idx);
748 smp_mb__after_srcu_read_unlock();
751 * We might have got VCPU interrupts updated asynchronously
752 * so update it in HW.
754 kvm_riscv_vcpu_flush_interrupts(vcpu);
756 /* Update HVIP CSR for current CPU */
757 kvm_riscv_update_hvip(vcpu);
760 kvm_riscv_stage2_vmid_ver_changed(&vcpu->kvm->arch.vmid) ||
761 kvm_request_pending(vcpu)) {
762 vcpu->mode = OUTSIDE_GUEST_MODE;
765 vcpu->arch.srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
769 guest_enter_irqoff();
771 __kvm_riscv_switch_to(&vcpu->arch);
773 vcpu->mode = OUTSIDE_GUEST_MODE;
777 * Save SCAUSE, STVAL, HTVAL, and HTINST because we might
778 * get an interrupt between __kvm_riscv_switch_to() and
779 * local_irq_enable() which can potentially change CSRs.
781 trap.sepc = vcpu->arch.guest_context.sepc;
782 trap.scause = csr_read(CSR_SCAUSE);
783 trap.stval = csr_read(CSR_STVAL);
784 trap.htval = csr_read(CSR_HTVAL);
785 trap.htinst = csr_read(CSR_HTINST);
787 /* Syncup interrupts state with HW */
788 kvm_riscv_vcpu_sync_interrupts(vcpu);
791 * We may have taken a host interrupt in VS/VU-mode (i.e.
792 * while executing the guest). This interrupt is still
793 * pending, as we haven't serviced it yet!
795 * We're now back in HS-mode with interrupts disabled
796 * so enabling the interrupts now will have the effect
797 * of taking the interrupt again, in HS-mode this time.
802 * We do local_irq_enable() before calling guest_exit() so
803 * that if a timer interrupt hits while running the guest
804 * we account that tick as being spent in the guest. We
805 * enable preemption after calling guest_exit() so that if
806 * we get preempted we make sure ticks after that is not
807 * counted as guest time.
813 vcpu->arch.srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
815 ret = kvm_riscv_vcpu_exit(vcpu, run, &trap);
818 kvm_sigset_deactivate(vcpu);
822 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->arch.srcu_idx);