arch/riscv/kvm/vcpu.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2019 Western Digital Corporation or its affiliates.
   4  *
   5  * Authors:
   6  *     Anup Patel <anup.patel@wdc.com>
   7  */
   8
   9 #include <linux/bitops.h>
  10 #include <linux/entry-kvm.h>
  11 #include <linux/errno.h>
  12 #include <linux/err.h>
  13 #include <linux/kdebug.h>
  14 #include <linux/module.h>
  15 #include <linux/percpu.h>
  16 #include <linux/uaccess.h>
  17 #include <linux/vmalloc.h>
  18 #include <linux/sched/signal.h>
  19 #include <linux/fs.h>
  20 #include <linux/kvm_host.h>
  21 #include <asm/csr.h>
  22 #include <asm/cacheflush.h>
  23 #include <asm/hwcap.h>
  24 #include <asm/sbi.h>
  25
  26 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = {
  27         KVM_GENERIC_VCPU_STATS(),
  28         STATS_DESC_COUNTER(VCPU, ecall_exit_stat),
  29         STATS_DESC_COUNTER(VCPU, wfi_exit_stat),
  30         STATS_DESC_COUNTER(VCPU, mmio_exit_user),
  31         STATS_DESC_COUNTER(VCPU, mmio_exit_kernel),
  32         STATS_DESC_COUNTER(VCPU, csr_exit_user),
  33         STATS_DESC_COUNTER(VCPU, csr_exit_kernel),
  34         STATS_DESC_COUNTER(VCPU, signal_exits),
  35         STATS_DESC_COUNTER(VCPU, exits)
  36 };
  37
  38 const struct kvm_stats_header kvm_vcpu_stats_header = {
  39         .name_size = KVM_STATS_NAME_SIZE,
  40         .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc),
  41         .id_offset = sizeof(struct kvm_stats_header),
  42         .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
  43         .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
  44                        sizeof(kvm_vcpu_stats_desc),
  45 };
  46
  47 #define KVM_RISCV_BASE_ISA_MASK         GENMASK(25, 0)
  48
  49 #define KVM_ISA_EXT_ARR(ext)            [KVM_RISCV_ISA_EXT_##ext] = RISCV_ISA_EXT_##ext
  50
  51 /* Mapping between KVM ISA Extension ID & Host ISA extension ID */
  52 static const unsigned long kvm_isa_ext_arr[] = {
  53         [KVM_RISCV_ISA_EXT_A] = RISCV_ISA_EXT_a,
  54         [KVM_RISCV_ISA_EXT_C] = RISCV_ISA_EXT_c,
  55         [KVM_RISCV_ISA_EXT_D] = RISCV_ISA_EXT_d,
  56         [KVM_RISCV_ISA_EXT_F] = RISCV_ISA_EXT_f,
  57         [KVM_RISCV_ISA_EXT_H] = RISCV_ISA_EXT_h,
  58         [KVM_RISCV_ISA_EXT_I] = RISCV_ISA_EXT_i,
  59         [KVM_RISCV_ISA_EXT_M] = RISCV_ISA_EXT_m,
  60         [KVM_RISCV_ISA_EXT_V] = RISCV_ISA_EXT_v,
  61
  62         KVM_ISA_EXT_ARR(SSAIA),
  63         KVM_ISA_EXT_ARR(SSTC),
  64         KVM_ISA_EXT_ARR(SVINVAL),
  65         KVM_ISA_EXT_ARR(SVPBMT),
  66         KVM_ISA_EXT_ARR(ZBB),
  67         KVM_ISA_EXT_ARR(ZIHINTPAUSE),
  68         KVM_ISA_EXT_ARR(ZICBOM),
  69         KVM_ISA_EXT_ARR(ZICBOZ),
  70 };
  71
  72 static unsigned long kvm_riscv_vcpu_base2isa_ext(unsigned long base_ext)
  73 {
  74         unsigned long i;
  75
  76         for (i = 0; i < KVM_RISCV_ISA_EXT_MAX; i++) {
  77                 if (kvm_isa_ext_arr[i] == base_ext)
  78                         return i;
  79         }
  80
  81         return KVM_RISCV_ISA_EXT_MAX;
  82 }
  83
  84 static bool kvm_riscv_vcpu_isa_enable_allowed(unsigned long ext)
  85 {
  86         switch (ext) {
  87         case KVM_RISCV_ISA_EXT_H:
  88                 return false;
  89         default:
  90                 break;
  91         }
  92
  93         return true;
  94 }
  95
  96 static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext)
  97 {
  98         switch (ext) {
  99         case KVM_RISCV_ISA_EXT_A:
 100         case KVM_RISCV_ISA_EXT_C:
 101         case KVM_RISCV_ISA_EXT_I:
 102         case KVM_RISCV_ISA_EXT_M:
 103         case KVM_RISCV_ISA_EXT_SSAIA:
 104         case KVM_RISCV_ISA_EXT_SSTC:
 105         case KVM_RISCV_ISA_EXT_SVINVAL:
 106         case KVM_RISCV_ISA_EXT_ZIHINTPAUSE:
 107         case KVM_RISCV_ISA_EXT_ZBB:
 108                 return false;
 109         default:
 110                 break;
 111         }
 112
 113         return true;
 114 }
 115
 116 static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu)
 117 {
 118         struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
 119         struct kvm_vcpu_csr *reset_csr = &vcpu->arch.guest_reset_csr;
 120         struct kvm_cpu_context *cntx = &vcpu->arch.guest_context;
 121         struct kvm_cpu_context *reset_cntx = &vcpu->arch.guest_reset_context;
 122         bool loaded;
 123
 124         /**
 125          * The preemption should be disabled here because it races with
 126          * kvm_sched_out/kvm_sched_in(called from preempt notifiers) which
 127          * also calls vcpu_load/put.
 128          */
 129         get_cpu();
 130         loaded = (vcpu->cpu != -1);
 131         if (loaded)
 132                 kvm_arch_vcpu_put(vcpu);
 133
 134         vcpu->arch.last_exit_cpu = -1;
 135
 136         memcpy(csr, reset_csr, sizeof(*csr));
 137
 138         memcpy(cntx, reset_cntx, sizeof(*cntx));
 139
 140         kvm_riscv_vcpu_fp_reset(vcpu);
 141
 142         kvm_riscv_vcpu_timer_reset(vcpu);
 143
 144         kvm_riscv_vcpu_aia_reset(vcpu);
 145
 146         bitmap_zero(vcpu->arch.irqs_pending, KVM_RISCV_VCPU_NR_IRQS);
 147         bitmap_zero(vcpu->arch.irqs_pending_mask, KVM_RISCV_VCPU_NR_IRQS);
 148
 149         kvm_riscv_vcpu_pmu_reset(vcpu);
 150
 151         vcpu->arch.hfence_head = 0;
 152         vcpu->arch.hfence_tail = 0;
 153         memset(vcpu->arch.hfence_queue, 0, sizeof(vcpu->arch.hfence_queue));
 154
 155         /* Reset the guest CSRs for hotplug usecase */
 156         if (loaded)
 157                 kvm_arch_vcpu_load(vcpu, smp_processor_id());
 158         put_cpu();
 159 }
 160
 161 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
 162 {
 163         return 0;
 164 }
 165
 166 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
 167 {
 168         int rc;
 169         struct kvm_cpu_context *cntx;
 170         struct kvm_vcpu_csr *reset_csr = &vcpu->arch.guest_reset_csr;
 171         unsigned long host_isa, i;
 172
 173         /* Mark this VCPU never ran */
 174         vcpu->arch.ran_atleast_once = false;
 175         vcpu->arch.mmu_page_cache.gfp_zero = __GFP_ZERO;
 176         bitmap_zero(vcpu->arch.isa, RISCV_ISA_EXT_MAX);
 177
 178         /* Setup ISA features available to VCPU */
 179         for (i = 0; i < ARRAY_SIZE(kvm_isa_ext_arr); i++) {
 180                 host_isa = kvm_isa_ext_arr[i];
 181                 if (__riscv_isa_extension_available(NULL, host_isa) &&
 182                     kvm_riscv_vcpu_isa_enable_allowed(i))
 183                         set_bit(host_isa, vcpu->arch.isa);
 184         }
 185
 186         /* Setup vendor, arch, and implementation details */
 187         vcpu->arch.mvendorid = sbi_get_mvendorid();
 188         vcpu->arch.marchid = sbi_get_marchid();
 189         vcpu->arch.mimpid = sbi_get_mimpid();
 190
 191         /* Setup VCPU hfence queue */
 192         spin_lock_init(&vcpu->arch.hfence_lock);
 193
 194         /* Setup reset state of shadow SSTATUS and HSTATUS CSRs */
 195         cntx = &vcpu->arch.guest_reset_context;
 196         cntx->sstatus = SR_SPP | SR_SPIE;
 197         cntx->hstatus = 0;
 198         cntx->hstatus |= HSTATUS_VTW;
 199         cntx->hstatus |= HSTATUS_SPVP;
 200         cntx->hstatus |= HSTATUS_SPV;
 201
 202         /* By default, make CY, TM, and IR counters accessible in VU mode */
 203         reset_csr->scounteren = 0x7;
 204
 205         /* Setup VCPU timer */
 206         kvm_riscv_vcpu_timer_init(vcpu);
 207
 208         /* setup performance monitoring */
 209         kvm_riscv_vcpu_pmu_init(vcpu);
 210
 211         /* Setup VCPU AIA */
 212         rc = kvm_riscv_vcpu_aia_init(vcpu);
 213         if (rc)
 214                 return rc;
 215
 216         /* Reset VCPU */
 217         kvm_riscv_reset_vcpu(vcpu);
 218
 219         return 0;
 220 }
 221
 222 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
 223 {
 224         /**
 225          * vcpu with id 0 is the designated boot cpu.
 226          * Keep all vcpus with non-zero id in power-off state so that
 227          * they can be brought up using SBI HSM extension.
 228          */
 229         if (vcpu->vcpu_idx != 0)
 230                 kvm_riscv_vcpu_power_off(vcpu);
 231 }
 232
 233 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
 234 {
 235         /* Cleanup VCPU AIA context */
 236         kvm_riscv_vcpu_aia_deinit(vcpu);
 237
 238         /* Cleanup VCPU timer */
 239         kvm_riscv_vcpu_timer_deinit(vcpu);
 240
 241         kvm_riscv_vcpu_pmu_deinit(vcpu);
 242
 243         /* Free unused pages pre-allocated for G-stage page table mappings */
 244         kvm_mmu_free_memory_cache(&vcpu->arch.mmu_page_cache);
 245 }
 246
 247 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
 248 {
 249         return kvm_riscv_vcpu_timer_pending(vcpu);
 250 }
 251
 252 void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu)
 253 {
 254 }
 255
 256 void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu)
 257 {
 258 }
 259
 260 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
 261 {
 262         return (kvm_riscv_vcpu_has_interrupts(vcpu, -1UL) &&
 263                 !vcpu->arch.power_off && !vcpu->arch.pause);
 264 }
 265
 266 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
 267 {
 268         return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
 269 }
 270
 271 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
 272 {
 273         return (vcpu->arch.guest_context.sstatus & SR_SPP) ? true : false;
 274 }
 275
 276 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
 277 {
 278         return VM_FAULT_SIGBUS;
 279 }
 280
 281 static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu,
 282                                          const struct kvm_one_reg *reg)
 283 {
 284         unsigned long __user *uaddr =
 285                         (unsigned long __user *)(unsigned long)reg->addr;
 286         unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
 287                                             KVM_REG_SIZE_MASK |
 288                                             KVM_REG_RISCV_CONFIG);
 289         unsigned long reg_val;
 290
 291         if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
 292                 return -EINVAL;
 293
 294         switch (reg_num) {
 295         case KVM_REG_RISCV_CONFIG_REG(isa):
 296                 reg_val = vcpu->arch.isa[0] & KVM_RISCV_BASE_ISA_MASK;
 297                 break;
 298         case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):
 299                 if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOM))
 300                         return -EINVAL;
 301                 reg_val = riscv_cbom_block_size;
 302                 break;
 303         case KVM_REG_RISCV_CONFIG_REG(zicboz_block_size):
 304                 if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOZ))
 305                         return -EINVAL;
 306                 reg_val = riscv_cboz_block_size;
 307                 break;
 308         case KVM_REG_RISCV_CONFIG_REG(mvendorid):
 309                 reg_val = vcpu->arch.mvendorid;
 310                 break;
 311         case KVM_REG_RISCV_CONFIG_REG(marchid):
 312                 reg_val = vcpu->arch.marchid;
 313                 break;
 314         case KVM_REG_RISCV_CONFIG_REG(mimpid):
 315                 reg_val = vcpu->arch.mimpid;
 316                 break;
 317         default:
 318                 return -EINVAL;
 319         }
 320
 321         if (copy_to_user(uaddr, &reg_val, KVM_REG_SIZE(reg->id)))
 322                 return -EFAULT;
 323
 324         return 0;
 325 }
 326
 327 static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu,
 328                                          const struct kvm_one_reg *reg)
 329 {
 330         unsigned long __user *uaddr =
 331                         (unsigned long __user *)(unsigned long)reg->addr;
 332         unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
 333                                             KVM_REG_SIZE_MASK |
 334                                             KVM_REG_RISCV_CONFIG);
 335         unsigned long i, isa_ext, reg_val;
 336
 337         if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
 338                 return -EINVAL;
 339
 340         if (copy_from_user(&reg_val, uaddr, KVM_REG_SIZE(reg->id)))
 341                 return -EFAULT;
 342
 343         switch (reg_num) {
 344         case KVM_REG_RISCV_CONFIG_REG(isa):
 345                 /*
 346                  * This ONE REG interface is only defined for
 347                  * single letter extensions.
 348                  */
 349                 if (fls(reg_val) >= RISCV_ISA_EXT_BASE)
 350                         return -EINVAL;
 351
 352                 if (!vcpu->arch.ran_atleast_once) {
 353                         /* Ignore the enable/disable request for certain extensions */
 354                         for (i = 0; i < RISCV_ISA_EXT_BASE; i++) {
 355                                 isa_ext = kvm_riscv_vcpu_base2isa_ext(i);
 356                                 if (isa_ext >= KVM_RISCV_ISA_EXT_MAX) {
 357                                         reg_val &= ~BIT(i);
 358                                         continue;
 359                                 }
 360                                 if (!kvm_riscv_vcpu_isa_enable_allowed(isa_ext))
 361                                         if (reg_val & BIT(i))
 362                                                 reg_val &= ~BIT(i);
 363                                 if (!kvm_riscv_vcpu_isa_disable_allowed(isa_ext))
 364                                         if (!(reg_val & BIT(i)))
 365                                                 reg_val |= BIT(i);
 366                         }
 367                         reg_val &= riscv_isa_extension_base(NULL);
 368                         /* Do not modify anything beyond single letter extensions */
 369                         reg_val = (vcpu->arch.isa[0] & ~KVM_RISCV_BASE_ISA_MASK) |
 370                                   (reg_val & KVM_RISCV_BASE_ISA_MASK);
 371                         vcpu->arch.isa[0] = reg_val;
 372                         kvm_riscv_vcpu_fp_reset(vcpu);
 373                 } else {
 374                         return -EOPNOTSUPP;
 375                 }
 376                 break;
 377         case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):
 378                 return -EOPNOTSUPP;
 379         case KVM_REG_RISCV_CONFIG_REG(zicboz_block_size):
 380                 return -EOPNOTSUPP;
 381         case KVM_REG_RISCV_CONFIG_REG(mvendorid):
 382                 if (!vcpu->arch.ran_atleast_once)
 383                         vcpu->arch.mvendorid = reg_val;
 384                 else
 385                         return -EBUSY;
 386                 break;
 387         case KVM_REG_RISCV_CONFIG_REG(marchid):
 388                 if (!vcpu->arch.ran_atleast_once)
 389                         vcpu->arch.marchid = reg_val;
 390                 else
 391                         return -EBUSY;
 392                 break;
 393         case KVM_REG_RISCV_CONFIG_REG(mimpid):
 394                 if (!vcpu->arch.ran_atleast_once)
 395                         vcpu->arch.mimpid = reg_val;
 396                 else
 397                         return -EBUSY;
 398                 break;
 399         default:
 400                 return -EINVAL;
 401         }
 402
 403         return 0;
 404 }
 405
 406 static int kvm_riscv_vcpu_get_reg_core(struct kvm_vcpu *vcpu,
 407                                        const struct kvm_one_reg *reg)
 408 {
 409         struct kvm_cpu_context *cntx = &vcpu->arch.guest_context;
 410         unsigned long __user *uaddr =
 411                         (unsigned long __user *)(unsigned long)reg->addr;
 412         unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
 413                                             KVM_REG_SIZE_MASK |
 414                                             KVM_REG_RISCV_CORE);
 415         unsigned long reg_val;
 416
 417         if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
 418                 return -EINVAL;
 419         if (reg_num >= sizeof(struct kvm_riscv_core) / sizeof(unsigned long))
 420                 return -EINVAL;
 421
 422         if (reg_num == KVM_REG_RISCV_CORE_REG(regs.pc))
 423                 reg_val = cntx->sepc;
 424         else if (KVM_REG_RISCV_CORE_REG(regs.pc) < reg_num &&
 425                  reg_num <= KVM_REG_RISCV_CORE_REG(regs.t6))
 426                 reg_val = ((unsigned long *)cntx)[reg_num];
 427         else if (reg_num == KVM_REG_RISCV_CORE_REG(mode))
 428                 reg_val = (cntx->sstatus & SR_SPP) ?
 429                                 KVM_RISCV_MODE_S : KVM_RISCV_MODE_U;
 430         else
 431                 return -EINVAL;
 432
 433         if (copy_to_user(uaddr, &reg_val, KVM_REG_SIZE(reg->id)))
 434                 return -EFAULT;
 435
 436         return 0;
 437 }
 438
 439 static int kvm_riscv_vcpu_set_reg_core(struct kvm_vcpu *vcpu,
 440                                        const struct kvm_one_reg *reg)
 441 {
 442         struct kvm_cpu_context *cntx = &vcpu->arch.guest_context;
 443         unsigned long __user *uaddr =
 444                         (unsigned long __user *)(unsigned long)reg->addr;
 445         unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
 446                                             KVM_REG_SIZE_MASK |
 447                                             KVM_REG_RISCV_CORE);
 448         unsigned long reg_val;
 449
 450         if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
 451                 return -EINVAL;
 452         if (reg_num >= sizeof(struct kvm_riscv_core) / sizeof(unsigned long))
 453                 return -EINVAL;
 454
 455         if (copy_from_user(&reg_val, uaddr, KVM_REG_SIZE(reg->id)))
 456                 return -EFAULT;
 457
 458         if (reg_num == KVM_REG_RISCV_CORE_REG(regs.pc))
 459                 cntx->sepc = reg_val;
 460         else if (KVM_REG_RISCV_CORE_REG(regs.pc) < reg_num &&
 461                  reg_num <= KVM_REG_RISCV_CORE_REG(regs.t6))
 462                 ((unsigned long *)cntx)[reg_num] = reg_val;
 463         else if (reg_num == KVM_REG_RISCV_CORE_REG(mode)) {
 464                 if (reg_val == KVM_RISCV_MODE_S)
 465                         cntx->sstatus |= SR_SPP;
 466                 else
 467                         cntx->sstatus &= ~SR_SPP;
 468         } else
 469                 return -EINVAL;
 470
 471         return 0;
 472 }
 473
 474 static int kvm_riscv_vcpu_general_get_csr(struct kvm_vcpu *vcpu,
 475                                           unsigned long reg_num,
 476                                           unsigned long *out_val)
 477 {
 478         struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
 479
 480         if (reg_num >= sizeof(struct kvm_riscv_csr) / sizeof(unsigned long))
 481                 return -EINVAL;
 482
 483         if (reg_num == KVM_REG_RISCV_CSR_REG(sip)) {
 484                 kvm_riscv_vcpu_flush_interrupts(vcpu);
 485                 *out_val = (csr->hvip >> VSIP_TO_HVIP_SHIFT) & VSIP_VALID_MASK;
 486                 *out_val |= csr->hvip & ~IRQ_LOCAL_MASK;
 487         } else
 488                 *out_val = ((unsigned long *)csr)[reg_num];
 489
 490         return 0;
 491 }
 492
 493 static inline int kvm_riscv_vcpu_general_set_csr(struct kvm_vcpu *vcpu,
 494                                                  unsigned long reg_num,
 495                                                  unsigned long reg_val)
 496 {
 497         struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
 498
 499         if (reg_num >= sizeof(struct kvm_riscv_csr) / sizeof(unsigned long))
 500                 return -EINVAL;
 501
 502         if (reg_num == KVM_REG_RISCV_CSR_REG(sip)) {
 503                 reg_val &= VSIP_VALID_MASK;
 504                 reg_val <<= VSIP_TO_HVIP_SHIFT;
 505         }
 506
 507         ((unsigned long *)csr)[reg_num] = reg_val;
 508
 509         if (reg_num == KVM_REG_RISCV_CSR_REG(sip))
 510                 WRITE_ONCE(vcpu->arch.irqs_pending_mask[0], 0);
 511
 512         return 0;
 513 }
 514
 515 static int kvm_riscv_vcpu_get_reg_csr(struct kvm_vcpu *vcpu,
 516                                       const struct kvm_one_reg *reg)
 517 {
 518         int rc;
 519         unsigned long __user *uaddr =
 520                         (unsigned long __user *)(unsigned long)reg->addr;
 521         unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
 522                                             KVM_REG_SIZE_MASK |
 523                                             KVM_REG_RISCV_CSR);
 524         unsigned long reg_val, reg_subtype;
 525
 526         if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
 527                 return -EINVAL;
 528
 529         reg_subtype = reg_num & KVM_REG_RISCV_SUBTYPE_MASK;
 530         reg_num &= ~KVM_REG_RISCV_SUBTYPE_MASK;
 531         switch (reg_subtype) {
 532         case KVM_REG_RISCV_CSR_GENERAL:
 533                 rc = kvm_riscv_vcpu_general_get_csr(vcpu, reg_num, &reg_val);
 534                 break;
 535         case KVM_REG_RISCV_CSR_AIA:
 536                 rc = kvm_riscv_vcpu_aia_get_csr(vcpu, reg_num, &reg_val);
 537                 break;
 538         default:
 539                 rc = -EINVAL;
 540                 break;
 541         }
 542         if (rc)
 543                 return rc;
 544
 545         if (copy_to_user(uaddr, &reg_val, KVM_REG_SIZE(reg->id)))
 546                 return -EFAULT;
 547
 548         return 0;
 549 }
 550
 551 static int kvm_riscv_vcpu_set_reg_csr(struct kvm_vcpu *vcpu,
 552                                       const struct kvm_one_reg *reg)
 553 {
 554         int rc;
 555         unsigned long __user *uaddr =
 556                         (unsigned long __user *)(unsigned long)reg->addr;
 557         unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
 558                                             KVM_REG_SIZE_MASK |
 559                                             KVM_REG_RISCV_CSR);
 560         unsigned long reg_val, reg_subtype;
 561
 562         if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
 563                 return -EINVAL;
 564
 565         if (copy_from_user(&reg_val, uaddr, KVM_REG_SIZE(reg->id)))
 566                 return -EFAULT;
 567
 568         reg_subtype = reg_num & KVM_REG_RISCV_SUBTYPE_MASK;
 569         reg_num &= ~KVM_REG_RISCV_SUBTYPE_MASK;
 570         switch (reg_subtype) {
 571         case KVM_REG_RISCV_CSR_GENERAL:
 572                 rc = kvm_riscv_vcpu_general_set_csr(vcpu, reg_num, reg_val);
 573                 break;
 574         case KVM_REG_RISCV_CSR_AIA:
 575                 rc = kvm_riscv_vcpu_aia_set_csr(vcpu, reg_num, reg_val);
 576                 break;
 577         default:
 578                 rc = -EINVAL;
 579                 break;
 580         }
 581         if (rc)
 582                 return rc;
 583
 584         return 0;
 585 }
 586
 587 static int kvm_riscv_vcpu_get_reg_isa_ext(struct kvm_vcpu *vcpu,
 588                                           const struct kvm_one_reg *reg)
 589 {
 590         unsigned long __user *uaddr =
 591                         (unsigned long __user *)(unsigned long)reg->addr;
 592         unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
 593                                             KVM_REG_SIZE_MASK |
 594                                             KVM_REG_RISCV_ISA_EXT);
 595         unsigned long reg_val = 0;
 596         unsigned long host_isa_ext;
 597
 598         if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
 599                 return -EINVAL;
 600
 601         if (reg_num >= KVM_RISCV_ISA_EXT_MAX ||
 602             reg_num >= ARRAY_SIZE(kvm_isa_ext_arr))
 603                 return -EINVAL;
 604
 605         host_isa_ext = kvm_isa_ext_arr[reg_num];
 606         if (__riscv_isa_extension_available(vcpu->arch.isa, host_isa_ext))
 607                 reg_val = 1; /* Mark the given extension as available */
 608
 609         if (copy_to_user(uaddr, &reg_val, KVM_REG_SIZE(reg->id)))
 610                 return -EFAULT;
 611
 612         return 0;
 613 }
 614
 615 static int kvm_riscv_vcpu_set_reg_isa_ext(struct kvm_vcpu *vcpu,
 616                                           const struct kvm_one_reg *reg)
 617 {
 618         unsigned long __user *uaddr =
 619                         (unsigned long __user *)(unsigned long)reg->addr;
 620         unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK |
 621                                             KVM_REG_SIZE_MASK |
 622                                             KVM_REG_RISCV_ISA_EXT);
 623         unsigned long reg_val;
 624         unsigned long host_isa_ext;
 625
 626         if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long))
 627                 return -EINVAL;
 628
 629         if (reg_num >= KVM_RISCV_ISA_EXT_MAX ||
 630             reg_num >= ARRAY_SIZE(kvm_isa_ext_arr))
 631                 return -EINVAL;
 632
 633         if (copy_from_user(&reg_val, uaddr, KVM_REG_SIZE(reg->id)))
 634                 return -EFAULT;
 635
 636         host_isa_ext = kvm_isa_ext_arr[reg_num];
 637         if (!__riscv_isa_extension_available(NULL, host_isa_ext))
 638                 return  -EOPNOTSUPP;
 639
 640         if (!vcpu->arch.ran_atleast_once) {
 641                 /*
 642                  * All multi-letter extension and a few single letter
 643                  * extension can be disabled
 644                  */
 645                 if (reg_val == 1 &&
 646                     kvm_riscv_vcpu_isa_enable_allowed(reg_num))
 647                         set_bit(host_isa_ext, vcpu->arch.isa);
 648                 else if (!reg_val &&
 649                          kvm_riscv_vcpu_isa_disable_allowed(reg_num))
 650                         clear_bit(host_isa_ext, vcpu->arch.isa);
 651                 else
 652                         return -EINVAL;
 653                 kvm_riscv_vcpu_fp_reset(vcpu);
 654         } else {
 655                 return -EOPNOTSUPP;
 656         }
 657
 658         return 0;
 659 }
 660
 661 static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu,
 662                                   const struct kvm_one_reg *reg)
 663 {
 664         switch (reg->id & KVM_REG_RISCV_TYPE_MASK) {
 665         case KVM_REG_RISCV_CONFIG:
 666                 return kvm_riscv_vcpu_set_reg_config(vcpu, reg);
 667         case KVM_REG_RISCV_CORE:
 668                 return kvm_riscv_vcpu_set_reg_core(vcpu, reg);
 669         case KVM_REG_RISCV_CSR:
 670                 return kvm_riscv_vcpu_set_reg_csr(vcpu, reg);
 671         case KVM_REG_RISCV_TIMER:
 672                 return kvm_riscv_vcpu_set_reg_timer(vcpu, reg);
 673         case KVM_REG_RISCV_FP_F:
 674                 return kvm_riscv_vcpu_set_reg_fp(vcpu, reg,
 675                                                  KVM_REG_RISCV_FP_F);
 676         case KVM_REG_RISCV_FP_D:
 677                 return kvm_riscv_vcpu_set_reg_fp(vcpu, reg,
 678                                                  KVM_REG_RISCV_FP_D);
 679         case KVM_REG_RISCV_ISA_EXT:
 680                 return kvm_riscv_vcpu_set_reg_isa_ext(vcpu, reg);
 681         case KVM_REG_RISCV_SBI_EXT:
 682                 return kvm_riscv_vcpu_set_reg_sbi_ext(vcpu, reg);
 683         default:
 684                 break;
 685         }
 686
 687         return -EINVAL;
 688 }
 689
 690 static int kvm_riscv_vcpu_get_reg(struct kvm_vcpu *vcpu,
 691                                   const struct kvm_one_reg *reg)
 692 {
 693         switch (reg->id & KVM_REG_RISCV_TYPE_MASK) {
 694         case KVM_REG_RISCV_CONFIG:
 695                 return kvm_riscv_vcpu_get_reg_config(vcpu, reg);
 696         case KVM_REG_RISCV_CORE:
 697                 return kvm_riscv_vcpu_get_reg_core(vcpu, reg);
 698         case KVM_REG_RISCV_CSR:
 699                 return kvm_riscv_vcpu_get_reg_csr(vcpu, reg);
 700         case KVM_REG_RISCV_TIMER:
 701                 return kvm_riscv_vcpu_get_reg_timer(vcpu, reg);
 702         case KVM_REG_RISCV_FP_F:
 703                 return kvm_riscv_vcpu_get_reg_fp(vcpu, reg,
 704                                                  KVM_REG_RISCV_FP_F);
 705         case KVM_REG_RISCV_FP_D:
 706                 return kvm_riscv_vcpu_get_reg_fp(vcpu, reg,
 707                                                  KVM_REG_RISCV_FP_D);
 708         case KVM_REG_RISCV_ISA_EXT:
 709                 return kvm_riscv_vcpu_get_reg_isa_ext(vcpu, reg);
 710         case KVM_REG_RISCV_SBI_EXT:
 711                 return kvm_riscv_vcpu_get_reg_sbi_ext(vcpu, reg);
 712         default:
 713                 break;
 714         }
 715
 716         return -EINVAL;
 717 }
 718
 719 long kvm_arch_vcpu_async_ioctl(struct file *filp,
 720                                unsigned int ioctl, unsigned long arg)
 721 {
 722         struct kvm_vcpu *vcpu = filp->private_data;
 723         void __user *argp = (void __user *)arg;
 724
 725         if (ioctl == KVM_INTERRUPT) {
 726                 struct kvm_interrupt irq;
 727
 728                 if (copy_from_user(&irq, argp, sizeof(irq)))
 729                         return -EFAULT;
 730
 731                 if (irq.irq == KVM_INTERRUPT_SET)
 732                         return kvm_riscv_vcpu_set_interrupt(vcpu, IRQ_VS_EXT);
 733                 else
 734                         return kvm_riscv_vcpu_unset_interrupt(vcpu, IRQ_VS_EXT);
 735         }
 736
 737         return -ENOIOCTLCMD;
 738 }
 739
 740 long kvm_arch_vcpu_ioctl(struct file *filp,
 741                          unsigned int ioctl, unsigned long arg)
 742 {
 743         struct kvm_vcpu *vcpu = filp->private_data;
 744         void __user *argp = (void __user *)arg;
 745         long r = -EINVAL;
 746
 747         switch (ioctl) {
 748         case KVM_SET_ONE_REG:
 749         case KVM_GET_ONE_REG: {
 750                 struct kvm_one_reg reg;
 751
 752                 r = -EFAULT;
 753                 if (copy_from_user(&reg, argp, sizeof(reg)))
 754                         break;
 755
 756                 if (ioctl == KVM_SET_ONE_REG)
 757                         r = kvm_riscv_vcpu_set_reg(vcpu, &reg);
 758                 else
 759                         r = kvm_riscv_vcpu_get_reg(vcpu, &reg);
 760                 break;
 761         }
 762         default:
 763                 break;
 764         }
 765
 766         return r;
 767 }
 768
 769 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
 770                                   struct kvm_sregs *sregs)
 771 {
 772         return -EINVAL;
 773 }
 774
 775 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
 776                                   struct kvm_sregs *sregs)
 777 {
 778         return -EINVAL;
 779 }
 780
 781 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
 782 {
 783         return -EINVAL;
 784 }
 785
 786 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
 787 {
 788         return -EINVAL;
 789 }
 790
 791 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
 792                                   struct kvm_translation *tr)
 793 {
 794         return -EINVAL;
 795 }
 796
 797 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
 798 {
 799         return -EINVAL;
 800 }
 801
 802 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
 803 {
 804         return -EINVAL;
 805 }
 806
 807 void kvm_riscv_vcpu_flush_interrupts(struct kvm_vcpu *vcpu)
 808 {
 809         struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
 810         unsigned long mask, val;
 811
 812         if (READ_ONCE(vcpu->arch.irqs_pending_mask[0])) {
 813                 mask = xchg_acquire(&vcpu->arch.irqs_pending_mask[0], 0);
 814                 val = READ_ONCE(vcpu->arch.irqs_pending[0]) & mask;
 815
 816                 csr->hvip &= ~mask;
 817                 csr->hvip |= val;
 818         }
 819
 820         /* Flush AIA high interrupts */
 821         kvm_riscv_vcpu_aia_flush_interrupts(vcpu);
 822 }
 823
 824 void kvm_riscv_vcpu_sync_interrupts(struct kvm_vcpu *vcpu)
 825 {
 826         unsigned long hvip;
 827         struct kvm_vcpu_arch *v = &vcpu->arch;
 828         struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
 829
 830         /* Read current HVIP and VSIE CSRs */
 831         csr->vsie = csr_read(CSR_VSIE);
 832
 833         /* Sync-up HVIP.VSSIP bit changes does by Guest */
 834         hvip = csr_read(CSR_HVIP);
 835         if ((csr->hvip ^ hvip) & (1UL << IRQ_VS_SOFT)) {
 836                 if (hvip & (1UL << IRQ_VS_SOFT)) {
 837                         if (!test_and_set_bit(IRQ_VS_SOFT,
 838                                               v->irqs_pending_mask))
 839                                 set_bit(IRQ_VS_SOFT, v->irqs_pending);
 840                 } else {
 841                         if (!test_and_set_bit(IRQ_VS_SOFT,
 842                                               v->irqs_pending_mask))
 843                                 clear_bit(IRQ_VS_SOFT, v->irqs_pending);
 844                 }
 845         }
 846
 847         /* Sync-up AIA high interrupts */
 848         kvm_riscv_vcpu_aia_sync_interrupts(vcpu);
 849
 850         /* Sync-up timer CSRs */
 851         kvm_riscv_vcpu_timer_sync(vcpu);
 852 }
 853
 854 int kvm_riscv_vcpu_set_interrupt(struct kvm_vcpu *vcpu, unsigned int irq)
 855 {
 856         /*
 857          * We only allow VS-mode software, timer, and external
 858          * interrupts when irq is one of the local interrupts
 859          * defined by RISC-V privilege specification.
 860          */
 861         if (irq < IRQ_LOCAL_MAX &&
 862             irq != IRQ_VS_SOFT &&
 863             irq != IRQ_VS_TIMER &&
 864             irq != IRQ_VS_EXT)
 865                 return -EINVAL;
 866
 867         set_bit(irq, vcpu->arch.irqs_pending);
 868         smp_mb__before_atomic();
 869         set_bit(irq, vcpu->arch.irqs_pending_mask);
 870
 871         kvm_vcpu_kick(vcpu);
 872
 873         return 0;
 874 }
 875
 876 int kvm_riscv_vcpu_unset_interrupt(struct kvm_vcpu *vcpu, unsigned int irq)
 877 {
 878         /*
 879          * We only allow VS-mode software, timer, and external
 880          * interrupts when irq is one of the local interrupts
 881          * defined by RISC-V privilege specification.
 882          */
 883         if (irq < IRQ_LOCAL_MAX &&
 884             irq != IRQ_VS_SOFT &&
 885             irq != IRQ_VS_TIMER &&
 886             irq != IRQ_VS_EXT)
 887                 return -EINVAL;
 888
 889         clear_bit(irq, vcpu->arch.irqs_pending);
 890         smp_mb__before_atomic();
 891         set_bit(irq, vcpu->arch.irqs_pending_mask);
 892
 893         return 0;
 894 }
 895
 896 bool kvm_riscv_vcpu_has_interrupts(struct kvm_vcpu *vcpu, u64 mask)
 897 {
 898         unsigned long ie;
 899
 900         ie = ((vcpu->arch.guest_csr.vsie & VSIP_VALID_MASK)
 901                 << VSIP_TO_HVIP_SHIFT) & (unsigned long)mask;
 902         ie |= vcpu->arch.guest_csr.vsie & ~IRQ_LOCAL_MASK &
 903                 (unsigned long)mask;
 904         if (READ_ONCE(vcpu->arch.irqs_pending[0]) & ie)
 905                 return true;
 906
 907         /* Check AIA high interrupts */
 908         return kvm_riscv_vcpu_aia_has_interrupts(vcpu, mask);
 909 }
 910
 911 void kvm_riscv_vcpu_power_off(struct kvm_vcpu *vcpu)
 912 {
 913         vcpu->arch.power_off = true;
 914         kvm_make_request(KVM_REQ_SLEEP, vcpu);
 915         kvm_vcpu_kick(vcpu);
 916 }
 917
 918 void kvm_riscv_vcpu_power_on(struct kvm_vcpu *vcpu)
 919 {
 920         vcpu->arch.power_off = false;
 921         kvm_vcpu_wake_up(vcpu);
 922 }
 923
 924 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
 925                                     struct kvm_mp_state *mp_state)
 926 {
 927         if (vcpu->arch.power_off)
 928                 mp_state->mp_state = KVM_MP_STATE_STOPPED;
 929         else
 930                 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
 931
 932         return 0;
 933 }
 934
 935 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
 936                                     struct kvm_mp_state *mp_state)
 937 {
 938         int ret = 0;
 939
 940         switch (mp_state->mp_state) {
 941         case KVM_MP_STATE_RUNNABLE:
 942                 vcpu->arch.power_off = false;
 943                 break;
 944         case KVM_MP_STATE_STOPPED:
 945                 kvm_riscv_vcpu_power_off(vcpu);
 946                 break;
 947         default:
 948                 ret = -EINVAL;
 949         }
 950
 951         return ret;
 952 }
 953
 954 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
 955                                         struct kvm_guest_debug *dbg)
 956 {
 957         /* TODO; To be implemented later. */
 958         return -EINVAL;
 959 }
 960
 961 static void kvm_riscv_vcpu_update_config(const unsigned long *isa)
 962 {
 963         u64 henvcfg = 0;
 964
 965         if (riscv_isa_extension_available(isa, SVPBMT))
 966                 henvcfg |= ENVCFG_PBMTE;
 967
 968         if (riscv_isa_extension_available(isa, SSTC))
 969                 henvcfg |= ENVCFG_STCE;
 970
 971         if (riscv_isa_extension_available(isa, ZICBOM))
 972                 henvcfg |= (ENVCFG_CBIE | ENVCFG_CBCFE);
 973
 974         if (riscv_isa_extension_available(isa, ZICBOZ))
 975                 henvcfg |= ENVCFG_CBZE;
 976
 977         csr_write(CSR_HENVCFG, henvcfg);
 978 #ifdef CONFIG_32BIT
 979         csr_write(CSR_HENVCFGH, henvcfg >> 32);
 980 #endif
 981 }
 982
 983 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 984 {
 985         struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
 986
 987         csr_write(CSR_VSSTATUS, csr->vsstatus);
 988         csr_write(CSR_VSIE, csr->vsie);
 989         csr_write(CSR_VSTVEC, csr->vstvec);
 990         csr_write(CSR_VSSCRATCH, csr->vsscratch);
 991         csr_write(CSR_VSEPC, csr->vsepc);
 992         csr_write(CSR_VSCAUSE, csr->vscause);
 993         csr_write(CSR_VSTVAL, csr->vstval);
 994         csr_write(CSR_HVIP, csr->hvip);
 995         csr_write(CSR_VSATP, csr->vsatp);
 996
 997         kvm_riscv_vcpu_update_config(vcpu->arch.isa);
 998
 999         kvm_riscv_gstage_update_hgatp(vcpu);
1000
1001         kvm_riscv_vcpu_timer_restore(vcpu);
1002
1003         kvm_riscv_vcpu_host_fp_save(&vcpu->arch.host_context);
1004         kvm_riscv_vcpu_guest_fp_restore(&vcpu->arch.guest_context,
1005                                         vcpu->arch.isa);
1006
1007         kvm_riscv_vcpu_aia_load(vcpu, cpu);
1008
1009         vcpu->cpu = cpu;
1010 }
1011
1012 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1013 {
1014         struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
1015
1016         vcpu->cpu = -1;
1017
1018         kvm_riscv_vcpu_aia_put(vcpu);
1019
1020         kvm_riscv_vcpu_guest_fp_save(&vcpu->arch.guest_context,
1021                                      vcpu->arch.isa);
1022         kvm_riscv_vcpu_host_fp_restore(&vcpu->arch.host_context);
1023
1024         kvm_riscv_vcpu_timer_save(vcpu);
1025
1026         csr->vsstatus = csr_read(CSR_VSSTATUS);
1027         csr->vsie = csr_read(CSR_VSIE);
1028         csr->vstvec = csr_read(CSR_VSTVEC);
1029         csr->vsscratch = csr_read(CSR_VSSCRATCH);
1030         csr->vsepc = csr_read(CSR_VSEPC);
1031         csr->vscause = csr_read(CSR_VSCAUSE);
1032         csr->vstval = csr_read(CSR_VSTVAL);
1033         csr->hvip = csr_read(CSR_HVIP);
1034         csr->vsatp = csr_read(CSR_VSATP);
1035 }
1036
1037 static void kvm_riscv_check_vcpu_requests(struct kvm_vcpu *vcpu)
1038 {
1039         struct rcuwait *wait = kvm_arch_vcpu_get_wait(vcpu);
1040
1041         if (kvm_request_pending(vcpu)) {
1042                 if (kvm_check_request(KVM_REQ_SLEEP, vcpu)) {
1043                         kvm_vcpu_srcu_read_unlock(vcpu);
1044                         rcuwait_wait_event(wait,
1045                                 (!vcpu->arch.power_off) && (!vcpu->arch.pause),
1046                                 TASK_INTERRUPTIBLE);
1047                         kvm_vcpu_srcu_read_lock(vcpu);
1048
1049                         if (vcpu->arch.power_off || vcpu->arch.pause) {
1050                                 /*
1051                                  * Awaken to handle a signal, request to
1052                                  * sleep again later.
1053                                  */
1054                                 kvm_make_request(KVM_REQ_SLEEP, vcpu);
1055                         }
1056                 }
1057
1058                 if (kvm_check_request(KVM_REQ_VCPU_RESET, vcpu))
1059                         kvm_riscv_reset_vcpu(vcpu);
1060
1061                 if (kvm_check_request(KVM_REQ_UPDATE_HGATP, vcpu))
1062                         kvm_riscv_gstage_update_hgatp(vcpu);
1063
1064                 if (kvm_check_request(KVM_REQ_FENCE_I, vcpu))
1065                         kvm_riscv_fence_i_process(vcpu);
1066
1067                 /*
1068                  * The generic KVM_REQ_TLB_FLUSH is same as
1069                  * KVM_REQ_HFENCE_GVMA_VMID_ALL
1070                  */
1071                 if (kvm_check_request(KVM_REQ_HFENCE_GVMA_VMID_ALL, vcpu))
1072                         kvm_riscv_hfence_gvma_vmid_all_process(vcpu);
1073
1074                 if (kvm_check_request(KVM_REQ_HFENCE_VVMA_ALL, vcpu))
1075                         kvm_riscv_hfence_vvma_all_process(vcpu);
1076
1077                 if (kvm_check_request(KVM_REQ_HFENCE, vcpu))
1078                         kvm_riscv_hfence_process(vcpu);
1079         }
1080 }
1081
1082 static void kvm_riscv_update_hvip(struct kvm_vcpu *vcpu)
1083 {
1084         struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr;
1085
1086         csr_write(CSR_HVIP, csr->hvip);
1087         kvm_riscv_vcpu_aia_update_hvip(vcpu);
1088 }
1089
1090 /*
1091  * Actually run the vCPU, entering an RCU extended quiescent state (EQS) while
1092  * the vCPU is running.
1093  *
1094  * This must be noinstr as instrumentation may make use of RCU, and this is not
1095  * safe during the EQS.
1096  */
1097 static void noinstr kvm_riscv_vcpu_enter_exit(struct kvm_vcpu *vcpu)
1098 {
1099         guest_state_enter_irqoff();
1100         __kvm_riscv_switch_to(&vcpu->arch);
1101         vcpu->arch.last_exit_cpu = vcpu->cpu;
1102         guest_state_exit_irqoff();
1103 }
1104
1105 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
1106 {
1107         int ret;
1108         struct kvm_cpu_trap trap;
1109         struct kvm_run *run = vcpu->run;
1110
1111         /* Mark this VCPU ran at least once */
1112         vcpu->arch.ran_atleast_once = true;
1113
1114         kvm_vcpu_srcu_read_lock(vcpu);
1115
1116         switch (run->exit_reason) {
1117         case KVM_EXIT_MMIO:
1118                 /* Process MMIO value returned from user-space */
1119                 ret = kvm_riscv_vcpu_mmio_return(vcpu, vcpu->run);
1120                 break;
1121         case KVM_EXIT_RISCV_SBI:
1122                 /* Process SBI value returned from user-space */
1123                 ret = kvm_riscv_vcpu_sbi_return(vcpu, vcpu->run);
1124                 break;
1125         case KVM_EXIT_RISCV_CSR:
1126                 /* Process CSR value returned from user-space */
1127                 ret = kvm_riscv_vcpu_csr_return(vcpu, vcpu->run);
1128                 break;
1129         default:
1130                 ret = 0;
1131                 break;
1132         }
1133         if (ret) {
1134                 kvm_vcpu_srcu_read_unlock(vcpu);
1135                 return ret;
1136         }
1137
1138         if (run->immediate_exit) {
1139                 kvm_vcpu_srcu_read_unlock(vcpu);
1140                 return -EINTR;
1141         }
1142
1143         vcpu_load(vcpu);
1144
1145         kvm_sigset_activate(vcpu);
1146
1147         ret = 1;
1148         run->exit_reason = KVM_EXIT_UNKNOWN;
1149         while (ret > 0) {
1150                 /* Check conditions before entering the guest */
1151                 ret = xfer_to_guest_mode_handle_work(vcpu);
1152                 if (ret)
1153                         continue;
1154                 ret = 1;
1155
1156                 kvm_riscv_gstage_vmid_update(vcpu);
1157
1158                 kvm_riscv_check_vcpu_requests(vcpu);
1159
1160                 preempt_disable();
1161
1162                 /* Update AIA HW state before entering guest */
1163                 ret = kvm_riscv_vcpu_aia_update(vcpu);
1164                 if (ret <= 0) {
1165                         preempt_enable();
1166                         continue;
1167                 }
1168
1169                 local_irq_disable();
1170
1171                 /*
1172                  * Ensure we set mode to IN_GUEST_MODE after we disable
1173                  * interrupts and before the final VCPU requests check.
1174                  * See the comment in kvm_vcpu_exiting_guest_mode() and
1175                  * Documentation/virt/kvm/vcpu-requests.rst
1176                  */
1177                 vcpu->mode = IN_GUEST_MODE;
1178
1179                 kvm_vcpu_srcu_read_unlock(vcpu);
1180                 smp_mb__after_srcu_read_unlock();
1181
1182                 /*
1183                  * We might have got VCPU interrupts updated asynchronously
1184                  * so update it in HW.
1185                  */
1186                 kvm_riscv_vcpu_flush_interrupts(vcpu);
1187
1188                 /* Update HVIP CSR for current CPU */
1189                 kvm_riscv_update_hvip(vcpu);
1190
1191                 if (ret <= 0 ||
1192                     kvm_riscv_gstage_vmid_ver_changed(&vcpu->kvm->arch.vmid) ||
1193                     kvm_request_pending(vcpu) ||
1194                     xfer_to_guest_mode_work_pending()) {
1195                         vcpu->mode = OUTSIDE_GUEST_MODE;
1196                         local_irq_enable();
1197                         preempt_enable();
1198                         kvm_vcpu_srcu_read_lock(vcpu);
1199                         continue;
1200                 }
1201
1202                 /*
1203                  * Cleanup stale TLB enteries
1204                  *
1205                  * Note: This should be done after G-stage VMID has been
1206                  * updated using kvm_riscv_gstage_vmid_ver_changed()
1207                  */
1208                 kvm_riscv_local_tlb_sanitize(vcpu);
1209
1210                 guest_timing_enter_irqoff();
1211
1212                 kvm_riscv_vcpu_enter_exit(vcpu);
1213
1214                 vcpu->mode = OUTSIDE_GUEST_MODE;
1215                 vcpu->stat.exits++;
1216
1217                 /*
1218                  * Save SCAUSE, STVAL, HTVAL, and HTINST because we might
1219                  * get an interrupt between __kvm_riscv_switch_to() and
1220                  * local_irq_enable() which can potentially change CSRs.
1221                  */
1222                 trap.sepc = vcpu->arch.guest_context.sepc;
1223                 trap.scause = csr_read(CSR_SCAUSE);
1224                 trap.stval = csr_read(CSR_STVAL);
1225                 trap.htval = csr_read(CSR_HTVAL);
1226                 trap.htinst = csr_read(CSR_HTINST);
1227
1228                 /* Syncup interrupts state with HW */
1229                 kvm_riscv_vcpu_sync_interrupts(vcpu);
1230
1231                 /*
1232                  * We must ensure that any pending interrupts are taken before
1233                  * we exit guest timing so that timer ticks are accounted as
1234                  * guest time. Transiently unmask interrupts so that any
1235                  * pending interrupts are taken.
1236                  *
1237                  * There's no barrier which ensures that pending interrupts are
1238                  * recognised, so we just hope that the CPU takes any pending
1239                  * interrupts between the enable and disable.
1240                  */
1241                 local_irq_enable();
1242                 local_irq_disable();
1243
1244                 guest_timing_exit_irqoff();
1245
1246                 local_irq_enable();
1247
1248                 preempt_enable();
1249
1250                 kvm_vcpu_srcu_read_lock(vcpu);
1251
1252                 ret = kvm_riscv_vcpu_exit(vcpu, run, &trap);
1253         }
1254
1255         kvm_sigset_deactivate(vcpu);
1256
1257         vcpu_put(vcpu);
1258
1259         kvm_vcpu_srcu_read_unlock(vcpu);
1260
1261         return ret;
1262 }