arch/riscv/kernel/vector.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (C) 2023 SiFive
   4  * Author: Andy Chiu <andy.chiu@sifive.com>
   5  */
   6 #include <linux/export.h>
   7
   8 #include <asm/vector.h>
   9 #include <asm/csr.h>
  10 #include <asm/elf.h>
  11 #include <asm/bug.h>
  12
  13 unsigned long riscv_v_vsize __read_mostly;
  14 EXPORT_SYMBOL_GPL(riscv_v_vsize);
  15
  16 int riscv_v_setup_vsize(void)
  17 {
  18         unsigned long this_vsize;
  19
  20         /* There are 32 vector registers with vlenb length. */
  21         riscv_v_enable();
  22         this_vsize = csr_read(CSR_VLENB) * 32;
  23         riscv_v_disable();
  24
  25         if (!riscv_v_vsize) {
  26                 riscv_v_vsize = this_vsize;
  27                 return 0;
  28         }
  29
  30         if (riscv_v_vsize != this_vsize) {
  31                 WARN(1, "RISCV_ISA_V only supports one vlenb on SMP systems");
  32                 return -EOPNOTSUPP;
  33         }
  34
  35         return 0;
  36 }