1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2012 Regents of the University of California
6 #include <asm/asm-offsets.h>
8 #include <linux/init.h>
9 #include <linux/linkage.h>
10 #include <asm/thread_info.h>
12 #include <asm/pgtable.h>
14 #include <asm/hwcap.h>
15 #include <asm/image.h>
16 #include "efi-header.S"
18 #ifdef CONFIG_XIP_KERNEL
19 .macro XIP_FIXUP_OFFSET reg
23 _xip_fixup: .dword CONFIG_PHYS_RAM_BASE - CONFIG_XIP_PHYS_ADDR - XIP_OFFSET
25 .macro XIP_FIXUP_OFFSET reg
27 #endif /* CONFIG_XIP_KERNEL */
32 * Image header expected by Linux boot-loaders. The image header data
33 * structure is described in asm/image.h.
34 * Do not modify it without modifying the structure and all bootloaders
35 * that expects this header format!!
39 * This instruction decodes to "MZ" ASCII required by UEFI.
44 /* jump to start kernel */
50 #ifdef CONFIG_RISCV_M_MODE
51 /* Image load offset (0MB) from start of RAM for M-mode */
54 #if __riscv_xlen == 64
55 /* Image load offset(2MB) from start of RAM */
58 /* Image load offset(4MB) from start of RAM */
62 /* Effective size of kernel image */
65 .word RISCV_HEADER_VERSION
68 .ascii RISCV_IMAGE_MAGIC
70 .ascii RISCV_IMAGE_MAGIC2
72 .word pe_head_start - _start
82 .global relocate_enable_mmu
84 /* Relocate return address */
87 REG_L a1, KERNEL_MAP_VIRT_ADDR(a1)
92 /* Point stvec to virtual address of intruction after satp write */
97 /* Compute satp for kernel page tables, but don't load it yet */
98 srl a2, a0, PAGE_SHIFT
103 * Load trampoline page directory, which will cause us to trap to
104 * stvec if VA != PA, or simply fall through if VA == PA. We need a
105 * full fence here because setup_vm() just wrote these PTEs and we need
106 * to ensure the new translations are in use.
108 la a0, trampoline_pg_dir
110 srl a0, a0, PAGE_SHIFT
116 /* Set trap vector to spin forever to help debug */
117 la a0, .Lsecondary_park
120 /* Reload the global pointer */
123 la gp, __global_pointer$
127 * Switch to kernel page tables. A full fence is necessary in order to
128 * avoid using the trampoline translations, which are only correct for
129 * the first superpage. Fetching the fence is guarnteed to work
130 * because that first superpage is translated the same way.
136 #endif /* CONFIG_MMU */
138 .global secondary_start_sbi
140 /* Mask all interrupts */
144 /* Load the global pointer */
147 la gp, __global_pointer$
151 * Disable FPU to detect illegal usage of
152 * floating point in kernel space
157 /* Set trap vector to spin forever to help debug */
158 la a3, .Lsecondary_park
162 la a4, __cpu_up_stack_pointer
164 la a5, __cpu_up_task_pointer
171 .global secondary_start_common
172 secondary_start_common:
175 /* Enable virtual memory and relocate to virtual address */
176 la a0, swapper_pg_dir
178 call relocate_enable_mmu
180 call setup_trap_vector
182 #endif /* CONFIG_SMP */
186 /* Set trap vector to exception handler */
187 la a0, handle_exception
191 * Set sup0 scratch register to 0, indicating to exception vector that
192 * we are presently executing in kernel.
194 csrw CSR_SCRATCH, zero
199 /* We lack SMP support or have too many harts, so park this hart */
206 /* Mask all interrupts */
210 #ifdef CONFIG_RISCV_M_MODE
211 /* flush the instruction cache */
214 /* Reset all registers except ra, a0, a1 */
218 * Setup a PMP to permit access to all of memory. Some machines may
219 * not implement PMPs, so we set up a quick trap handler to just skip
220 * touching the PMPs on any trap.
226 csrw CSR_PMPADDR0, a0
227 li a0, (PMP_A_NAPOT | PMP_R | PMP_W | PMP_X)
233 * The hartid in a0 is expected later on, and we have no firmware
237 #endif /* CONFIG_RISCV_M_MODE */
239 /* Load the global pointer */
242 la gp, __global_pointer$
246 * Disable FPU to detect illegal usage of
247 * floating point in kernel space
253 li t0, CONFIG_NR_CPUS
254 blt a0, t0, .Lgood_cores
255 tail .Lsecondary_park
259 #ifndef CONFIG_XIP_KERNEL
260 /* Pick one hart to run the main boot sequence */
263 amoadd.w a3, a2, (a3)
264 bnez a3, .Lsecondary_start
267 /* hart_lottery in flash contains a magic number */
272 amoswap.w t0, t1, (a2)
273 /* first time here if hart_lottery in RAM is not set */
274 beq t0, t1, .Lsecondary_start
276 la sp, _end + THREAD_SIZE
281 /* Restore a0 copy */
285 #ifndef CONFIG_XIP_KERNEL
286 /* Clear BSS for flat non-ELF images */
289 ble a4, a3, clear_bss_done
292 add a3, a3, RISCV_SZPTR
293 blt a3, a4, clear_bss
296 /* Save hart ID and DTB physical address */
300 la a2, boot_cpu_hartid
304 /* Initialize page tables and relocate to virtual addresses */
305 la sp, init_thread_union + THREAD_SIZE
307 #ifdef CONFIG_BUILTIN_DTB
311 #endif /* CONFIG_BUILTIN_DTB */
316 call relocate_enable_mmu
317 #endif /* CONFIG_MMU */
319 call setup_trap_vector
320 /* Restore C environment */
322 sw zero, TASK_TI_CPU(tp)
323 la sp, init_thread_union + THREAD_SIZE
326 call kasan_early_init
328 /* Start the kernel */
334 /* Set trap vector to spin forever to help debug */
335 la a3, .Lsecondary_park
339 la a1, __cpu_up_stack_pointer
341 la a2, __cpu_up_task_pointer
347 * This hart didn't win the lottery, so we wait for the winning hart to
348 * get far enough along the boot process that it should continue.
351 /* FIXME: We should WFI to save some energy here. */
354 beqz sp, .Lwait_for_cpu_up
355 beqz tp, .Lwait_for_cpu_up
358 tail secondary_start_common
363 #ifdef CONFIG_RISCV_M_MODE
397 andi t0, t0, (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)
398 beqz t0, .Lreset_regs_done
435 /* note that the caller must clear SR_FS */
436 #endif /* CONFIG_FPU */
440 #endif /* CONFIG_RISCV_M_MODE */
443 /* Empty zero page */