1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2012 Regents of the University of California
4 * Copyright (C) 2017 SiFive
7 #include <linux/init.h>
8 #include <linux/linkage.h>
12 #include <asm/unistd.h>
13 #include <asm/thread_info.h>
14 #include <asm/asm-offsets.h>
15 #include <asm/errata_list.h>
17 #if !IS_ENABLED(CONFIG_PREEMPTION)
18 .set resume_kernel, restore_all
21 ENTRY(handle_exception)
23 * If coming from userspace, preserve the user thread pointer and load
24 * the kernel thread pointer. If we came from the kernel, the scratch
25 * register will contain 0, and we should continue on the current TP.
27 csrrw tp, CSR_SCRATCH, tp
28 bnez tp, _save_context
32 REG_S sp, TASK_TI_KERNEL_SP(tp)
34 #ifdef CONFIG_VMAP_STACK
35 addi sp, sp, -(PT_SIZE_ON_STACK)
36 srli sp, sp, THREAD_SHIFT
38 bnez sp, handle_kernel_stack_overflow
39 REG_L sp, TASK_TI_KERNEL_SP(tp)
43 REG_S sp, TASK_TI_USER_SP(tp)
44 REG_L sp, TASK_TI_KERNEL_SP(tp)
45 addi sp, sp, -(PT_SIZE_ON_STACK)
77 * Disable user-mode memory access as it should only be set in the
78 * actual user copy routines.
80 * Disable the FPU to detect illegal usage of floating point in kernel
85 REG_L s0, TASK_TI_USER_SP(tp)
86 csrrc s1, CSR_STATUS, t0
92 REG_S s1, PT_STATUS(sp)
94 REG_S s3, PT_BADADDR(sp)
95 REG_S s4, PT_CAUSE(sp)
99 * Set the scratch register to 0, so that if a recursive exception
100 * occurs, the exception vector knows it came from the kernel
104 /* Load the global pointer */
107 la gp, __global_pointer$
110 #ifdef CONFIG_TRACE_IRQFLAGS
111 call trace_hardirqs_off
114 #ifdef CONFIG_CONTEXT_TRACKING
115 /* If previous state is in user mode, call context_tracking_user_exit. */
118 bnez a0, skip_context_tracking
119 call context_tracking_user_exit
120 skip_context_tracking:
124 * MSB of cause differentiates between
125 * interrupts and exceptions
129 la ra, ret_from_exception
131 /* Handle interrupts */
132 move a0, sp /* pt_regs */
133 la a1, handle_arch_irq
138 * Exceptions run with interrupts enabled or disabled depending on the
139 * state of SR_PIE in m/sstatus.
143 /* kprobes, entered via ebreak, must have interrupts disabled. */
144 li t0, EXC_BREAKPOINT
146 #ifdef CONFIG_TRACE_IRQFLAGS
147 call trace_hardirqs_on
149 csrs CSR_STATUS, SR_IE
152 la ra, ret_from_exception
153 /* Handle syscalls */
155 beq s4, t0, handle_syscall
157 /* Handle other exceptions */
158 slli t0, s4, RISCV_LGPTR
159 la t1, excp_vect_table
160 la t2, excp_vect_table_end
161 move a0, sp /* pt_regs */
163 /* Check if exception code lies within bounds */
171 #ifdef CONFIG_RISCV_M_MODE
173 * When running is M-Mode (no MMU config), MPIE does not get set.
174 * As a result, we need to force enable interrupts here because
175 * handle_exception did not do set SR_IE as it always sees SR_PIE
178 csrs CSR_STATUS, SR_IE
180 #if defined(CONFIG_TRACE_IRQFLAGS) || defined(CONFIG_CONTEXT_TRACKING)
181 /* Recover a0 - a7 for system calls */
191 /* save the initial A0 value (needed in signal handlers) */
192 REG_S a0, PT_ORIG_A0(sp)
194 * Advance SEPC to avoid executing the original
195 * scall instruction on sret
199 /* Trace syscalls, but only if requested by the user. */
200 REG_L t0, TASK_TI_FLAGS(tp)
201 andi t0, t0, _TIF_SYSCALL_WORK
202 bnez t0, handle_syscall_trace_enter
204 /* Check to make sure we don't jump to a bogus syscall number. */
206 la s0, sys_ni_syscall
208 * Syscall number held in a7.
209 * If syscall number is above allowed value, redirect to ni_syscall.
213 la s0, sys_call_table
214 slli t0, a7, RISCV_LGPTR
221 /* Set user a0 to kernel a0 */
224 * We didn't execute the actual syscall.
225 * Seccomp already set return value for the current task pt_regs.
226 * (If it was configured with SECCOMP_RET_ERRNO/TRACE)
228 ret_from_syscall_rejected:
229 /* Trace syscalls, but only if requested by the user. */
230 REG_L t0, TASK_TI_FLAGS(tp)
231 andi t0, t0, _TIF_SYSCALL_WORK
232 bnez t0, handle_syscall_trace_exit
235 REG_L s0, PT_STATUS(sp)
236 csrc CSR_STATUS, SR_IE
237 #ifdef CONFIG_TRACE_IRQFLAGS
238 call trace_hardirqs_off
240 #ifdef CONFIG_RISCV_M_MODE
241 /* the MPP value is too large to be used as an immediate arg for addi */
247 bnez s0, resume_kernel
250 /* Interrupts must be disabled here so flags are checked atomically */
251 REG_L s0, TASK_TI_FLAGS(tp) /* current_thread_info->flags */
252 andi s1, s0, _TIF_WORK_MASK
253 bnez s1, work_pending
255 #ifdef CONFIG_CONTEXT_TRACKING
256 call context_tracking_user_enter
259 /* Save unwound kernel stack pointer in thread_info */
260 addi s0, sp, PT_SIZE_ON_STACK
261 REG_S s0, TASK_TI_KERNEL_SP(tp)
264 * Save TP into the scratch register , so we can find the kernel data
270 #ifdef CONFIG_TRACE_IRQFLAGS
271 REG_L s1, PT_STATUS(sp)
274 call trace_hardirqs_on
277 call trace_hardirqs_off
280 REG_L a0, PT_STATUS(sp)
282 * The current load reservation is effectively part of the processor's
283 * state, in the sense that load reservations cannot be shared between
284 * different hart contexts. We can't actually save and restore a load
285 * reservation, so instead here we clear any existing reservation --
286 * it's always legal for implementations to clear load reservations at
287 * any point (as long as the forward progress guarantee is kept, but
288 * we'll ignore that here).
290 * Dangling load reservations can be the result of taking a trap in the
291 * middle of an LR/SC sequence, but can also be the result of a taken
292 * forward branch around an SC -- which is how we implement CAS. As a
293 * result we need to clear reservations between the last CAS and the
294 * jump back to the new context. While it is unlikely the store
295 * completes, implementations are allowed to expand reservations to be
299 REG_SC x0, a2, PT_EPC(sp)
328 REG_L x26, PT_S10(sp)
329 REG_L x27, PT_S11(sp)
337 #ifdef CONFIG_RISCV_M_MODE
343 #if IS_ENABLED(CONFIG_PREEMPTION)
345 REG_L s0, TASK_TI_PREEMPT_COUNT(tp)
347 REG_L s0, TASK_TI_FLAGS(tp)
348 andi s0, s0, _TIF_NEED_RESCHED
350 call preempt_schedule_irq
355 /* Enter slow path for supplementary processing */
356 la ra, ret_from_exception
357 andi s1, s0, _TIF_NEED_RESCHED
358 bnez s1, work_resched
360 /* Handle pending signals and notify-resume requests */
361 csrs CSR_STATUS, SR_IE /* Enable interrupts for do_notify_resume() */
362 move a0, sp /* pt_regs */
363 move a1, s0 /* current_thread_info->flags */
364 tail do_notify_resume
368 /* Slow paths for ptrace. */
369 handle_syscall_trace_enter:
371 call do_syscall_trace_enter
381 bnez t0, ret_from_syscall_rejected
383 handle_syscall_trace_exit:
385 call do_syscall_trace_exit
388 #ifdef CONFIG_VMAP_STACK
389 handle_kernel_stack_overflow:
391 * Takes the psuedo-spinlock for the shadow stack, in case multiple
392 * harts are concurrently overflowing their kernel stacks. We could
393 * store any value here, but since we're overflowing the kernel stack
394 * already we only have SP to use as a scratch register. So we just
395 * swap in the address of the spinlock, as that's definately non-zero.
397 * Pairs with a store_release in handle_bad_stack().
399 1: la sp, spin_shadow_stack
400 REG_AMOSWAP_AQ sp, sp, (sp)
404 addi sp, sp, SHADOW_OVERFLOW_STACK_SIZE
406 //save caller register to shadow stack
407 addi sp, sp, -(PT_SIZE_ON_STACK)
425 la ra, restore_caller_reg
426 tail get_overflow_stack
429 //save per-cpu overflow stack
431 //restore caller register from shadow_stack
449 //load per-cpu overflow stack
451 addi sp, sp, -(PT_SIZE_ON_STACK)
453 //save context to overflow stack
477 REG_S x26, PT_S10(sp)
478 REG_S x27, PT_S11(sp)
484 REG_L s0, TASK_TI_KERNEL_SP(tp)
491 REG_S s1, PT_STATUS(sp)
493 REG_S s3, PT_BADADDR(sp)
494 REG_S s4, PT_CAUSE(sp)
497 tail handle_bad_stack
500 END(handle_exception)
503 la ra, ret_from_exception
505 ENDPROC(ret_from_fork)
507 ENTRY(ret_from_kernel_thread)
510 la ra, ret_from_exception
513 ENDPROC(ret_from_kernel_thread)
517 * Integer register context switch
518 * The callee-saved registers must be saved and restored.
520 * a0: previous task_struct (must be preserved across the switch)
521 * a1: next task_struct
523 * The value of a0 and a1 must be preserved by this function, as that's how
524 * arguments are passed to schedule_tail.
527 /* Save context into prev->thread */
528 li a4, TASK_THREAD_RA
531 REG_S ra, TASK_THREAD_RA_RA(a3)
532 REG_S sp, TASK_THREAD_SP_RA(a3)
533 REG_S s0, TASK_THREAD_S0_RA(a3)
534 REG_S s1, TASK_THREAD_S1_RA(a3)
535 REG_S s2, TASK_THREAD_S2_RA(a3)
536 REG_S s3, TASK_THREAD_S3_RA(a3)
537 REG_S s4, TASK_THREAD_S4_RA(a3)
538 REG_S s5, TASK_THREAD_S5_RA(a3)
539 REG_S s6, TASK_THREAD_S6_RA(a3)
540 REG_S s7, TASK_THREAD_S7_RA(a3)
541 REG_S s8, TASK_THREAD_S8_RA(a3)
542 REG_S s9, TASK_THREAD_S9_RA(a3)
543 REG_S s10, TASK_THREAD_S10_RA(a3)
544 REG_S s11, TASK_THREAD_S11_RA(a3)
545 /* Restore context from next->thread */
546 REG_L ra, TASK_THREAD_RA_RA(a4)
547 REG_L sp, TASK_THREAD_SP_RA(a4)
548 REG_L s0, TASK_THREAD_S0_RA(a4)
549 REG_L s1, TASK_THREAD_S1_RA(a4)
550 REG_L s2, TASK_THREAD_S2_RA(a4)
551 REG_L s3, TASK_THREAD_S3_RA(a4)
552 REG_L s4, TASK_THREAD_S4_RA(a4)
553 REG_L s5, TASK_THREAD_S5_RA(a4)
554 REG_L s6, TASK_THREAD_S6_RA(a4)
555 REG_L s7, TASK_THREAD_S7_RA(a4)
556 REG_L s8, TASK_THREAD_S8_RA(a4)
557 REG_L s9, TASK_THREAD_S9_RA(a4)
558 REG_L s10, TASK_THREAD_S10_RA(a4)
559 REG_L s11, TASK_THREAD_S11_RA(a4)
560 /* Swap the CPU entry around. */
561 lw a3, TASK_TI_CPU(a0)
562 lw a4, TASK_TI_CPU(a1)
563 sw a3, TASK_TI_CPU(a1)
564 sw a4, TASK_TI_CPU(a0)
565 /* The offset of thread_info in task_struct is zero. */
571 #define do_page_fault do_trap_unknown
576 /* Exception vector table */
577 ENTRY(excp_vect_table)
578 RISCV_PTR do_trap_insn_misaligned
579 ALT_INSN_FAULT(RISCV_PTR do_trap_insn_fault)
580 RISCV_PTR do_trap_insn_illegal
581 RISCV_PTR do_trap_break
582 RISCV_PTR do_trap_load_misaligned
583 RISCV_PTR do_trap_load_fault
584 RISCV_PTR do_trap_store_misaligned
585 RISCV_PTR do_trap_store_fault
586 RISCV_PTR do_trap_ecall_u /* system call, gets intercepted */
587 RISCV_PTR do_trap_ecall_s
588 RISCV_PTR do_trap_unknown
589 RISCV_PTR do_trap_ecall_m
590 /* instruciton page fault */
591 ALT_PAGE_FAULT(RISCV_PTR do_page_fault)
592 RISCV_PTR do_page_fault /* load page fault */
593 RISCV_PTR do_trap_unknown
594 RISCV_PTR do_page_fault /* store page fault */
599 ENTRY(__user_rt_sigreturn)
600 li a7, __NR_rt_sigreturn
602 END(__user_rt_sigreturn)