arch/riscv/kernel/cpufeature.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copied from arch/arm64/kernel/cpufeature.c
   4  *
   5  * Copyright (C) 2015 ARM Ltd.
   6  * Copyright (C) 2017 SiFive
   7  */
   8
   9 #include <linux/acpi.h>
  10 #include <linux/bitmap.h>
  11 #include <linux/ctype.h>
  12 #include <linux/log2.h>
  13 #include <linux/memory.h>
  14 #include <linux/module.h>
  15 #include <linux/of.h>
  16 #include <linux/of_device.h>
  17 #include <asm/acpi.h>
  18 #include <asm/alternative.h>
  19 #include <asm/cacheflush.h>
  20 #include <asm/cpufeature.h>
  21 #include <asm/hwcap.h>
  22 #include <asm/patch.h>
  23 #include <asm/processor.h>
  24 #include <asm/vector.h>
  25
  26 #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
  27
  28 unsigned long elf_hwcap __read_mostly;
  29
  30 /* Host ISA bitmap */
  31 static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
  32
  33 /* Per-cpu ISA extensions. */
  34 struct riscv_isainfo hart_isa[NR_CPUS];
  35
  36 /* Performance information */
  37 DEFINE_PER_CPU(long, misaligned_access_speed);
  38
  39 /**
  40  * riscv_isa_extension_base() - Get base extension word
  41  *
  42  * @isa_bitmap: ISA bitmap to use
  43  * Return: base extension word as unsigned long value
  44  *
  45  * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.
  46  */
  47 unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap)
  48 {
  49         if (!isa_bitmap)
  50                 return riscv_isa[0];
  51         return isa_bitmap[0];
  52 }
  53 EXPORT_SYMBOL_GPL(riscv_isa_extension_base);
  54
  55 /**
  56  * __riscv_isa_extension_available() - Check whether given extension
  57  * is available or not
  58  *
  59  * @isa_bitmap: ISA bitmap to use
  60  * @bit: bit position of the desired extension
  61  * Return: true or false
  62  *
  63  * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.
  64  */
  65 bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit)
  66 {
  67         const unsigned long *bmap = (isa_bitmap) ? isa_bitmap : riscv_isa;
  68
  69         if (bit >= RISCV_ISA_EXT_MAX)
  70                 return false;
  71
  72         return test_bit(bit, bmap) ? true : false;
  73 }
  74 EXPORT_SYMBOL_GPL(__riscv_isa_extension_available);
  75
  76 static bool riscv_isa_extension_check(int id)
  77 {
  78         switch (id) {
  79         case RISCV_ISA_EXT_ZICBOM:
  80                 if (!riscv_cbom_block_size) {
  81                         pr_err("Zicbom detected in ISA string, disabling as no cbom-block-size found\n");
  82                         return false;
  83                 } else if (!is_power_of_2(riscv_cbom_block_size)) {
  84                         pr_err("Zicbom disabled as cbom-block-size present, but is not a power-of-2\n");
  85                         return false;
  86                 }
  87                 return true;
  88         case RISCV_ISA_EXT_ZICBOZ:
  89                 if (!riscv_cboz_block_size) {
  90                         pr_err("Zicboz detected in ISA string, but no cboz-block-size found\n");
  91                         return false;
  92                 } else if (!is_power_of_2(riscv_cboz_block_size)) {
  93                         pr_err("cboz-block-size present, but is not a power-of-2\n");
  94                         return false;
  95                 }
  96                 return true;
  97         }
  98
  99         return true;
 100 }
 101
 102 void __init riscv_fill_hwcap(void)
 103 {
 104         struct device_node *node;
 105         const char *isa;
 106         char print_str[NUM_ALPHA_EXTS + 1];
 107         int i, j, rc;
 108         unsigned long isa2hwcap[26] = {0};
 109         struct acpi_table_header *rhct;
 110         acpi_status status;
 111         unsigned int cpu;
 112
 113         isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I;
 114         isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M;
 115         isa2hwcap['a' - 'a'] = COMPAT_HWCAP_ISA_A;
 116         isa2hwcap['f' - 'a'] = COMPAT_HWCAP_ISA_F;
 117         isa2hwcap['d' - 'a'] = COMPAT_HWCAP_ISA_D;
 118         isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C;
 119         isa2hwcap['v' - 'a'] = COMPAT_HWCAP_ISA_V;
 120
 121         elf_hwcap = 0;
 122
 123         bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX);
 124
 125         if (!acpi_disabled) {
 126                 status = acpi_get_table(ACPI_SIG_RHCT, 0, &rhct);
 127                 if (ACPI_FAILURE(status))
 128                         return;
 129         }
 130
 131         for_each_possible_cpu(cpu) {
 132                 struct riscv_isainfo *isainfo = &hart_isa[cpu];
 133                 unsigned long this_hwcap = 0;
 134                 const char *temp;
 135
 136                 if (acpi_disabled) {
 137                         node = of_cpu_device_node_get(cpu);
 138                         if (!node) {
 139                                 pr_warn("Unable to find cpu node\n");
 140                                 continue;
 141                         }
 142
 143                         rc = of_property_read_string(node, "riscv,isa", &isa);
 144                         of_node_put(node);
 145                         if (rc) {
 146                                 pr_warn("Unable to find \"riscv,isa\" devicetree entry\n");
 147                                 continue;
 148                         }
 149                 } else {
 150                         rc = acpi_get_riscv_isa(rhct, cpu, &isa);
 151                         if (rc < 0) {
 152                                 pr_warn("Unable to get ISA for the hart - %d\n", cpu);
 153                                 continue;
 154                         }
 155                 }
 156
 157                 temp = isa;
 158                 if (IS_ENABLED(CONFIG_32BIT) && !strncasecmp(isa, "rv32", 4))
 159                         isa += 4;
 160                 else if (IS_ENABLED(CONFIG_64BIT) && !strncasecmp(isa, "rv64", 4))
 161                         isa += 4;
 162                 /* The riscv,isa DT property must start with rv64 or rv32 */
 163                 if (temp == isa)
 164                         continue;
 165                 for (; *isa; ++isa) {
 166                         const char *ext = isa++;
 167                         const char *ext_end = isa;
 168                         bool ext_long = false, ext_err = false;
 169
 170                         switch (*ext) {
 171                         case 's':
 172                                 /**
 173                                  * Workaround for invalid single-letter 's' & 'u'(QEMU).
 174                                  * No need to set the bit in riscv_isa as 's' & 'u' are
 175                                  * not valid ISA extensions. It works until multi-letter
 176                                  * extension starting with "Su" appears.
 177                                  */
 178                                 if (ext[-1] != '_' && ext[1] == 'u') {
 179                                         ++isa;
 180                                         ext_err = true;
 181                                         break;
 182                                 }
 183                                 fallthrough;
 184                         case 'S':
 185                         case 'x':
 186                         case 'X':
 187                         case 'z':
 188                         case 'Z':
 189                                 ext_long = true;
 190                                 /* Multi-letter extension must be delimited */
 191                                 for (; *isa && *isa != '_'; ++isa)
 192                                         if (unlikely(!isalnum(*isa)))
 193                                                 ext_err = true;
 194                                 /* Parse backwards */
 195                                 ext_end = isa;
 196                                 if (unlikely(ext_err))
 197                                         break;
 198                                 if (!isdigit(ext_end[-1]))
 199                                         break;
 200                                 /* Skip the minor version */
 201                                 while (isdigit(*--ext_end))
 202                                         ;
 203                                 if (tolower(ext_end[0]) != 'p'
 204                                     || !isdigit(ext_end[-1])) {
 205                                         /* Advance it to offset the pre-decrement */
 206                                         ++ext_end;
 207                                         break;
 208                                 }
 209                                 /* Skip the major version */
 210                                 while (isdigit(*--ext_end))
 211                                         ;
 212                                 ++ext_end;
 213                                 break;
 214                         default:
 215                                 if (unlikely(!isalpha(*ext))) {
 216                                         ext_err = true;
 217                                         break;
 218                                 }
 219                                 /* Find next extension */
 220                                 if (!isdigit(*isa))
 221                                         break;
 222                                 /* Skip the minor version */
 223                                 while (isdigit(*++isa))
 224                                         ;
 225                                 if (tolower(*isa) != 'p')
 226                                         break;
 227                                 if (!isdigit(*++isa)) {
 228                                         --isa;
 229                                         break;
 230                                 }
 231                                 /* Skip the major version */
 232                                 while (isdigit(*++isa))
 233                                         ;
 234                                 break;
 235                         }
 236                         if (*isa != '_')
 237                                 --isa;
 238
 239 #define SET_ISA_EXT_MAP(name, bit)                                                      \
 240                         do {                                                            \
 241                                 if ((ext_end - ext == sizeof(name) - 1) &&              \
 242                                      !strncasecmp(ext, name, sizeof(name) - 1) &&       \
 243                                      riscv_isa_extension_check(bit))                    \
 244                                         set_bit(bit, isainfo->isa);                     \
 245                         } while (false)                                                 \
 246
 247                         if (unlikely(ext_err))
 248                                 continue;
 249                         if (!ext_long) {
 250                                 int nr = tolower(*ext) - 'a';
 251
 252                                 if (riscv_isa_extension_check(nr)) {
 253                                         this_hwcap |= isa2hwcap[nr];
 254                                         set_bit(nr, isainfo->isa);
 255                                 }
 256                         } else {
 257                                 /* sorted alphabetically */
 258                                 SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA);
 259                                 SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA);
 260                                 SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF);
 261                                 SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC);
 262                                 SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL);
 263                                 SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT);
 264                                 SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT);
 265                                 SET_ISA_EXT_MAP("zba", RISCV_ISA_EXT_ZBA);
 266                                 SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB);
 267                                 SET_ISA_EXT_MAP("zbs", RISCV_ISA_EXT_ZBS);
 268                                 SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM);
 269                                 SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ);
 270                                 SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE);
 271                         }
 272 #undef SET_ISA_EXT_MAP
 273                 }
 274
 275                 /*
 276                  * All "okay" hart should have same isa. Set HWCAP based on
 277                  * common capabilities of every "okay" hart, in case they don't
 278                  * have.
 279                  */
 280                 if (elf_hwcap)
 281                         elf_hwcap &= this_hwcap;
 282                 else
 283                         elf_hwcap = this_hwcap;
 284
 285                 if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX))
 286                         bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
 287                 else
 288                         bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
 289         }
 290
 291         if (!acpi_disabled && rhct)
 292                 acpi_put_table((struct acpi_table_header *)rhct);
 293
 294         /* We don't support systems with F but without D, so mask those out
 295          * here. */
 296         if ((elf_hwcap & COMPAT_HWCAP_ISA_F) && !(elf_hwcap & COMPAT_HWCAP_ISA_D)) {
 297                 pr_info("This kernel does not support systems with F but not D\n");
 298                 elf_hwcap &= ~COMPAT_HWCAP_ISA_F;
 299         }
 300
 301         if (elf_hwcap & COMPAT_HWCAP_ISA_V) {
 302                 riscv_v_setup_vsize();
 303                 /*
 304                  * ISA string in device tree might have 'v' flag, but
 305                  * CONFIG_RISCV_ISA_V is disabled in kernel.
 306                  * Clear V flag in elf_hwcap if CONFIG_RISCV_ISA_V is disabled.
 307                  */
 308                 if (!IS_ENABLED(CONFIG_RISCV_ISA_V))
 309                         elf_hwcap &= ~COMPAT_HWCAP_ISA_V;
 310         }
 311
 312         memset(print_str, 0, sizeof(print_str));
 313         for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
 314                 if (riscv_isa[0] & BIT_MASK(i))
 315                         print_str[j++] = (char)('a' + i);
 316         pr_info("riscv: base ISA extensions %s\n", print_str);
 317
 318         memset(print_str, 0, sizeof(print_str));
 319         for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
 320                 if (elf_hwcap & BIT_MASK(i))
 321                         print_str[j++] = (char)('a' + i);
 322         pr_info("riscv: ELF capabilities %s\n", print_str);
 323 }
 324
 325 unsigned long riscv_get_elf_hwcap(void)
 326 {
 327         unsigned long hwcap;
 328
 329         hwcap = (elf_hwcap & ((1UL << RISCV_ISA_EXT_BASE) - 1));
 330
 331         if (!riscv_v_vstate_ctrl_user_allowed())
 332                 hwcap &= ~COMPAT_HWCAP_ISA_V;
 333
 334         return hwcap;
 335 }
 336
 337 #ifdef CONFIG_RISCV_ALTERNATIVE
 338 /*
 339  * Alternative patch sites consider 48 bits when determining when to patch
 340  * the old instruction sequence with the new. These bits are broken into a
 341  * 16-bit vendor ID and a 32-bit patch ID. A non-zero vendor ID means the
 342  * patch site is for an erratum, identified by the 32-bit patch ID. When
 343  * the vendor ID is zero, the patch site is for a cpufeature. cpufeatures
 344  * further break down patch ID into two 16-bit numbers. The lower 16 bits
 345  * are the cpufeature ID and the upper 16 bits are used for a value specific
 346  * to the cpufeature and patch site. If the upper 16 bits are zero, then it
 347  * implies no specific value is specified. cpufeatures that want to control
 348  * patching on a per-site basis will provide non-zero values and implement
 349  * checks here. The checks return true when patching should be done, and
 350  * false otherwise.
 351  */
 352 static bool riscv_cpufeature_patch_check(u16 id, u16 value)
 353 {
 354         if (!value)
 355                 return true;
 356
 357         switch (id) {
 358         case RISCV_ISA_EXT_ZICBOZ:
 359                 /*
 360                  * Zicboz alternative applications provide the maximum
 361                  * supported block size order, or zero when it doesn't
 362                  * matter. If the current block size exceeds the maximum,
 363                  * then the alternative cannot be applied.
 364                  */
 365                 return riscv_cboz_block_size <= (1U << value);
 366         }
 367
 368         return false;
 369 }
 370
 371 void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin,
 372                                                   struct alt_entry *end,
 373                                                   unsigned int stage)
 374 {
 375         struct alt_entry *alt;
 376         void *oldptr, *altptr;
 377         u16 id, value;
 378
 379         if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
 380                 return;
 381
 382         for (alt = begin; alt < end; alt++) {
 383                 if (alt->vendor_id != 0)
 384                         continue;
 385
 386                 id = PATCH_ID_CPUFEATURE_ID(alt->patch_id);
 387
 388                 if (id >= RISCV_ISA_EXT_MAX) {
 389                         WARN(1, "This extension id:%d is not in ISA extension list", id);
 390                         continue;
 391                 }
 392
 393                 if (!__riscv_isa_extension_available(NULL, id))
 394                         continue;
 395
 396                 value = PATCH_ID_CPUFEATURE_VALUE(alt->patch_id);
 397                 if (!riscv_cpufeature_patch_check(id, value))
 398                         continue;
 399
 400                 oldptr = ALT_OLD_PTR(alt);
 401                 altptr = ALT_ALT_PTR(alt);
 402
 403                 mutex_lock(&text_mutex);
 404                 patch_text_nosync(oldptr, altptr, alt->alt_len);
 405                 riscv_alternative_fix_offsets(oldptr, alt->alt_len, oldptr - altptr);
 406                 mutex_unlock(&text_mutex);
 407         }
 408 }
 409 #endif