arch/riscv/kernel/cpufeature.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copied from arch/arm64/kernel/cpufeature.c
   4  *
   5  * Copyright (C) 2015 ARM Ltd.
   6  * Copyright (C) 2017 SiFive
   7  */
   8
   9 #include <linux/bitmap.h>
  10 #include <linux/ctype.h>
  11 #include <linux/log2.h>
  12 #include <linux/memory.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <asm/alternative.h>
  16 #include <asm/cacheflush.h>
  17 #include <asm/cpufeature.h>
  18 #include <asm/hwcap.h>
  19 #include <asm/patch.h>
  20 #include <asm/processor.h>
  21
  22 #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
  23
  24 unsigned long elf_hwcap __read_mostly;
  25
  26 /* Host ISA bitmap */
  27 static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
  28
  29 /* Per-cpu ISA extensions. */
  30 struct riscv_isainfo hart_isa[NR_CPUS];
  31
  32 /* Performance information */
  33 DEFINE_PER_CPU(long, misaligned_access_speed);
  34
  35 /**
  36  * riscv_isa_extension_base() - Get base extension word
  37  *
  38  * @isa_bitmap: ISA bitmap to use
  39  * Return: base extension word as unsigned long value
  40  *
  41  * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.
  42  */
  43 unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap)
  44 {
  45         if (!isa_bitmap)
  46                 return riscv_isa[0];
  47         return isa_bitmap[0];
  48 }
  49 EXPORT_SYMBOL_GPL(riscv_isa_extension_base);
  50
  51 /**
  52  * __riscv_isa_extension_available() - Check whether given extension
  53  * is available or not
  54  *
  55  * @isa_bitmap: ISA bitmap to use
  56  * @bit: bit position of the desired extension
  57  * Return: true or false
  58  *
  59  * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.
  60  */
  61 bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit)
  62 {
  63         const unsigned long *bmap = (isa_bitmap) ? isa_bitmap : riscv_isa;
  64
  65         if (bit >= RISCV_ISA_EXT_MAX)
  66                 return false;
  67
  68         return test_bit(bit, bmap) ? true : false;
  69 }
  70 EXPORT_SYMBOL_GPL(__riscv_isa_extension_available);
  71
  72 static bool riscv_isa_extension_check(int id)
  73 {
  74         switch (id) {
  75         case RISCV_ISA_EXT_ZICBOM:
  76                 if (!riscv_cbom_block_size) {
  77                         pr_err("Zicbom detected in ISA string, but no cbom-block-size found\n");
  78                         return false;
  79                 } else if (!is_power_of_2(riscv_cbom_block_size)) {
  80                         pr_err("cbom-block-size present, but is not a power-of-2\n");
  81                         return false;
  82                 }
  83                 return true;
  84         case RISCV_ISA_EXT_ZICBOZ:
  85                 if (!riscv_cboz_block_size) {
  86                         pr_err("Zicboz detected in ISA string, but no cboz-block-size found\n");
  87                         return false;
  88                 } else if (!is_power_of_2(riscv_cboz_block_size)) {
  89                         pr_err("cboz-block-size present, but is not a power-of-2\n");
  90                         return false;
  91                 }
  92                 return true;
  93         }
  94
  95         return true;
  96 }
  97
  98 void __init riscv_fill_hwcap(void)
  99 {
 100         struct device_node *node;
 101         const char *isa;
 102         char print_str[NUM_ALPHA_EXTS + 1];
 103         int i, j, rc;
 104         unsigned long isa2hwcap[26] = {0};
 105         unsigned long hartid;
 106
 107         isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I;
 108         isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M;
 109         isa2hwcap['a' - 'a'] = COMPAT_HWCAP_ISA_A;
 110         isa2hwcap['f' - 'a'] = COMPAT_HWCAP_ISA_F;
 111         isa2hwcap['d' - 'a'] = COMPAT_HWCAP_ISA_D;
 112         isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C;
 113
 114         elf_hwcap = 0;
 115
 116         bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX);
 117
 118         for_each_of_cpu_node(node) {
 119                 struct riscv_isainfo *isainfo;
 120                 unsigned long this_hwcap = 0;
 121                 const char *temp;
 122                 unsigned int cpu_id;
 123
 124                 rc = riscv_of_processor_hartid(node, &hartid);
 125                 if (rc < 0)
 126                         continue;
 127
 128                 cpu_id = riscv_hartid_to_cpuid(hartid);
 129                 isainfo = &hart_isa[cpu_id];
 130
 131                 if (of_property_read_string(node, "riscv,isa", &isa)) {
 132                         pr_warn("Unable to find \"riscv,isa\" devicetree entry\n");
 133                         continue;
 134                 }
 135
 136                 temp = isa;
 137 #if IS_ENABLED(CONFIG_32BIT)
 138                 if (!strncmp(isa, "rv32", 4))
 139                         isa += 4;
 140 #elif IS_ENABLED(CONFIG_64BIT)
 141                 if (!strncmp(isa, "rv64", 4))
 142                         isa += 4;
 143 #endif
 144                 /* The riscv,isa DT property must start with rv64 or rv32 */
 145                 if (temp == isa)
 146                         continue;
 147                 for (; *isa; ++isa) {
 148                         const char *ext = isa++;
 149                         const char *ext_end = isa;
 150                         bool ext_long = false, ext_err = false;
 151
 152                         switch (*ext) {
 153                         case 's':
 154                                 /**
 155                                  * Workaround for invalid single-letter 's' & 'u'(QEMU).
 156                                  * No need to set the bit in riscv_isa as 's' & 'u' are
 157                                  * not valid ISA extensions. It works until multi-letter
 158                                  * extension starting with "Su" appears.
 159                                  */
 160                                 if (ext[-1] != '_' && ext[1] == 'u') {
 161                                         ++isa;
 162                                         ext_err = true;
 163                                         break;
 164                                 }
 165                                 fallthrough;
 166                         case 'x':
 167                         case 'z':
 168                                 ext_long = true;
 169                                 /* Multi-letter extension must be delimited */
 170                                 for (; *isa && *isa != '_'; ++isa)
 171                                         if (unlikely(!islower(*isa)
 172                                                      && !isdigit(*isa)))
 173                                                 ext_err = true;
 174                                 /* Parse backwards */
 175                                 ext_end = isa;
 176                                 if (unlikely(ext_err))
 177                                         break;
 178                                 if (!isdigit(ext_end[-1]))
 179                                         break;
 180                                 /* Skip the minor version */
 181                                 while (isdigit(*--ext_end))
 182                                         ;
 183                                 if (ext_end[0] != 'p'
 184                                     || !isdigit(ext_end[-1])) {
 185                                         /* Advance it to offset the pre-decrement */
 186                                         ++ext_end;
 187                                         break;
 188                                 }
 189                                 /* Skip the major version */
 190                                 while (isdigit(*--ext_end))
 191                                         ;
 192                                 ++ext_end;
 193                                 break;
 194                         default:
 195                                 if (unlikely(!islower(*ext))) {
 196                                         ext_err = true;
 197                                         break;
 198                                 }
 199                                 /* Find next extension */
 200                                 if (!isdigit(*isa))
 201                                         break;
 202                                 /* Skip the minor version */
 203                                 while (isdigit(*++isa))
 204                                         ;
 205                                 if (*isa != 'p')
 206                                         break;
 207                                 if (!isdigit(*++isa)) {
 208                                         --isa;
 209                                         break;
 210                                 }
 211                                 /* Skip the major version */
 212                                 while (isdigit(*++isa))
 213                                         ;
 214                                 break;
 215                         }
 216                         if (*isa != '_')
 217                                 --isa;
 218
 219 #define SET_ISA_EXT_MAP(name, bit)                                              \
 220                         do {                                                    \
 221                                 if ((ext_end - ext == sizeof(name) - 1) &&      \
 222                                      !memcmp(ext, name, sizeof(name) - 1) &&    \
 223                                      riscv_isa_extension_check(bit))            \
 224                                         set_bit(bit, isainfo->isa);             \
 225                         } while (false)                                         \
 226
 227                         if (unlikely(ext_err))
 228                                 continue;
 229                         if (!ext_long) {
 230                                 int nr = *ext - 'a';
 231
 232                                 if (riscv_isa_extension_check(nr)) {
 233                                         this_hwcap |= isa2hwcap[nr];
 234                                         set_bit(nr, isainfo->isa);
 235                                 }
 236                         } else {
 237                                 /* sorted alphabetically */
 238                                 SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA);
 239                                 SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA);
 240                                 SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF);
 241                                 SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC);
 242                                 SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL);
 243                                 SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT);
 244                                 SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT);
 245                                 SET_ISA_EXT_MAP("zba", RISCV_ISA_EXT_ZBA);
 246                                 SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB);
 247                                 SET_ISA_EXT_MAP("zbs", RISCV_ISA_EXT_ZBS);
 248                                 SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM);
 249                                 SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ);
 250                                 SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE);
 251                         }
 252 #undef SET_ISA_EXT_MAP
 253                 }
 254
 255                 /*
 256                  * All "okay" hart should have same isa. Set HWCAP based on
 257                  * common capabilities of every "okay" hart, in case they don't
 258                  * have.
 259                  */
 260                 if (elf_hwcap)
 261                         elf_hwcap &= this_hwcap;
 262                 else
 263                         elf_hwcap = this_hwcap;
 264
 265                 if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX))
 266                         bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
 267                 else
 268                         bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
 269         }
 270
 271         /* We don't support systems with F but without D, so mask those out
 272          * here. */
 273         if ((elf_hwcap & COMPAT_HWCAP_ISA_F) && !(elf_hwcap & COMPAT_HWCAP_ISA_D)) {
 274                 pr_info("This kernel does not support systems with F but not D\n");
 275                 elf_hwcap &= ~COMPAT_HWCAP_ISA_F;
 276         }
 277
 278         memset(print_str, 0, sizeof(print_str));
 279         for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
 280                 if (riscv_isa[0] & BIT_MASK(i))
 281                         print_str[j++] = (char)('a' + i);
 282         pr_info("riscv: base ISA extensions %s\n", print_str);
 283
 284         memset(print_str, 0, sizeof(print_str));
 285         for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
 286                 if (elf_hwcap & BIT_MASK(i))
 287                         print_str[j++] = (char)('a' + i);
 288         pr_info("riscv: ELF capabilities %s\n", print_str);
 289 }
 290
 291 #ifdef CONFIG_RISCV_ALTERNATIVE
 292 /*
 293  * Alternative patch sites consider 48 bits when determining when to patch
 294  * the old instruction sequence with the new. These bits are broken into a
 295  * 16-bit vendor ID and a 32-bit patch ID. A non-zero vendor ID means the
 296  * patch site is for an erratum, identified by the 32-bit patch ID. When
 297  * the vendor ID is zero, the patch site is for a cpufeature. cpufeatures
 298  * further break down patch ID into two 16-bit numbers. The lower 16 bits
 299  * are the cpufeature ID and the upper 16 bits are used for a value specific
 300  * to the cpufeature and patch site. If the upper 16 bits are zero, then it
 301  * implies no specific value is specified. cpufeatures that want to control
 302  * patching on a per-site basis will provide non-zero values and implement
 303  * checks here. The checks return true when patching should be done, and
 304  * false otherwise.
 305  */
 306 static bool riscv_cpufeature_patch_check(u16 id, u16 value)
 307 {
 308         if (!value)
 309                 return true;
 310
 311         switch (id) {
 312         case RISCV_ISA_EXT_ZICBOZ:
 313                 /*
 314                  * Zicboz alternative applications provide the maximum
 315                  * supported block size order, or zero when it doesn't
 316                  * matter. If the current block size exceeds the maximum,
 317                  * then the alternative cannot be applied.
 318                  */
 319                 return riscv_cboz_block_size <= (1U << value);
 320         }
 321
 322         return false;
 323 }
 324
 325 void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin,
 326                                                   struct alt_entry *end,
 327                                                   unsigned int stage)
 328 {
 329         struct alt_entry *alt;
 330         void *oldptr, *altptr;
 331         u16 id, value;
 332
 333         if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
 334                 return;
 335
 336         for (alt = begin; alt < end; alt++) {
 337                 if (alt->vendor_id != 0)
 338                         continue;
 339
 340                 id = PATCH_ID_CPUFEATURE_ID(alt->patch_id);
 341
 342                 if (id >= RISCV_ISA_EXT_MAX) {
 343                         WARN(1, "This extension id:%d is not in ISA extension list", id);
 344                         continue;
 345                 }
 346
 347                 if (!__riscv_isa_extension_available(NULL, id))
 348                         continue;
 349
 350                 value = PATCH_ID_CPUFEATURE_VALUE(alt->patch_id);
 351                 if (!riscv_cpufeature_patch_check(id, value))
 352                         continue;
 353
 354                 oldptr = ALT_OLD_PTR(alt);
 355                 altptr = ALT_ALT_PTR(alt);
 356
 357                 mutex_lock(&text_mutex);
 358                 patch_text_nosync(oldptr, altptr, alt->alt_len);
 359                 riscv_alternative_fix_offsets(oldptr, alt->alt_len, oldptr - altptr);
 360                 mutex_unlock(&text_mutex);
 361         }
 362 }
 363 #endif