arch/riscv/kernel/cpufeature.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copied from arch/arm64/kernel/cpufeature.c
   4  *
   5  * Copyright (C) 2015 ARM Ltd.
   6  * Copyright (C) 2017 SiFive
   7  */
   8
   9 #include <linux/acpi.h>
  10 #include <linux/bitmap.h>
  11 #include <linux/ctype.h>
  12 #include <linux/log2.h>
  13 #include <linux/memory.h>
  14 #include <linux/module.h>
  15 #include <linux/of.h>
  16 #include <linux/of_device.h>
  17 #include <asm/acpi.h>
  18 #include <asm/alternative.h>
  19 #include <asm/cacheflush.h>
  20 #include <asm/cpufeature.h>
  21 #include <asm/hwcap.h>
  22 #include <asm/patch.h>
  23 #include <asm/processor.h>
  24
  25 #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
  26
  27 unsigned long elf_hwcap __read_mostly;
  28
  29 /* Host ISA bitmap */
  30 static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
  31
  32 /* Performance information */
  33 DEFINE_PER_CPU(long, misaligned_access_speed);
  34
  35 /**
  36  * riscv_isa_extension_base() - Get base extension word
  37  *
  38  * @isa_bitmap: ISA bitmap to use
  39  * Return: base extension word as unsigned long value
  40  *
  41  * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.
  42  */
  43 unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap)
  44 {
  45         if (!isa_bitmap)
  46                 return riscv_isa[0];
  47         return isa_bitmap[0];
  48 }
  49 EXPORT_SYMBOL_GPL(riscv_isa_extension_base);
  50
  51 /**
  52  * __riscv_isa_extension_available() - Check whether given extension
  53  * is available or not
  54  *
  55  * @isa_bitmap: ISA bitmap to use
  56  * @bit: bit position of the desired extension
  57  * Return: true or false
  58  *
  59  * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.
  60  */
  61 bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit)
  62 {
  63         const unsigned long *bmap = (isa_bitmap) ? isa_bitmap : riscv_isa;
  64
  65         if (bit >= RISCV_ISA_EXT_MAX)
  66                 return false;
  67
  68         return test_bit(bit, bmap) ? true : false;
  69 }
  70 EXPORT_SYMBOL_GPL(__riscv_isa_extension_available);
  71
  72 static bool riscv_isa_extension_check(int id)
  73 {
  74         switch (id) {
  75         case RISCV_ISA_EXT_ZICBOM:
  76                 if (!riscv_cbom_block_size) {
  77                         pr_err("Zicbom detected in ISA string, but no cbom-block-size found\n");
  78                         return false;
  79                 } else if (!is_power_of_2(riscv_cbom_block_size)) {
  80                         pr_err("cbom-block-size present, but is not a power-of-2\n");
  81                         return false;
  82                 }
  83                 return true;
  84         case RISCV_ISA_EXT_ZICBOZ:
  85                 if (!riscv_cboz_block_size) {
  86                         pr_err("Zicboz detected in ISA string, but no cboz-block-size found\n");
  87                         return false;
  88                 } else if (!is_power_of_2(riscv_cboz_block_size)) {
  89                         pr_err("cboz-block-size present, but is not a power-of-2\n");
  90                         return false;
  91                 }
  92                 return true;
  93         }
  94
  95         return true;
  96 }
  97
  98 void __init riscv_fill_hwcap(void)
  99 {
 100         struct device_node *node;
 101         const char *isa;
 102         char print_str[NUM_ALPHA_EXTS + 1];
 103         int i, j, rc;
 104         unsigned long isa2hwcap[26] = {0};
 105         struct acpi_table_header *rhct;
 106         acpi_status status;
 107         unsigned int cpu;
 108
 109         isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I;
 110         isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M;
 111         isa2hwcap['a' - 'a'] = COMPAT_HWCAP_ISA_A;
 112         isa2hwcap['f' - 'a'] = COMPAT_HWCAP_ISA_F;
 113         isa2hwcap['d' - 'a'] = COMPAT_HWCAP_ISA_D;
 114         isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C;
 115
 116         elf_hwcap = 0;
 117
 118         bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX);
 119
 120         if (!acpi_disabled) {
 121                 status = acpi_get_table(ACPI_SIG_RHCT, 0, &rhct);
 122                 if (ACPI_FAILURE(status))
 123                         return;
 124         }
 125
 126         for_each_possible_cpu(cpu) {
 127                 unsigned long this_hwcap = 0;
 128                 DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX);
 129
 130                 if (acpi_disabled) {
 131                         node = of_cpu_device_node_get(cpu);
 132                         if (!node) {
 133                                 pr_warn("Unable to find cpu node\n");
 134                                 continue;
 135                         }
 136
 137                         rc = of_property_read_string(node, "riscv,isa", &isa);
 138                         of_node_put(node);
 139                         if (rc) {
 140                                 pr_warn("Unable to find \"riscv,isa\" devicetree entry\n");
 141                                 continue;
 142                         }
 143                 } else {
 144                         rc = acpi_get_riscv_isa(rhct, cpu, &isa);
 145                         if (rc < 0) {
 146                                 pr_warn("Unable to get ISA for the hart - %d\n", cpu);
 147                                 continue;
 148                         }
 149                 }
 150
 151                 /*
 152                  * For all possible cpus, we have already validated in
 153                  * the boot process that they at least contain "rv" and
 154                  * whichever of "32"/"64" this kernel supports, and so this
 155                  * section can be skipped.
 156                  */
 157                 isa += 4;
 158
 159                 bitmap_zero(this_isa, RISCV_ISA_EXT_MAX);
 160                 while (*isa) {
 161                         const char *ext = isa++;
 162                         const char *ext_end = isa;
 163                         bool ext_long = false, ext_err = false;
 164
 165                         switch (*ext) {
 166                         case 's':
 167                                 /*
 168                                  * Workaround for invalid single-letter 's' & 'u'(QEMU).
 169                                  * No need to set the bit in riscv_isa as 's' & 'u' are
 170                                  * not valid ISA extensions. It works until multi-letter
 171                                  * extension starting with "Su" appears.
 172                                  */
 173                                 if (ext[-1] != '_' && ext[1] == 'u') {
 174                                         ++isa;
 175                                         ext_err = true;
 176                                         break;
 177                                 }
 178                                 fallthrough;
 179                         case 'S':
 180                         case 'x':
 181                         case 'X':
 182                         case 'z':
 183                         case 'Z':
 184                                 /*
 185                                  * Before attempting to parse the extension itself, we find its end.
 186                                  * As multi-letter extensions must be split from other multi-letter
 187                                  * extensions with an "_", the end of a multi-letter extension will
 188                                  * either be the null character or the "_" at the start of the next
 189                                  * multi-letter extension.
 190                                  *
 191                                  * Next, as the extensions version is currently ignored, we
 192                                  * eliminate that portion. This is done by parsing backwards from
 193                                  * the end of the extension, removing any numbers. This may be a
 194                                  * major or minor number however, so the process is repeated if a
 195                                  * minor number was found.
 196                                  *
 197                                  * ext_end is intended to represent the first character *after* the
 198                                  * name portion of an extension, but will be decremented to the last
 199                                  * character itself while eliminating the extensions version number.
 200                                  * A simple re-increment solves this problem.
 201                                  */
 202                                 ext_long = true;
 203                                 for (; *isa && *isa != '_'; ++isa)
 204                                         if (unlikely(!isalnum(*isa)))
 205                                                 ext_err = true;
 206
 207                                 ext_end = isa;
 208                                 if (unlikely(ext_err))
 209                                         break;
 210
 211                                 if (!isdigit(ext_end[-1]))
 212                                         break;
 213
 214                                 while (isdigit(*--ext_end))
 215                                         ;
 216
 217                                 if (tolower(ext_end[0]) != 'p' || !isdigit(ext_end[-1])) {
 218                                         ++ext_end;
 219                                         break;
 220                                 }
 221
 222                                 while (isdigit(*--ext_end))
 223                                         ;
 224
 225                                 ++ext_end;
 226                                 break;
 227                         default:
 228                                 /*
 229                                  * Things are a little easier for single-letter extensions, as they
 230                                  * are parsed forwards.
 231                                  *
 232                                  * After checking that our starting position is valid, we need to
 233                                  * ensure that, when isa was incremented at the start of the loop,
 234                                  * that it arrived at the start of the next extension.
 235                                  *
 236                                  * If we are already on a non-digit, there is nothing to do. Either
 237                                  * we have a multi-letter extension's _, or the start of an
 238                                  * extension.
 239                                  *
 240                                  * Otherwise we have found the current extension's major version
 241                                  * number. Parse past it, and a subsequent p/minor version number
 242                                  * if present. The `p` extension must not appear immediately after
 243                                  * a number, so there is no fear of missing it.
 244                                  *
 245                                  */
 246                                 if (unlikely(!isalpha(*ext))) {
 247                                         ext_err = true;
 248                                         break;
 249                                 }
 250
 251                                 if (!isdigit(*isa))
 252                                         break;
 253
 254                                 while (isdigit(*++isa))
 255                                         ;
 256
 257                                 if (tolower(*isa) != 'p')
 258                                         break;
 259
 260                                 if (!isdigit(*++isa)) {
 261                                         --isa;
 262                                         break;
 263                                 }
 264
 265                                 while (isdigit(*++isa))
 266                                         ;
 267
 268                                 break;
 269                         }
 270
 271                         /*
 272                          * The parser expects that at the start of an iteration isa points to the
 273                          * first character of the next extension. As we stop parsing an extension
 274                          * on meeting a non-alphanumeric character, an extra increment is needed
 275                          * where the succeeding extension is a multi-letter prefixed with an "_".
 276                          */
 277                         if (*isa == '_')
 278                                 ++isa;
 279
 280 #define SET_ISA_EXT_MAP(name, bit)                                                      \
 281                         do {                                                            \
 282                                 if ((ext_end - ext == sizeof(name) - 1) &&              \
 283                                      !strncasecmp(ext, name, sizeof(name) - 1) &&       \
 284                                      riscv_isa_extension_check(bit))                    \
 285                                         set_bit(bit, this_isa);                         \
 286                         } while (false)                                                 \
 287
 288                         if (unlikely(ext_err))
 289                                 continue;
 290                         if (!ext_long) {
 291                                 int nr = tolower(*ext) - 'a';
 292
 293                                 if (riscv_isa_extension_check(nr)) {
 294                                         this_hwcap |= isa2hwcap[nr];
 295                                         set_bit(nr, this_isa);
 296                                 }
 297                         } else {
 298                                 /* sorted alphabetically */
 299                                 SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA);
 300                                 SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA);
 301                                 SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF);
 302                                 SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC);
 303                                 SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL);
 304                                 SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT);
 305                                 SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT);
 306                                 SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB);
 307                                 SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM);
 308                                 SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ);
 309                                 SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE);
 310                         }
 311 #undef SET_ISA_EXT_MAP
 312                 }
 313
 314                 /*
 315                  * Linux requires the following extensions, so we may as well
 316                  * always set them.
 317                  */
 318                 set_bit(RISCV_ISA_EXT_ZICSR, this_isa);
 319                 set_bit(RISCV_ISA_EXT_ZIFENCEI, this_isa);
 320
 321                 /*
 322                  * These ones were as they were part of the base ISA when the
 323                  * port & dt-bindings were upstreamed, and so can be set
 324                  * unconditionally where `i` is in riscv,isa on DT systems.
 325                  */
 326                 if (acpi_disabled) {
 327                         set_bit(RISCV_ISA_EXT_ZICNTR, this_isa);
 328                         set_bit(RISCV_ISA_EXT_ZIHPM, this_isa);
 329                 }
 330
 331                 /*
 332                  * All "okay" hart should have same isa. Set HWCAP based on
 333                  * common capabilities of every "okay" hart, in case they don't
 334                  * have.
 335                  */
 336                 if (elf_hwcap)
 337                         elf_hwcap &= this_hwcap;
 338                 else
 339                         elf_hwcap = this_hwcap;
 340
 341                 if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX))
 342                         bitmap_copy(riscv_isa, this_isa, RISCV_ISA_EXT_MAX);
 343                 else
 344                         bitmap_and(riscv_isa, riscv_isa, this_isa, RISCV_ISA_EXT_MAX);
 345         }
 346
 347         if (!acpi_disabled && rhct)
 348                 acpi_put_table((struct acpi_table_header *)rhct);
 349
 350         /* We don't support systems with F but without D, so mask those out
 351          * here. */
 352         if ((elf_hwcap & COMPAT_HWCAP_ISA_F) && !(elf_hwcap & COMPAT_HWCAP_ISA_D)) {
 353                 pr_info("This kernel does not support systems with F but not D\n");
 354                 elf_hwcap &= ~COMPAT_HWCAP_ISA_F;
 355         }
 356
 357         memset(print_str, 0, sizeof(print_str));
 358         for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
 359                 if (riscv_isa[0] & BIT_MASK(i))
 360                         print_str[j++] = (char)('a' + i);
 361         pr_info("riscv: base ISA extensions %s\n", print_str);
 362
 363         memset(print_str, 0, sizeof(print_str));
 364         for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
 365                 if (elf_hwcap & BIT_MASK(i))
 366                         print_str[j++] = (char)('a' + i);
 367         pr_info("riscv: ELF capabilities %s\n", print_str);
 368 }
 369
 370 #ifdef CONFIG_RISCV_ALTERNATIVE
 371 /*
 372  * Alternative patch sites consider 48 bits when determining when to patch
 373  * the old instruction sequence with the new. These bits are broken into a
 374  * 16-bit vendor ID and a 32-bit patch ID. A non-zero vendor ID means the
 375  * patch site is for an erratum, identified by the 32-bit patch ID. When
 376  * the vendor ID is zero, the patch site is for a cpufeature. cpufeatures
 377  * further break down patch ID into two 16-bit numbers. The lower 16 bits
 378  * are the cpufeature ID and the upper 16 bits are used for a value specific
 379  * to the cpufeature and patch site. If the upper 16 bits are zero, then it
 380  * implies no specific value is specified. cpufeatures that want to control
 381  * patching on a per-site basis will provide non-zero values and implement
 382  * checks here. The checks return true when patching should be done, and
 383  * false otherwise.
 384  */
 385 static bool riscv_cpufeature_patch_check(u16 id, u16 value)
 386 {
 387         if (!value)
 388                 return true;
 389
 390         switch (id) {
 391         case RISCV_ISA_EXT_ZICBOZ:
 392                 /*
 393                  * Zicboz alternative applications provide the maximum
 394                  * supported block size order, or zero when it doesn't
 395                  * matter. If the current block size exceeds the maximum,
 396                  * then the alternative cannot be applied.
 397                  */
 398                 return riscv_cboz_block_size <= (1U << value);
 399         }
 400
 401         return false;
 402 }
 403
 404 void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin,
 405                                                   struct alt_entry *end,
 406                                                   unsigned int stage)
 407 {
 408         struct alt_entry *alt;
 409         void *oldptr, *altptr;
 410         u16 id, value;
 411
 412         if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
 413                 return;
 414
 415         for (alt = begin; alt < end; alt++) {
 416                 if (alt->vendor_id != 0)
 417                         continue;
 418
 419                 id = PATCH_ID_CPUFEATURE_ID(alt->patch_id);
 420
 421                 if (id >= RISCV_ISA_EXT_MAX) {
 422                         WARN(1, "This extension id:%d is not in ISA extension list", id);
 423                         continue;
 424                 }
 425
 426                 if (!__riscv_isa_extension_available(NULL, id))
 427                         continue;
 428
 429                 value = PATCH_ID_CPUFEATURE_VALUE(alt->patch_id);
 430                 if (!riscv_cpufeature_patch_check(id, value))
 431                         continue;
 432
 433                 oldptr = ALT_OLD_PTR(alt);
 434                 altptr = ALT_ALT_PTR(alt);
 435
 436                 mutex_lock(&text_mutex);
 437                 patch_text_nosync(oldptr, altptr, alt->alt_len);
 438                 riscv_alternative_fix_offsets(oldptr, alt->alt_len, oldptr - altptr);
 439                 mutex_unlock(&text_mutex);
 440         }
 441 }
 442 #endif