arch/riscv/kernel/cpufeature.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copied from arch/arm64/kernel/cpufeature.c
   4  *
   5  * Copyright (C) 2015 ARM Ltd.
   6  * Copyright (C) 2017 SiFive
   7  */
   8
   9 #include <linux/bitmap.h>
  10 #include <linux/ctype.h>
  11 #include <linux/log2.h>
  12 #include <linux/memory.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <asm/alternative.h>
  16 #include <asm/cacheflush.h>
  17 #include <asm/cpufeature.h>
  18 #include <asm/hwcap.h>
  19 #include <asm/patch.h>
  20 #include <asm/processor.h>
  21
  22 #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
  23
  24 unsigned long elf_hwcap __read_mostly;
  25
  26 /* Host ISA bitmap */
  27 static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
  28
  29 /* Performance information */
  30 DEFINE_PER_CPU(long, misaligned_access_speed);
  31
  32 /**
  33  * riscv_isa_extension_base() - Get base extension word
  34  *
  35  * @isa_bitmap: ISA bitmap to use
  36  * Return: base extension word as unsigned long value
  37  *
  38  * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.
  39  */
  40 unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap)
  41 {
  42         if (!isa_bitmap)
  43                 return riscv_isa[0];
  44         return isa_bitmap[0];
  45 }
  46 EXPORT_SYMBOL_GPL(riscv_isa_extension_base);
  47
  48 /**
  49  * __riscv_isa_extension_available() - Check whether given extension
  50  * is available or not
  51  *
  52  * @isa_bitmap: ISA bitmap to use
  53  * @bit: bit position of the desired extension
  54  * Return: true or false
  55  *
  56  * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.
  57  */
  58 bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit)
  59 {
  60         const unsigned long *bmap = (isa_bitmap) ? isa_bitmap : riscv_isa;
  61
  62         if (bit >= RISCV_ISA_EXT_MAX)
  63                 return false;
  64
  65         return test_bit(bit, bmap) ? true : false;
  66 }
  67 EXPORT_SYMBOL_GPL(__riscv_isa_extension_available);
  68
  69 static bool riscv_isa_extension_check(int id)
  70 {
  71         switch (id) {
  72         case RISCV_ISA_EXT_ZICBOM:
  73                 if (!riscv_cbom_block_size) {
  74                         pr_err("Zicbom detected in ISA string, but no cbom-block-size found\n");
  75                         return false;
  76                 } else if (!is_power_of_2(riscv_cbom_block_size)) {
  77                         pr_err("cbom-block-size present, but is not a power-of-2\n");
  78                         return false;
  79                 }
  80                 return true;
  81         case RISCV_ISA_EXT_ZICBOZ:
  82                 if (!riscv_cboz_block_size) {
  83                         pr_err("Zicboz detected in ISA string, but no cboz-block-size found\n");
  84                         return false;
  85                 } else if (!is_power_of_2(riscv_cboz_block_size)) {
  86                         pr_err("cboz-block-size present, but is not a power-of-2\n");
  87                         return false;
  88                 }
  89                 return true;
  90         }
  91
  92         return true;
  93 }
  94
  95 void __init riscv_fill_hwcap(void)
  96 {
  97         struct device_node *node;
  98         const char *isa;
  99         char print_str[NUM_ALPHA_EXTS + 1];
 100         int i, j, rc;
 101         unsigned long isa2hwcap[26] = {0};
 102         unsigned long hartid;
 103
 104         isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I;
 105         isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M;
 106         isa2hwcap['a' - 'a'] = COMPAT_HWCAP_ISA_A;
 107         isa2hwcap['f' - 'a'] = COMPAT_HWCAP_ISA_F;
 108         isa2hwcap['d' - 'a'] = COMPAT_HWCAP_ISA_D;
 109         isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C;
 110         isa2hwcap['v' - 'a'] = COMPAT_HWCAP_ISA_V;
 111
 112         elf_hwcap = 0;
 113
 114         bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX);
 115
 116         for_each_of_cpu_node(node) {
 117                 unsigned long this_hwcap = 0;
 118                 DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX);
 119                 const char *temp;
 120
 121                 rc = riscv_of_processor_hartid(node, &hartid);
 122                 if (rc < 0)
 123                         continue;
 124
 125                 if (of_property_read_string(node, "riscv,isa", &isa)) {
 126                         pr_warn("Unable to find \"riscv,isa\" devicetree entry\n");
 127                         continue;
 128                 }
 129
 130                 temp = isa;
 131 #if IS_ENABLED(CONFIG_32BIT)
 132                 if (!strncmp(isa, "rv32", 4))
 133                         isa += 4;
 134 #elif IS_ENABLED(CONFIG_64BIT)
 135                 if (!strncmp(isa, "rv64", 4))
 136                         isa += 4;
 137 #endif
 138                 /* The riscv,isa DT property must start with rv64 or rv32 */
 139                 if (temp == isa)
 140                         continue;
 141                 bitmap_zero(this_isa, RISCV_ISA_EXT_MAX);
 142                 for (; *isa; ++isa) {
 143                         const char *ext = isa++;
 144                         const char *ext_end = isa;
 145                         bool ext_long = false, ext_err = false;
 146
 147                         switch (*ext) {
 148                         case 's':
 149                                 /**
 150                                  * Workaround for invalid single-letter 's' & 'u'(QEMU).
 151                                  * No need to set the bit in riscv_isa as 's' & 'u' are
 152                                  * not valid ISA extensions. It works until multi-letter
 153                                  * extension starting with "Su" appears.
 154                                  */
 155                                 if (ext[-1] != '_' && ext[1] == 'u') {
 156                                         ++isa;
 157                                         ext_err = true;
 158                                         break;
 159                                 }
 160                                 fallthrough;
 161                         case 'x':
 162                         case 'z':
 163                                 ext_long = true;
 164                                 /* Multi-letter extension must be delimited */
 165                                 for (; *isa && *isa != '_'; ++isa)
 166                                         if (unlikely(!islower(*isa)
 167                                                      && !isdigit(*isa)))
 168                                                 ext_err = true;
 169                                 /* Parse backwards */
 170                                 ext_end = isa;
 171                                 if (unlikely(ext_err))
 172                                         break;
 173                                 if (!isdigit(ext_end[-1]))
 174                                         break;
 175                                 /* Skip the minor version */
 176                                 while (isdigit(*--ext_end))
 177                                         ;
 178                                 if (ext_end[0] != 'p'
 179                                     || !isdigit(ext_end[-1])) {
 180                                         /* Advance it to offset the pre-decrement */
 181                                         ++ext_end;
 182                                         break;
 183                                 }
 184                                 /* Skip the major version */
 185                                 while (isdigit(*--ext_end))
 186                                         ;
 187                                 ++ext_end;
 188                                 break;
 189                         default:
 190                                 if (unlikely(!islower(*ext))) {
 191                                         ext_err = true;
 192                                         break;
 193                                 }
 194                                 /* Find next extension */
 195                                 if (!isdigit(*isa))
 196                                         break;
 197                                 /* Skip the minor version */
 198                                 while (isdigit(*++isa))
 199                                         ;
 200                                 if (*isa != 'p')
 201                                         break;
 202                                 if (!isdigit(*++isa)) {
 203                                         --isa;
 204                                         break;
 205                                 }
 206                                 /* Skip the major version */
 207                                 while (isdigit(*++isa))
 208                                         ;
 209                                 break;
 210                         }
 211                         if (*isa != '_')
 212                                 --isa;
 213
 214 #define SET_ISA_EXT_MAP(name, bit)                                              \
 215                         do {                                                    \
 216                                 if ((ext_end - ext == sizeof(name) - 1) &&      \
 217                                      !memcmp(ext, name, sizeof(name) - 1) &&    \
 218                                      riscv_isa_extension_check(bit))            \
 219                                         set_bit(bit, this_isa);                 \
 220                         } while (false)                                         \
 221
 222                         if (unlikely(ext_err))
 223                                 continue;
 224                         if (!ext_long) {
 225                                 int nr = *ext - 'a';
 226
 227                                 if (riscv_isa_extension_check(nr)) {
 228                                         this_hwcap |= isa2hwcap[nr];
 229                                         set_bit(nr, this_isa);
 230                                 }
 231                         } else {
 232                                 /* sorted alphabetically */
 233                                 SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA);
 234                                 SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA);
 235                                 SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF);
 236                                 SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC);
 237                                 SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL);
 238                                 SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT);
 239                                 SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT);
 240                                 SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB);
 241                                 SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM);
 242                                 SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ);
 243                                 SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE);
 244                         }
 245 #undef SET_ISA_EXT_MAP
 246                 }
 247
 248                 /*
 249                  * All "okay" hart should have same isa. Set HWCAP based on
 250                  * common capabilities of every "okay" hart, in case they don't
 251                  * have.
 252                  */
 253                 if (elf_hwcap)
 254                         elf_hwcap &= this_hwcap;
 255                 else
 256                         elf_hwcap = this_hwcap;
 257
 258                 if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX))
 259                         bitmap_copy(riscv_isa, this_isa, RISCV_ISA_EXT_MAX);
 260                 else
 261                         bitmap_and(riscv_isa, riscv_isa, this_isa, RISCV_ISA_EXT_MAX);
 262         }
 263
 264         /* We don't support systems with F but without D, so mask those out
 265          * here. */
 266         if ((elf_hwcap & COMPAT_HWCAP_ISA_F) && !(elf_hwcap & COMPAT_HWCAP_ISA_D)) {
 267                 pr_info("This kernel does not support systems with F but not D\n");
 268                 elf_hwcap &= ~COMPAT_HWCAP_ISA_F;
 269         }
 270
 271         if (elf_hwcap & COMPAT_HWCAP_ISA_V) {
 272                 /*
 273                  * ISA string in device tree might have 'v' flag, but
 274                  * CONFIG_RISCV_ISA_V is disabled in kernel.
 275                  * Clear V flag in elf_hwcap if CONFIG_RISCV_ISA_V is disabled.
 276                  */
 277                 if (!IS_ENABLED(CONFIG_RISCV_ISA_V))
 278                         elf_hwcap &= ~COMPAT_HWCAP_ISA_V;
 279         }
 280
 281         memset(print_str, 0, sizeof(print_str));
 282         for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
 283                 if (riscv_isa[0] & BIT_MASK(i))
 284                         print_str[j++] = (char)('a' + i);
 285         pr_info("riscv: base ISA extensions %s\n", print_str);
 286
 287         memset(print_str, 0, sizeof(print_str));
 288         for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++)
 289                 if (elf_hwcap & BIT_MASK(i))
 290                         print_str[j++] = (char)('a' + i);
 291         pr_info("riscv: ELF capabilities %s\n", print_str);
 292 }
 293
 294 #ifdef CONFIG_RISCV_ALTERNATIVE
 295 /*
 296  * Alternative patch sites consider 48 bits when determining when to patch
 297  * the old instruction sequence with the new. These bits are broken into a
 298  * 16-bit vendor ID and a 32-bit patch ID. A non-zero vendor ID means the
 299  * patch site is for an erratum, identified by the 32-bit patch ID. When
 300  * the vendor ID is zero, the patch site is for a cpufeature. cpufeatures
 301  * further break down patch ID into two 16-bit numbers. The lower 16 bits
 302  * are the cpufeature ID and the upper 16 bits are used for a value specific
 303  * to the cpufeature and patch site. If the upper 16 bits are zero, then it
 304  * implies no specific value is specified. cpufeatures that want to control
 305  * patching on a per-site basis will provide non-zero values and implement
 306  * checks here. The checks return true when patching should be done, and
 307  * false otherwise.
 308  */
 309 static bool riscv_cpufeature_patch_check(u16 id, u16 value)
 310 {
 311         if (!value)
 312                 return true;
 313
 314         switch (id) {
 315         case RISCV_ISA_EXT_ZICBOZ:
 316                 /*
 317                  * Zicboz alternative applications provide the maximum
 318                  * supported block size order, or zero when it doesn't
 319                  * matter. If the current block size exceeds the maximum,
 320                  * then the alternative cannot be applied.
 321                  */
 322                 return riscv_cboz_block_size <= (1U << value);
 323         }
 324
 325         return false;
 326 }
 327
 328 void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin,
 329                                                   struct alt_entry *end,
 330                                                   unsigned int stage)
 331 {
 332         struct alt_entry *alt;
 333         void *oldptr, *altptr;
 334         u16 id, value;
 335
 336         if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
 337                 return;
 338
 339         for (alt = begin; alt < end; alt++) {
 340                 if (alt->vendor_id != 0)
 341                         continue;
 342
 343                 id = PATCH_ID_CPUFEATURE_ID(alt->patch_id);
 344
 345                 if (id >= RISCV_ISA_EXT_MAX) {
 346                         WARN(1, "This extension id:%d is not in ISA extension list", id);
 347                         continue;
 348                 }
 349
 350                 if (!__riscv_isa_extension_available(NULL, id))
 351                         continue;
 352
 353                 value = PATCH_ID_CPUFEATURE_VALUE(alt->patch_id);
 354                 if (!riscv_cpufeature_patch_check(id, value))
 355                         continue;
 356
 357                 oldptr = ALT_OLD_PTR(alt);
 358                 altptr = ALT_ALT_PTR(alt);
 359
 360                 mutex_lock(&text_mutex);
 361                 patch_text_nosync(oldptr, altptr, alt->alt_len);
 362                 riscv_alternative_fix_offsets(oldptr, alt->alt_len, oldptr - altptr);
 363                 mutex_unlock(&text_mutex);
 364         }
 365 }
 366 #endif