1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * Copyright (C) 2019 Western Digital Corporation or its affiliates.
6 * Anup Patel <anup.patel@wdc.com>
9 #ifndef __LINUX_KVM_RISCV_H
10 #define __LINUX_KVM_RISCV_H
14 #include <linux/types.h>
15 #include <asm/bitsperlong.h>
16 #include <asm/ptrace.h>
18 #define __KVM_HAVE_IRQ_LINE
19 #define __KVM_HAVE_READONLY_MEM
21 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
23 #define KVM_INTERRUPT_SET -1U
24 #define KVM_INTERRUPT_UNSET -2U
26 /* for KVM_GET_REGS and KVM_SET_REGS */
30 /* for KVM_GET_FPU and KVM_SET_FPU */
34 /* KVM Debug exit structure */
35 struct kvm_debug_exit_arch {
38 /* for KVM_SET_GUEST_DEBUG */
39 struct kvm_guest_debug_arch {
42 /* definition of registers in kvm_run */
43 struct kvm_sync_regs {
46 /* for KVM_GET_SREGS and KVM_SET_SREGS */
50 /* CONFIG registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
51 struct kvm_riscv_config {
53 unsigned long zicbom_block_size;
54 unsigned long mvendorid;
55 unsigned long marchid;
57 unsigned long zicboz_block_size;
60 /* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
61 struct kvm_riscv_core {
62 struct user_regs_struct regs;
66 /* Possible privilege modes for kvm_riscv_core */
67 #define KVM_RISCV_MODE_S 1
68 #define KVM_RISCV_MODE_U 0
70 /* General CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
71 struct kvm_riscv_csr {
72 unsigned long sstatus;
75 unsigned long sscratch;
81 unsigned long scounteren;
84 /* AIA CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
85 struct kvm_riscv_aia_csr {
86 unsigned long siselect;
91 unsigned long iprio1h;
92 unsigned long iprio2h;
95 /* TIMER registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
96 struct kvm_riscv_timer {
104 * ISA extension IDs specific to KVM. This is not the same as the host ISA
105 * extension IDs as that is internal to the host and should not be exposed
106 * to the guest. This should always be contiguous to keep the mapping simple
107 * in KVM implementation.
109 enum KVM_RISCV_ISA_EXT_ID {
110 KVM_RISCV_ISA_EXT_A = 0,
117 KVM_RISCV_ISA_EXT_SVPBMT,
118 KVM_RISCV_ISA_EXT_SSTC,
119 KVM_RISCV_ISA_EXT_SVINVAL,
120 KVM_RISCV_ISA_EXT_ZIHINTPAUSE,
121 KVM_RISCV_ISA_EXT_ZICBOM,
122 KVM_RISCV_ISA_EXT_ZICBOZ,
123 KVM_RISCV_ISA_EXT_ZBB,
124 KVM_RISCV_ISA_EXT_SSAIA,
125 KVM_RISCV_ISA_EXT_SVNAPOT,
126 KVM_RISCV_ISA_EXT_MAX,
130 * SBI extension IDs specific to KVM. This is not the same as the SBI
131 * extension IDs defined by the RISC-V SBI specification.
133 enum KVM_RISCV_SBI_EXT_ID {
134 KVM_RISCV_SBI_EXT_V01 = 0,
135 KVM_RISCV_SBI_EXT_TIME,
136 KVM_RISCV_SBI_EXT_IPI,
137 KVM_RISCV_SBI_EXT_RFENCE,
138 KVM_RISCV_SBI_EXT_SRST,
139 KVM_RISCV_SBI_EXT_HSM,
140 KVM_RISCV_SBI_EXT_PMU,
141 KVM_RISCV_SBI_EXT_EXPERIMENTAL,
142 KVM_RISCV_SBI_EXT_VENDOR,
143 KVM_RISCV_SBI_EXT_MAX,
146 /* Possible states for kvm_riscv_timer */
147 #define KVM_RISCV_TIMER_STATE_OFF 0
148 #define KVM_RISCV_TIMER_STATE_ON 1
150 #define KVM_REG_SIZE(id) \
151 (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
153 /* If you need to interpret the index values, here is the key: */
154 #define KVM_REG_RISCV_TYPE_MASK 0x00000000FF000000
155 #define KVM_REG_RISCV_TYPE_SHIFT 24
156 #define KVM_REG_RISCV_SUBTYPE_MASK 0x0000000000FF0000
157 #define KVM_REG_RISCV_SUBTYPE_SHIFT 16
159 /* Config registers are mapped as type 1 */
160 #define KVM_REG_RISCV_CONFIG (0x01 << KVM_REG_RISCV_TYPE_SHIFT)
161 #define KVM_REG_RISCV_CONFIG_REG(name) \
162 (offsetof(struct kvm_riscv_config, name) / sizeof(unsigned long))
164 /* Core registers are mapped as type 2 */
165 #define KVM_REG_RISCV_CORE (0x02 << KVM_REG_RISCV_TYPE_SHIFT)
166 #define KVM_REG_RISCV_CORE_REG(name) \
167 (offsetof(struct kvm_riscv_core, name) / sizeof(unsigned long))
169 /* Control and status registers are mapped as type 3 */
170 #define KVM_REG_RISCV_CSR (0x03 << KVM_REG_RISCV_TYPE_SHIFT)
171 #define KVM_REG_RISCV_CSR_GENERAL (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT)
172 #define KVM_REG_RISCV_CSR_AIA (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT)
173 #define KVM_REG_RISCV_CSR_REG(name) \
174 (offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long))
175 #define KVM_REG_RISCV_CSR_AIA_REG(name) \
176 (offsetof(struct kvm_riscv_aia_csr, name) / sizeof(unsigned long))
178 /* Timer registers are mapped as type 4 */
179 #define KVM_REG_RISCV_TIMER (0x04 << KVM_REG_RISCV_TYPE_SHIFT)
180 #define KVM_REG_RISCV_TIMER_REG(name) \
181 (offsetof(struct kvm_riscv_timer, name) / sizeof(__u64))
183 /* F extension registers are mapped as type 5 */
184 #define KVM_REG_RISCV_FP_F (0x05 << KVM_REG_RISCV_TYPE_SHIFT)
185 #define KVM_REG_RISCV_FP_F_REG(name) \
186 (offsetof(struct __riscv_f_ext_state, name) / sizeof(__u32))
188 /* D extension registers are mapped as type 6 */
189 #define KVM_REG_RISCV_FP_D (0x06 << KVM_REG_RISCV_TYPE_SHIFT)
190 #define KVM_REG_RISCV_FP_D_REG(name) \
191 (offsetof(struct __riscv_d_ext_state, name) / sizeof(__u64))
193 /* ISA Extension registers are mapped as type 7 */
194 #define KVM_REG_RISCV_ISA_EXT (0x07 << KVM_REG_RISCV_TYPE_SHIFT)
196 /* SBI extension registers are mapped as type 8 */
197 #define KVM_REG_RISCV_SBI_EXT (0x08 << KVM_REG_RISCV_TYPE_SHIFT)
198 #define KVM_REG_RISCV_SBI_SINGLE (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT)
199 #define KVM_REG_RISCV_SBI_MULTI_EN (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT)
200 #define KVM_REG_RISCV_SBI_MULTI_DIS (0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT)
201 #define KVM_REG_RISCV_SBI_MULTI_REG(__ext_id) \
202 ((__ext_id) / __BITS_PER_LONG)
203 #define KVM_REG_RISCV_SBI_MULTI_MASK(__ext_id) \
204 (1UL << ((__ext_id) % __BITS_PER_LONG))
205 #define KVM_REG_RISCV_SBI_MULTI_REG_LAST \
206 KVM_REG_RISCV_SBI_MULTI_REG(KVM_RISCV_SBI_EXT_MAX - 1)
208 /* Device Control API: RISC-V AIA */
209 #define KVM_DEV_RISCV_APLIC_ALIGN 0x1000
210 #define KVM_DEV_RISCV_APLIC_SIZE 0x4000
211 #define KVM_DEV_RISCV_APLIC_MAX_HARTS 0x4000
212 #define KVM_DEV_RISCV_IMSIC_ALIGN 0x1000
213 #define KVM_DEV_RISCV_IMSIC_SIZE 0x1000
215 #define KVM_DEV_RISCV_AIA_GRP_CONFIG 0
216 #define KVM_DEV_RISCV_AIA_CONFIG_MODE 0
217 #define KVM_DEV_RISCV_AIA_CONFIG_IDS 1
218 #define KVM_DEV_RISCV_AIA_CONFIG_SRCS 2
219 #define KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS 3
220 #define KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT 4
221 #define KVM_DEV_RISCV_AIA_CONFIG_HART_BITS 5
222 #define KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS 6
225 * Modes of RISC-V AIA device:
226 * 1) EMUL (aka Emulation): Trap-n-emulate IMSIC
227 * 2) HWACCEL (aka HW Acceleration): Virtualize IMSIC using IMSIC guest files
228 * 3) AUTO (aka Automatic): Virtualize IMSIC using IMSIC guest files whenever
229 * available otherwise fallback to trap-n-emulation
231 #define KVM_DEV_RISCV_AIA_MODE_EMUL 0
232 #define KVM_DEV_RISCV_AIA_MODE_HWACCEL 1
233 #define KVM_DEV_RISCV_AIA_MODE_AUTO 2
235 #define KVM_DEV_RISCV_AIA_IDS_MIN 63
236 #define KVM_DEV_RISCV_AIA_IDS_MAX 2048
237 #define KVM_DEV_RISCV_AIA_SRCS_MAX 1024
238 #define KVM_DEV_RISCV_AIA_GROUP_BITS_MAX 8
239 #define KVM_DEV_RISCV_AIA_GROUP_SHIFT_MIN 24
240 #define KVM_DEV_RISCV_AIA_GROUP_SHIFT_MAX 56
241 #define KVM_DEV_RISCV_AIA_HART_BITS_MAX 16
242 #define KVM_DEV_RISCV_AIA_GUEST_BITS_MAX 8
244 #define KVM_DEV_RISCV_AIA_GRP_ADDR 1
245 #define KVM_DEV_RISCV_AIA_ADDR_APLIC 0
246 #define KVM_DEV_RISCV_AIA_ADDR_IMSIC(__vcpu) (1 + (__vcpu))
247 #define KVM_DEV_RISCV_AIA_ADDR_MAX \
248 (1 + KVM_DEV_RISCV_APLIC_MAX_HARTS)
250 #define KVM_DEV_RISCV_AIA_GRP_CTRL 2
251 #define KVM_DEV_RISCV_AIA_CTRL_INIT 0
254 * The device attribute type contains the memory mapped offset of the
255 * APLIC register (range 0x0000-0x3FFF) and it must be 4-byte aligned.
257 #define KVM_DEV_RISCV_AIA_GRP_APLIC 3
260 * The lower 12-bits of the device attribute type contains the iselect
261 * value of the IMSIC register (range 0x70-0xFF) whereas the higher order
262 * bits contains the VCPU id.
264 #define KVM_DEV_RISCV_AIA_GRP_IMSIC 4
265 #define KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS 12
266 #define KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK \
267 ((1U << KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) - 1)
268 #define KVM_DEV_RISCV_AIA_IMSIC_MKATTR(__vcpu, __isel) \
269 (((__vcpu) << KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) | \
270 ((__isel) & KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK))
271 #define KVM_DEV_RISCV_AIA_IMSIC_GET_ISEL(__attr) \
272 ((__attr) & KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK)
273 #define KVM_DEV_RISCV_AIA_IMSIC_GET_VCPU(__attr) \
274 ((__attr) >> KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS)
276 /* One single KVM irqchip, ie. the AIA */
277 #define KVM_NR_IRQCHIPS 1
281 #endif /* __LINUX_KVM_RISCV_H */