1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2012 Regents of the University of California
6 #ifndef _ASM_RISCV_PGTABLE_H
7 #define _ASM_RISCV_PGTABLE_H
9 #include <linux/mmzone.h>
10 #include <linux/sizes.h>
12 #include <asm/pgtable-bits.h>
15 #define KERNEL_LINK_ADDR PAGE_OFFSET
18 #define ADDRESS_SPACE_END (UL(-1))
21 /* Leave 2GB for kernel and BPF at the end of the address space */
22 #define KERNEL_LINK_ADDR (ADDRESS_SPACE_END - SZ_2G + 1)
24 #define KERNEL_LINK_ADDR PAGE_OFFSET
27 #define VMALLOC_SIZE (KERN_VIRT_SIZE >> 1)
28 #define VMALLOC_END (PAGE_OFFSET - 1)
29 #define VMALLOC_START (PAGE_OFFSET - VMALLOC_SIZE)
31 #define BPF_JIT_REGION_SIZE (SZ_128M)
33 /* KASLR should leave at least 128MB for BPF after the kernel */
34 #define BPF_JIT_REGION_START PFN_ALIGN((unsigned long)&_end)
35 #define BPF_JIT_REGION_END (BPF_JIT_REGION_START + BPF_JIT_REGION_SIZE)
37 #define BPF_JIT_REGION_START (PAGE_OFFSET - BPF_JIT_REGION_SIZE)
38 #define BPF_JIT_REGION_END (VMALLOC_END)
41 /* Modules always live before the kernel */
43 #define MODULES_VADDR (PFN_ALIGN((unsigned long)&_end) - SZ_2G)
44 #define MODULES_END (PFN_ALIGN((unsigned long)&_start))
48 * Roughly size the vmemmap space to be large enough to fit enough
49 * struct pages to map half the virtual address space. Then
50 * position vmemmap directly below the VMALLOC region.
52 #define VMEMMAP_SHIFT \
53 (CONFIG_VA_BITS - PAGE_SHIFT - 1 + STRUCT_PAGE_MAX_SHIFT)
54 #define VMEMMAP_SIZE BIT(VMEMMAP_SHIFT)
55 #define VMEMMAP_END (VMALLOC_START - 1)
56 #define VMEMMAP_START (VMALLOC_START - VMEMMAP_SIZE)
59 * Define vmemmap for pfn_to_page & page_to_pfn calls. Needed if kernel
60 * is configured with CONFIG_SPARSEMEM_VMEMMAP enabled.
62 #define vmemmap ((struct page *)VMEMMAP_START)
64 #define PCI_IO_SIZE SZ_16M
65 #define PCI_IO_END VMEMMAP_START
66 #define PCI_IO_START (PCI_IO_END - PCI_IO_SIZE)
68 #define FIXADDR_TOP PCI_IO_START
70 #define FIXADDR_SIZE PMD_SIZE
72 #define FIXADDR_SIZE PGDIR_SIZE
74 #define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE)
78 #ifdef CONFIG_XIP_KERNEL
79 #define XIP_OFFSET SZ_8M
86 /* Page Upper Directory not used in RISC-V */
87 #include <asm-generic/pgtable-nopud.h>
89 #include <asm/tlbflush.h>
90 #include <linux/mm_types.h>
93 #include <asm/pgtable-64.h>
95 #include <asm/pgtable-32.h>
96 #endif /* CONFIG_64BIT */
98 #ifdef CONFIG_XIP_KERNEL
99 #define XIP_FIXUP(addr) ({ \
100 uintptr_t __a = (uintptr_t)(addr); \
101 (__a >= CONFIG_XIP_PHYS_ADDR && __a < CONFIG_XIP_PHYS_ADDR + SZ_16M) ? \
102 __a - CONFIG_XIP_PHYS_ADDR + CONFIG_PHYS_RAM_BASE - XIP_OFFSET :\
106 #define XIP_FIXUP(addr) (addr)
107 #endif /* CONFIG_XIP_KERNEL */
110 /* Number of entries in the page global directory */
111 #define PTRS_PER_PGD (PAGE_SIZE / sizeof(pgd_t))
112 /* Number of entries in the page table */
113 #define PTRS_PER_PTE (PAGE_SIZE / sizeof(pte_t))
115 /* Number of PGD entries that a user-mode program can use */
116 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
118 /* Page protection bits */
119 #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_USER)
121 #define PAGE_NONE __pgprot(_PAGE_PROT_NONE)
122 #define PAGE_READ __pgprot(_PAGE_BASE | _PAGE_READ)
123 #define PAGE_WRITE __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_WRITE)
124 #define PAGE_EXEC __pgprot(_PAGE_BASE | _PAGE_EXEC)
125 #define PAGE_READ_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC)
126 #define PAGE_WRITE_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | \
127 _PAGE_EXEC | _PAGE_WRITE)
129 #define PAGE_COPY PAGE_READ
130 #define PAGE_COPY_EXEC PAGE_EXEC
131 #define PAGE_COPY_READ_EXEC PAGE_READ_EXEC
132 #define PAGE_SHARED PAGE_WRITE
133 #define PAGE_SHARED_EXEC PAGE_WRITE_EXEC
135 #define _PAGE_KERNEL (_PAGE_READ \
141 #define PAGE_KERNEL __pgprot(_PAGE_KERNEL)
142 #define PAGE_KERNEL_READ __pgprot(_PAGE_KERNEL & ~_PAGE_WRITE)
143 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL | _PAGE_EXEC)
144 #define PAGE_KERNEL_READ_EXEC __pgprot((_PAGE_KERNEL & ~_PAGE_WRITE) \
147 #define PAGE_TABLE __pgprot(_PAGE_TABLE)
150 * The RISC-V ISA doesn't yet specify how to query or modify PMAs, so we can't
151 * change the properties of memory regions.
153 #define _PAGE_IOREMAP _PAGE_KERNEL
155 extern pgd_t swapper_pg_dir[];
157 /* MAP_PRIVATE permissions: xwr (copy-on-write) */
158 #define __P000 PAGE_NONE
159 #define __P001 PAGE_READ
160 #define __P010 PAGE_COPY
161 #define __P011 PAGE_COPY
162 #define __P100 PAGE_EXEC
163 #define __P101 PAGE_READ_EXEC
164 #define __P110 PAGE_COPY_EXEC
165 #define __P111 PAGE_COPY_READ_EXEC
167 /* MAP_SHARED permissions: xwr */
168 #define __S000 PAGE_NONE
169 #define __S001 PAGE_READ
170 #define __S010 PAGE_SHARED
171 #define __S011 PAGE_SHARED
172 #define __S100 PAGE_EXEC
173 #define __S101 PAGE_READ_EXEC
174 #define __S110 PAGE_SHARED_EXEC
175 #define __S111 PAGE_SHARED_EXEC
177 static inline int pmd_present(pmd_t pmd)
179 return (pmd_val(pmd) & (_PAGE_PRESENT | _PAGE_PROT_NONE));
182 static inline int pmd_none(pmd_t pmd)
184 return (pmd_val(pmd) == 0);
187 static inline int pmd_bad(pmd_t pmd)
189 return !pmd_present(pmd);
192 #define pmd_leaf pmd_leaf
193 static inline int pmd_leaf(pmd_t pmd)
195 return pmd_present(pmd) &&
196 (pmd_val(pmd) & (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC));
199 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
204 static inline void pmd_clear(pmd_t *pmdp)
206 set_pmd(pmdp, __pmd(0));
209 static inline pgd_t pfn_pgd(unsigned long pfn, pgprot_t prot)
211 return __pgd((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot));
214 static inline unsigned long _pgd_pfn(pgd_t pgd)
216 return pgd_val(pgd) >> _PAGE_PFN_SHIFT;
219 static inline struct page *pmd_page(pmd_t pmd)
221 return pfn_to_page(pmd_val(pmd) >> _PAGE_PFN_SHIFT);
224 static inline unsigned long pmd_page_vaddr(pmd_t pmd)
226 return (unsigned long)pfn_to_virt(pmd_val(pmd) >> _PAGE_PFN_SHIFT);
229 static inline pte_t pmd_pte(pmd_t pmd)
231 return __pte(pmd_val(pmd));
234 /* Yields the page frame number (PFN) of a page table entry */
235 static inline unsigned long pte_pfn(pte_t pte)
237 return (pte_val(pte) >> _PAGE_PFN_SHIFT);
240 #define pte_page(x) pfn_to_page(pte_pfn(x))
242 /* Constructs a page table entry */
243 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
245 return __pte((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot));
248 #define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot)
250 static inline int pte_present(pte_t pte)
252 return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PROT_NONE));
255 static inline int pte_none(pte_t pte)
257 return (pte_val(pte) == 0);
260 static inline int pte_write(pte_t pte)
262 return pte_val(pte) & _PAGE_WRITE;
265 static inline int pte_exec(pte_t pte)
267 return pte_val(pte) & _PAGE_EXEC;
270 static inline int pte_huge(pte_t pte)
272 return pte_present(pte)
273 && (pte_val(pte) & (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC));
276 static inline int pte_dirty(pte_t pte)
278 return pte_val(pte) & _PAGE_DIRTY;
281 static inline int pte_young(pte_t pte)
283 return pte_val(pte) & _PAGE_ACCESSED;
286 static inline int pte_special(pte_t pte)
288 return pte_val(pte) & _PAGE_SPECIAL;
291 /* static inline pte_t pte_rdprotect(pte_t pte) */
293 static inline pte_t pte_wrprotect(pte_t pte)
295 return __pte(pte_val(pte) & ~(_PAGE_WRITE));
298 /* static inline pte_t pte_mkread(pte_t pte) */
300 static inline pte_t pte_mkwrite(pte_t pte)
302 return __pte(pte_val(pte) | _PAGE_WRITE);
305 /* static inline pte_t pte_mkexec(pte_t pte) */
307 static inline pte_t pte_mkdirty(pte_t pte)
309 return __pte(pte_val(pte) | _PAGE_DIRTY);
312 static inline pte_t pte_mkclean(pte_t pte)
314 return __pte(pte_val(pte) & ~(_PAGE_DIRTY));
317 static inline pte_t pte_mkyoung(pte_t pte)
319 return __pte(pte_val(pte) | _PAGE_ACCESSED);
322 static inline pte_t pte_mkold(pte_t pte)
324 return __pte(pte_val(pte) & ~(_PAGE_ACCESSED));
327 static inline pte_t pte_mkspecial(pte_t pte)
329 return __pte(pte_val(pte) | _PAGE_SPECIAL);
332 static inline pte_t pte_mkhuge(pte_t pte)
337 #ifdef CONFIG_NUMA_BALANCING
339 * See the comment in include/asm-generic/pgtable.h
341 static inline int pte_protnone(pte_t pte)
343 return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PROT_NONE)) == _PAGE_PROT_NONE;
346 static inline int pmd_protnone(pmd_t pmd)
348 return pte_protnone(pmd_pte(pmd));
352 /* Modify page protection bits */
353 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
355 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
358 #define pgd_ERROR(e) \
359 pr_err("%s:%d: bad pgd " PTE_FMT ".\n", __FILE__, __LINE__, pgd_val(e))
362 /* Commit new configuration to MMU hardware */
363 static inline void update_mmu_cache(struct vm_area_struct *vma,
364 unsigned long address, pte_t *ptep)
367 * The kernel assumes that TLBs don't cache invalid entries, but
368 * in RISC-V, SFENCE.VMA specifies an ordering constraint, not a
369 * cache flush; it is necessary even after writing invalid entries.
370 * Relying on flush_tlb_fix_spurious_fault would suffice, but
371 * the extra traps reduce performance. So, eagerly SFENCE.VMA.
373 local_flush_tlb_page(address);
376 #define __HAVE_ARCH_PTE_SAME
377 static inline int pte_same(pte_t pte_a, pte_t pte_b)
379 return pte_val(pte_a) == pte_val(pte_b);
383 * Certain architectures need to do special things when PTEs within
384 * a page table are directly modified. Thus, the following hook is
387 static inline void set_pte(pte_t *ptep, pte_t pteval)
392 void flush_icache_pte(pte_t pte);
394 static inline void set_pte_at(struct mm_struct *mm,
395 unsigned long addr, pte_t *ptep, pte_t pteval)
397 if (pte_present(pteval) && pte_exec(pteval))
398 flush_icache_pte(pteval);
400 set_pte(ptep, pteval);
403 static inline void pte_clear(struct mm_struct *mm,
404 unsigned long addr, pte_t *ptep)
406 set_pte_at(mm, addr, ptep, __pte(0));
409 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
410 static inline int ptep_set_access_flags(struct vm_area_struct *vma,
411 unsigned long address, pte_t *ptep,
412 pte_t entry, int dirty)
414 if (!pte_same(*ptep, entry))
415 set_pte_at(vma->vm_mm, address, ptep, entry);
417 * update_mmu_cache will unconditionally execute, handling both
418 * the case that the PTE changed and the spurious fault case.
423 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
424 static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
425 unsigned long address, pte_t *ptep)
427 return __pte(atomic_long_xchg((atomic_long_t *)ptep, 0));
430 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
431 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
432 unsigned long address,
435 if (!pte_young(*ptep))
437 return test_and_clear_bit(_PAGE_ACCESSED_OFFSET, &pte_val(*ptep));
440 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
441 static inline void ptep_set_wrprotect(struct mm_struct *mm,
442 unsigned long address, pte_t *ptep)
444 atomic_long_and(~(unsigned long)_PAGE_WRITE, (atomic_long_t *)ptep);
447 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
448 static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
449 unsigned long address, pte_t *ptep)
452 * This comment is borrowed from x86, but applies equally to RISC-V:
454 * Clearing the accessed bit without a TLB flush
455 * doesn't cause data corruption. [ It could cause incorrect
456 * page aging and the (mistaken) reclaim of hot pages, but the
457 * chance of that should be relatively low. ]
459 * So as a performance optimization don't flush the TLB when
460 * clearing the accessed bit, it will eventually be flushed by
461 * a context switch or a VM operation anyway. [ In the rare
462 * event of it not getting flushed for a long time the delay
463 * shouldn't really matter because there's no real memory
464 * pressure for swapout to react to. ]
466 return ptep_test_and_clear_young(vma, address, ptep);
470 * Encode and decode a swap entry
472 * Format of swap PTE:
473 * bit 0: _PAGE_PRESENT (zero)
474 * bit 1: _PAGE_PROT_NONE (zero)
475 * bits 2 to 6: swap type
476 * bits 7 to XLEN-1: swap offset
478 #define __SWP_TYPE_SHIFT 2
479 #define __SWP_TYPE_BITS 5
480 #define __SWP_TYPE_MASK ((1UL << __SWP_TYPE_BITS) - 1)
481 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
483 #define MAX_SWAPFILES_CHECK() \
484 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)
486 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
487 #define __swp_offset(x) ((x).val >> __SWP_OFFSET_SHIFT)
488 #define __swp_entry(type, offset) ((swp_entry_t) \
489 { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) })
491 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
492 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
495 * In the RV64 Linux scheme, we give the user half of the virtual-address space
496 * and give the kernel the other (upper) half.
499 #define KERN_VIRT_START (-(BIT(CONFIG_VA_BITS)) + TASK_SIZE)
501 #define KERN_VIRT_START FIXADDR_START
505 * Task size is 0x4000000000 for RV64 or 0x9fc00000 for RV32.
506 * Note that PGDIR_SIZE must evenly divide TASK_SIZE.
509 #define TASK_SIZE (PGDIR_SIZE * PTRS_PER_PGD / 2)
511 #define TASK_SIZE FIXADDR_START
514 #else /* CONFIG_MMU */
516 #define PAGE_SHARED __pgprot(0)
517 #define PAGE_KERNEL __pgprot(0)
518 #define swapper_pg_dir NULL
519 #define TASK_SIZE 0xffffffffUL
520 #define VMALLOC_START 0
521 #define VMALLOC_END TASK_SIZE
523 #endif /* !CONFIG_MMU */
525 #define kern_addr_valid(addr) (1) /* FIXME */
527 extern char _start[];
528 extern void *_dtb_early_va;
529 extern uintptr_t _dtb_early_pa;
530 #if defined(CONFIG_XIP_KERNEL) && defined(CONFIG_MMU)
531 #define dtb_early_va (*(void **)XIP_FIXUP(&_dtb_early_va))
532 #define dtb_early_pa (*(uintptr_t *)XIP_FIXUP(&_dtb_early_pa))
534 #define dtb_early_va _dtb_early_va
535 #define dtb_early_pa _dtb_early_pa
536 #endif /* CONFIG_XIP_KERNEL */
538 void setup_bootmem(void);
539 void paging_init(void);
540 void misc_mem_init(void);
542 #define FIRST_USER_ADDRESS 0
545 * ZERO_PAGE is a global shared page that is always zero,
546 * used for zero-mapped memory areas, etc.
548 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
549 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
551 #endif /* !__ASSEMBLY__ */
553 #endif /* _ASM_RISCV_PGTABLE_H */