1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2017 Andes Technology Corporation
4 * Rick Chen, Andes Technology Corporation <rick@andestech.com>
7 #ifndef __ASM_RISCV_IO_H
8 #define __ASM_RISCV_IO_H
10 #include <linux/types.h>
11 #include <asm/barrier.h>
12 #include <asm/byteorder.h>
14 static inline void sync(void)
18 #define __arch_getb(a) (*(volatile unsigned char *)(a))
19 #define __arch_getw(a) (*(volatile unsigned short *)(a))
20 #define __arch_getl(a) (*(volatile unsigned int *)(a))
21 #define __arch_getq(a) (*(volatile unsigned long long *)(a))
23 #define __arch_putb(v, a) (*(volatile unsigned char *)(a) = (v))
24 #define __arch_putw(v, a) (*(volatile unsigned short *)(a) = (v))
25 #define __arch_putl(v, a) (*(volatile unsigned int *)(a) = (v))
26 #define __arch_putq(v, a) (*(volatile unsigned long long *)(a) = (v))
28 #define __raw_writeb(v, a) __arch_putb(v, a)
29 #define __raw_writew(v, a) __arch_putw(v, a)
30 #define __raw_writel(v, a) __arch_putl(v, a)
31 #define __raw_writeq(v, a) __arch_putq(v, a)
33 #define __raw_readb(a) __arch_getb(a)
34 #define __raw_readw(a) __arch_getw(a)
35 #define __raw_readl(a) __arch_getl(a)
36 #define __raw_readq(a) __arch_getq(a)
38 /* adding for cadence_qspi_apb.c */
39 #define memcpy_fromio(a, c, l) memcpy((a), (c), (l))
40 #define memcpy_toio(c, a, l) memcpy((c), (a), (l))
43 #define __iormb() rmb()
44 #define __iowmb() wmb()
46 static inline void writeb(u8 val, volatile void __iomem *addr)
49 __arch_putb(val, addr);
52 static inline void writew(u16 val, volatile void __iomem *addr)
55 __arch_putw(val, addr);
58 static inline void writel(u32 val, volatile void __iomem *addr)
61 __arch_putl(val, addr);
64 static inline void writeq(u64 val, volatile void __iomem *addr)
67 __arch_putq(val, addr);
70 static inline u8 readb(const volatile void __iomem *addr)
74 val = __arch_getb(addr);
79 static inline u16 readw(const volatile void __iomem *addr)
83 val = __arch_getw(addr);
88 static inline u32 readl(const volatile void __iomem *addr)
92 val = __arch_getl(addr);
97 static inline u64 readq(const volatile void __iomem *addr)
101 val = __arch_getq(addr);
107 * The compiler seems to be incapable of optimising constants
108 * properly. Spell it out to the compiler in some cases.
109 * These are only valid for small values of "off" (< 1<<12)
111 #define __raw_base_writeb(val, base, off) __arch_base_putb(val, base, off)
112 #define __raw_base_writew(val, base, off) __arch_base_putw(val, base, off)
113 #define __raw_base_writel(val, base, off) __arch_base_putl(val, base, off)
115 #define __raw_base_readb(base, off) __arch_base_getb(base, off)
116 #define __raw_base_readw(base, off) __arch_base_getw(base, off)
117 #define __raw_base_readl(base, off) __arch_base_getl(base, off)
119 #define out_arch(type, endian, a, v) __raw_write##type(cpu_to_##endian(v), a)
120 #define in_arch(type, endian, a) endian##_to_cpu(__raw_read##type(a))
122 #define out_le32(a, v) out_arch(l, le32, a, v)
123 #define out_le16(a, v) out_arch(w, le16, a, v)
125 #define in_le32(a) in_arch(l, le32, a)
126 #define in_le16(a) in_arch(w, le16, a)
128 #define out_be32(a, v) out_arch(l, be32, a, v)
129 #define out_be16(a, v) out_arch(w, be16, a, v)
131 #define in_be32(a) in_arch(l, be32, a)
132 #define in_be16(a) in_arch(w, be16, a)
134 #define out_8(a, v) __raw_writeb(v, a)
135 #define in_8(a) __raw_readb(a)
138 * Clear and set bits in one shot. These macros can be used to clear and
139 * set multiple bits in a register using a single call. These macros can
140 * also be used to set a multiple-bit bit pattern using a mask, by
141 * specifying the mask in the 'clear' parameter and the new bit pattern
142 * in the 'set' parameter.
145 #define clrbits(type, addr, clear) \
146 out_##type((addr), in_##type(addr) & ~(clear))
148 #define setbits(type, addr, set) \
149 out_##type((addr), in_##type(addr) | (set))
151 #define clrsetbits(type, addr, clear, set) \
152 out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
154 #define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
155 #define setbits_be32(addr, set) setbits(be32, addr, set)
156 #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
158 #define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
159 #define setbits_le32(addr, set) setbits(le32, addr, set)
160 #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
162 #define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
163 #define setbits_be16(addr, set) setbits(be16, addr, set)
164 #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
166 #define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
167 #define setbits_le16(addr, set) setbits(le16, addr, set)
168 #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
170 #define clrbits_8(addr, clear) clrbits(8, addr, clear)
171 #define setbits_8(addr, set) setbits(8, addr, set)
172 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
175 * Now, pick up the machine-defined IO definitions
176 * #include <asm/arch/io.h>
180 * IO port access primitives
181 * -------------------------
183 * The RISC-V doesn't have special IO access instructions just like ARM;
184 * all IO is memory mapped.
185 * Note that these are defined to perform little endian accesses
186 * only. Their primary purpose is to access PCI and ISA peripherals.
188 * Note that for a big endian machine, this implies that the following
189 * big endian mode connectivity is in place, as described by numerious
192 * PCI: D0-D7 D8-D15 D16-D23 D24-D31
193 * ARM: D24-D31 D16-D23 D8-D15 D0-D7
195 * The machine specific io.h include defines __io to translate an "IO"
196 * address to a memory address.
198 * Note that we prevent GCC re-ordering or caching values in expressions
199 * by introducing sequence points into the in*() definitions. Note that
200 * __raw_* do not guarantee this behaviour.
202 * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
205 #define outb(v, p) __raw_writeb(v, __io(p))
206 #define outw(v, p) __raw_writew(cpu_to_le16(v), __io(p))
207 #define outl(v, p) __raw_writel(cpu_to_le32(v), __io(p))
209 #define inb(p) ({ unsigned int __v = __raw_readb(__io(p)); __v; })
210 #define inw(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; })
211 #define inl(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; })
213 #define outsb(p, d, l) writesb(__io(p), d, l)
214 #define outsw(p, d, l) writesw(__io(p), d, l)
215 #define outsl(p, d, l) writesl(__io(p), d, l)
217 #define insb(p, d, l) readsb(__io(p), d, l)
218 #define insw(p, d, l) readsw(__io(p), d, l)
219 #define insl(p, d, l) readsl(__io(p), d, l)
221 static inline void readsb(unsigned int *addr, void *data, int bytelen)
226 ptr = (unsigned char *)addr;
227 ptr2 = (unsigned char *)data;
236 static inline void readsw(unsigned int *addr, void *data, int wordlen)
239 unsigned short *ptr2;
241 ptr = (unsigned short *)addr;
242 ptr2 = (unsigned short *)data;
251 static inline void readsl(unsigned int *addr, void *data, int longlen)
256 ptr = (unsigned int *)addr;
257 ptr2 = (unsigned int *)data;
266 static inline void writesb(unsigned int *addr, const void *data, int bytelen)
271 ptr = (unsigned char *)addr;
272 ptr2 = (unsigned char *)data;
281 static inline void writesw(unsigned int *addr, const void *data, int wordlen)
284 unsigned short *ptr2;
286 ptr = (unsigned short *)addr;
287 ptr2 = (unsigned short *)data;
296 static inline void writesl(unsigned int *addr, const void *data, int longlen)
301 ptr = (unsigned int *)addr;
302 ptr2 = (unsigned int *)data;
312 #define outb_p(val, port) outb((val), (port))
313 #define outw_p(val, port) outw((val), (port))
314 #define outl_p(val, port) outl((val), (port))
315 #define inb_p(port) inb((port))
316 #define inw_p(port) inw((port))
317 #define inl_p(port) inl((port))
319 #define outsb_p(port, from, len) outsb(port, from, len)
320 #define outsw_p(port, from, len) outsw(port, from, len)
321 #define outsl_p(port, from, len) outsl(port, from, len)
322 #define insb_p(port, to, len) insb(port, to, len)
323 #define insw_p(port, to, len) insw(port, to, len)
324 #define insl_p(port, to, len) insl(port, to, len)
326 #include <asm-generic/io.h>
328 #endif /* __ASM_RISCV_IO_H */