1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2017 Andes Technology Corporation
4 * Rick Chen, Andes Technology Corporation <rick@andestech.com>
7 #ifndef __ASM_RISCV_IO_H
8 #define __ASM_RISCV_IO_H
12 #include <linux/types.h>
13 #include <asm/barrier.h>
14 #include <asm/byteorder.h>
16 static inline void sync(void)
20 #ifdef CONFIG_ARCH_MAP_SYSMEM
21 static inline void *map_sysmem(phys_addr_t paddr, unsigned long len)
23 if (paddr < PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE)
24 paddr = paddr | 0x40000000;
25 return (void *)(uintptr_t)paddr;
28 static inline void *unmap_sysmem(const void *vaddr)
30 phys_addr_t paddr = (phys_addr_t)vaddr;
32 paddr = paddr & ~0x40000000;
33 return (void *)(uintptr_t)paddr;
36 static inline phys_addr_t map_to_sysmem(const void *ptr)
38 return (phys_addr_t)(uintptr_t)ptr;
43 * Generic virtual read/write. Note that we don't support half-word
44 * read/writes. We define __arch_*[bl] here, and leave __arch_*w
45 * to the architecture specific code.
47 #define __arch_getb(a) (*(volatile unsigned char *)(a))
48 #define __arch_getw(a) (*(volatile unsigned short *)(a))
49 #define __arch_getl(a) (*(volatile unsigned int *)(a))
50 #define __arch_getq(a) (*(volatile unsigned long long *)(a))
52 #define __arch_putb(v, a) (*(volatile unsigned char *)(a) = (v))
53 #define __arch_putw(v, a) (*(volatile unsigned short *)(a) = (v))
54 #define __arch_putl(v, a) (*(volatile unsigned int *)(a) = (v))
55 #define __arch_putq(v, a) (*(volatile unsigned long long *)(a) = (v))
57 #define __raw_writeb(v, a) __arch_putb(v, a)
58 #define __raw_writew(v, a) __arch_putw(v, a)
59 #define __raw_writel(v, a) __arch_putl(v, a)
60 #define __raw_writeq(v, a) __arch_putq(v, a)
62 #define __raw_readb(a) __arch_getb(a)
63 #define __raw_readw(a) __arch_getw(a)
64 #define __raw_readl(a) __arch_getl(a)
65 #define __raw_readq(a) __arch_getq(a)
68 #define __iormb() rmb()
69 #define __iowmb() wmb()
71 static inline void writeb(u8 val, volatile void __iomem *addr)
74 __arch_putb(val, addr);
77 static inline void writew(u16 val, volatile void __iomem *addr)
80 __arch_putw(val, addr);
83 static inline void writel(u32 val, volatile void __iomem *addr)
86 __arch_putl(val, addr);
89 static inline void writeq(u64 val, volatile void __iomem *addr)
92 __arch_putq(val, addr);
95 static inline u8 readb(const volatile void __iomem *addr)
99 val = __arch_getb(addr);
104 static inline u16 readw(const volatile void __iomem *addr)
108 val = __arch_getw(addr);
113 static inline u32 readl(const volatile void __iomem *addr)
117 val = __arch_getl(addr);
122 static inline u64 readq(const volatile void __iomem *addr)
126 val = __arch_getq(addr);
132 * The compiler seems to be incapable of optimising constants
133 * properly. Spell it out to the compiler in some cases.
134 * These are only valid for small values of "off" (< 1<<12)
136 #define __raw_base_writeb(val, base, off) __arch_base_putb(val, base, off)
137 #define __raw_base_writew(val, base, off) __arch_base_putw(val, base, off)
138 #define __raw_base_writel(val, base, off) __arch_base_putl(val, base, off)
140 #define __raw_base_readb(base, off) __arch_base_getb(base, off)
141 #define __raw_base_readw(base, off) __arch_base_getw(base, off)
142 #define __raw_base_readl(base, off) __arch_base_getl(base, off)
144 #define out_arch(type, endian, a, v) __raw_write##type(cpu_to_##endian(v), a)
145 #define in_arch(type, endian, a) endian##_to_cpu(__raw_read##type(a))
147 #define out_le32(a, v) out_arch(l, le32, a, v)
148 #define out_le16(a, v) out_arch(w, le16, a, v)
150 #define in_le32(a) in_arch(l, le32, a)
151 #define in_le16(a) in_arch(w, le16, a)
153 #define out_be32(a, v) out_arch(l, be32, a, v)
154 #define out_be16(a, v) out_arch(w, be16, a, v)
156 #define in_be32(a) in_arch(l, be32, a)
157 #define in_be16(a) in_arch(w, be16, a)
159 #define out_8(a, v) __raw_writeb(v, a)
160 #define in_8(a) __raw_readb(a)
163 * Clear and set bits in one shot. These macros can be used to clear and
164 * set multiple bits in a register using a single call. These macros can
165 * also be used to set a multiple-bit bit pattern using a mask, by
166 * specifying the mask in the 'clear' parameter and the new bit pattern
167 * in the 'set' parameter.
170 #define clrbits(type, addr, clear) \
171 out_##type((addr), in_##type(addr) & ~(clear))
173 #define setbits(type, addr, set) \
174 out_##type((addr), in_##type(addr) | (set))
176 #define clrsetbits(type, addr, clear, set) \
177 out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
179 #define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
180 #define setbits_be32(addr, set) setbits(be32, addr, set)
181 #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
183 #define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
184 #define setbits_le32(addr, set) setbits(le32, addr, set)
185 #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
187 #define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
188 #define setbits_be16(addr, set) setbits(be16, addr, set)
189 #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
191 #define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
192 #define setbits_le16(addr, set) setbits(le16, addr, set)
193 #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
195 #define clrbits_8(addr, clear) clrbits(8, addr, clear)
196 #define setbits_8(addr, set) setbits(8, addr, set)
197 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
200 * Now, pick up the machine-defined IO definitions
201 * #include <asm/arch/io.h>
205 * IO port access primitives
206 * -------------------------
208 * The NDS32 doesn't have special IO access instructions just like ARM;
209 * all IO is memory mapped.
210 * Note that these are defined to perform little endian accesses
211 * only. Their primary purpose is to access PCI and ISA peripherals.
213 * Note that for a big endian machine, this implies that the following
214 * big endian mode connectivity is in place, as described by numerious
217 * PCI: D0-D7 D8-D15 D16-D23 D24-D31
218 * ARM: D24-D31 D16-D23 D8-D15 D0-D7
220 * The machine specific io.h include defines __io to translate an "IO"
221 * address to a memory address.
223 * Note that we prevent GCC re-ordering or caching values in expressions
224 * by introducing sequence points into the in*() definitions. Note that
225 * __raw_* do not guarantee this behaviour.
227 * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
230 #define outb(v, p) __raw_writeb(v, __io(p))
231 #define outw(v, p) __raw_writew(cpu_to_le16(v), __io(p))
232 #define outl(v, p) __raw_writel(cpu_to_le32(v), __io(p))
234 #define inb(p) ({ unsigned int __v = __raw_readb(__io(p)); __v; })
235 #define inw(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; })
236 #define inl(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; })
238 #define outsb(p, d, l) writesb(__io(p), d, l)
239 #define outsw(p, d, l) writesw(__io(p), d, l)
240 #define outsl(p, d, l) writesl(__io(p), d, l)
242 #define insb(p, d, l) readsb(__io(p), d, l)
243 #define insw(p, d, l) readsw(__io(p), d, l)
244 #define insl(p, d, l) readsl(__io(p), d, l)
246 static inline void readsb(unsigned int *addr, void *data, int bytelen)
251 ptr = (unsigned char *)addr;
252 ptr2 = (unsigned char *)data;
261 static inline void readsw(unsigned int *addr, void *data, int wordlen)
264 unsigned short *ptr2;
266 ptr = (unsigned short *)addr;
267 ptr2 = (unsigned short *)data;
276 static inline void readsl(unsigned int *addr, void *data, int longlen)
281 ptr = (unsigned int *)addr;
282 ptr2 = (unsigned int *)data;
291 static inline void writesb(unsigned int *addr, const void *data, int bytelen)
296 ptr = (unsigned char *)addr;
297 ptr2 = (unsigned char *)data;
306 static inline void writesw(unsigned int *addr, const void *data, int wordlen)
309 unsigned short *ptr2;
311 ptr = (unsigned short *)addr;
312 ptr2 = (unsigned short *)data;
321 static inline void writesl(unsigned int *addr, const void *data, int longlen)
326 ptr = (unsigned int *)addr;
327 ptr2 = (unsigned int *)data;
337 #define outb_p(val, port) outb((val), (port))
338 #define outw_p(val, port) outw((val), (port))
339 #define outl_p(val, port) outl((val), (port))
340 #define inb_p(port) inb((port))
341 #define inw_p(port) inw((port))
342 #define inl_p(port) inl((port))
344 #define outsb_p(port, from, len) outsb(port, from, len)
345 #define outsw_p(port, from, len) outsw(port, from, len)
346 #define outsl_p(port, from, len) outsl(port, from, len)
347 #define insb_p(port, to, len) insb(port, to, len)
348 #define insw_p(port, to, len) insw(port, to, len)
349 #define insl_p(port, to, len) insl(port, to, len)
352 * DMA-consistent mapping functions. These allocate/free a region of
353 * uncached, unwrite-buffered mapped memory space for use with DMA
354 * devices. This is the "generic" version. The PCI specific version
359 * String version of IO memory access ops:
363 * If this architecture has PCI memory IO, then define the read/write
364 * macros. These should only be used with the cookie passed from
369 #define readb(c) ({ unsigned int __v = \
370 __raw_readb(__mem_pci(c)); __v; })
371 #define readw(c) ({ unsigned int __v = \
372 le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
373 #define readl(c) ({ unsigned int __v = \
374 le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
376 #define writeb(v, c) __raw_writeb(v, __mem_pci(c))
377 #define writew(v, c) __raw_writew(cpu_to_le16(v), __mem_pci(c))
378 #define writel(v, c) __raw_writel(cpu_to_le32(v), __mem_pci(c))
380 #define memset_io(c, v, l) _memset_io(__mem_pci(c), (v), (l))
381 #define memcpy_fromio(a, c, l) _memcpy_fromio((a), __mem_pci(c), (l))
382 #define memcpy_toio(c, a, l) _memcpy_toio(__mem_pci(c), (a), (l))
384 #define eth_io_copy_and_sum(s, c, l, b) \
385 eth_copy_and_sum((s), __mem_pci(c), (l), (b))
387 static inline int check_signature(ulong io_addr, const uchar *s, int len)
392 if (readb(io_addr) != *s)
402 #endif /* __mem_pci */
405 * If this architecture has ISA IO, then define the isa_read/isa_write
410 #define isa_readb(addr) __raw_readb(__mem_isa(addr))
411 #define isa_readw(addr) __raw_readw(__mem_isa(addr))
412 #define isa_readl(addr) __raw_readl(__mem_isa(addr))
413 #define isa_writeb(val, addr) __raw_writeb(val, __mem_isa(addr))
414 #define isa_writew(val, addr) __raw_writew(val, __mem_isa(addr))
415 #define isa_writel(val, addr) __raw_writel(val, __mem_isa(addr))
416 #define isa_memset_io(a, b, c) _memset_io(__mem_isa(a), (b), (c))
417 #define isa_memcpy_fromio(a, b, c) _memcpy_fromio((a), __mem_isa(b), (c))
418 #define isa_memcpy_toio(a, b, c) _memcpy_toio(__mem_isa((a)), (b), (c))
420 #define isa_eth_io_copy_and_sum(a, b, c, d) \
421 eth_copy_and_sum((a), __mem_isa(b), (c), (d))
424 isa_check_signature(ulong io_addr, const uchar *s, int len)
429 if (isa_readb(io_addr) != *s)
440 #else /* __mem_isa */
442 #define isa_readb(addr) (__readwrite_bug("isa_readb"), 0)
443 #define isa_readw(addr) (__readwrite_bug("isa_readw"), 0)
444 #define isa_readl(addr) (__readwrite_bug("isa_readl"), 0)
445 #define isa_writeb(val, addr) __readwrite_bug("isa_writeb")
446 #define isa_writew(val, addr) __readwrite_bug("isa_writew")
447 #define isa_writel(val, addr) __readwrite_bug("isa_writel")
448 #define isa_memset_io(a, b, c) __readwrite_bug("isa_memset_io")
449 #define isa_memcpy_fromio(a, b, c) __readwrite_bug("isa_memcpy_fromio")
450 #define isa_memcpy_toio(a, b, c) __readwrite_bug("isa_memcpy_toio")
452 #define isa_eth_io_copy_and_sum(a, b, c, d) \
453 __readwrite_bug("isa_eth_io_copy_and_sum")
455 #define isa_check_signature(io, sig, len) (0)
457 #endif /* __mem_isa */
458 #endif /* __KERNEL__ */
460 #include <asm-generic/io.h>
462 #endif /* __ASM_RISCV_IO_H */