arch/riscv/include/asm/insn.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (C) 2020 SiFive
   4  */
   5
   6 #include <linux/bits.h>
   7
   8 #define RV_INSN_FUNCT3_MASK     GENMASK(14, 12)
   9 #define RV_INSN_FUNCT3_OPOFF    12
  10 #define RV_INSN_OPCODE_MASK     GENMASK(6, 0)
  11 #define RV_INSN_OPCODE_OPOFF    0
  12 #define RV_INSN_FUNCT12_OPOFF   20
  13
  14 #define RV_ENCODE_FUNCT3(f_)    (RVG_FUNCT3_##f_ << RV_INSN_FUNCT3_OPOFF)
  15 #define RV_ENCODE_FUNCT12(f_)   (RVG_FUNCT12_##f_ << RV_INSN_FUNCT12_OPOFF)
  16
  17 /* The bit field of immediate value in I-type instruction */
  18 #define RV_I_IMM_SIGN_OPOFF     31
  19 #define RV_I_IMM_11_0_OPOFF     20
  20 #define RV_I_IMM_SIGN_OFF       12
  21 #define RV_I_IMM_11_0_OFF       0
  22 #define RV_I_IMM_11_0_MASK      GENMASK(11, 0)
  23
  24 /* The bit field of immediate value in J-type instruction */
  25 #define RV_J_IMM_SIGN_OPOFF     31
  26 #define RV_J_IMM_10_1_OPOFF     21
  27 #define RV_J_IMM_11_OPOFF       20
  28 #define RV_J_IMM_19_12_OPOFF    12
  29 #define RV_J_IMM_SIGN_OFF       20
  30 #define RV_J_IMM_10_1_OFF       1
  31 #define RV_J_IMM_11_OFF         11
  32 #define RV_J_IMM_19_12_OFF      12
  33 #define RV_J_IMM_10_1_MASK      GENMASK(9, 0)
  34 #define RV_J_IMM_11_MASK        GENMASK(0, 0)
  35 #define RV_J_IMM_19_12_MASK     GENMASK(7, 0)
  36
  37 /*
  38  * U-type IMMs contain the upper 20bits [31:20] of an immediate with
  39  * the rest filled in by zeros, so no shifting required. Similarly,
  40  * bit31 contains the signed state, so no sign extension necessary.
  41  */
  42 #define RV_U_IMM_SIGN_OPOFF     31
  43 #define RV_U_IMM_31_12_OPOFF    0
  44 #define RV_U_IMM_31_12_MASK     GENMASK(31, 12)
  45
  46 /* The bit field of immediate value in B-type instruction */
  47 #define RV_B_IMM_SIGN_OPOFF     31
  48 #define RV_B_IMM_10_5_OPOFF     25
  49 #define RV_B_IMM_4_1_OPOFF      8
  50 #define RV_B_IMM_11_OPOFF       7
  51 #define RV_B_IMM_SIGN_OFF       12
  52 #define RV_B_IMM_10_5_OFF       5
  53 #define RV_B_IMM_4_1_OFF        1
  54 #define RV_B_IMM_11_OFF         11
  55 #define RV_B_IMM_10_5_MASK      GENMASK(5, 0)
  56 #define RV_B_IMM_4_1_MASK       GENMASK(3, 0)
  57 #define RV_B_IMM_11_MASK        GENMASK(0, 0)
  58
  59 /* The register offset in RVG instruction */
  60 #define RVG_RS1_OPOFF           15
  61 #define RVG_RS2_OPOFF           20
  62 #define RVG_RD_OPOFF            7
  63 #define RVG_RD_MASK             GENMASK(4, 0)
  64
  65 /* The bit field of immediate value in RVC J instruction */
  66 #define RVC_J_IMM_SIGN_OPOFF    12
  67 #define RVC_J_IMM_4_OPOFF       11
  68 #define RVC_J_IMM_9_8_OPOFF     9
  69 #define RVC_J_IMM_10_OPOFF      8
  70 #define RVC_J_IMM_6_OPOFF       7
  71 #define RVC_J_IMM_7_OPOFF       6
  72 #define RVC_J_IMM_3_1_OPOFF     3
  73 #define RVC_J_IMM_5_OPOFF       2
  74 #define RVC_J_IMM_SIGN_OFF      11
  75 #define RVC_J_IMM_4_OFF         4
  76 #define RVC_J_IMM_9_8_OFF       8
  77 #define RVC_J_IMM_10_OFF        10
  78 #define RVC_J_IMM_6_OFF         6
  79 #define RVC_J_IMM_7_OFF         7
  80 #define RVC_J_IMM_3_1_OFF       1
  81 #define RVC_J_IMM_5_OFF         5
  82 #define RVC_J_IMM_4_MASK        GENMASK(0, 0)
  83 #define RVC_J_IMM_9_8_MASK      GENMASK(1, 0)
  84 #define RVC_J_IMM_10_MASK       GENMASK(0, 0)
  85 #define RVC_J_IMM_6_MASK        GENMASK(0, 0)
  86 #define RVC_J_IMM_7_MASK        GENMASK(0, 0)
  87 #define RVC_J_IMM_3_1_MASK      GENMASK(2, 0)
  88 #define RVC_J_IMM_5_MASK        GENMASK(0, 0)
  89
  90 /* The bit field of immediate value in RVC B instruction */
  91 #define RVC_B_IMM_SIGN_OPOFF    12
  92 #define RVC_B_IMM_4_3_OPOFF     10
  93 #define RVC_B_IMM_7_6_OPOFF     5
  94 #define RVC_B_IMM_2_1_OPOFF     3
  95 #define RVC_B_IMM_5_OPOFF       2
  96 #define RVC_B_IMM_SIGN_OFF      8
  97 #define RVC_B_IMM_4_3_OFF       3
  98 #define RVC_B_IMM_7_6_OFF       6
  99 #define RVC_B_IMM_2_1_OFF       1
 100 #define RVC_B_IMM_5_OFF         5
 101 #define RVC_B_IMM_4_3_MASK      GENMASK(1, 0)
 102 #define RVC_B_IMM_7_6_MASK      GENMASK(1, 0)
 103 #define RVC_B_IMM_2_1_MASK      GENMASK(1, 0)
 104 #define RVC_B_IMM_5_MASK        GENMASK(0, 0)
 105
 106 #define RVC_INSN_FUNCT4_MASK    GENMASK(15, 12)
 107 #define RVC_INSN_FUNCT4_OPOFF   12
 108 #define RVC_INSN_FUNCT3_MASK    GENMASK(15, 13)
 109 #define RVC_INSN_FUNCT3_OPOFF   13
 110 #define RVC_INSN_J_RS2_MASK     GENMASK(6, 2)
 111 #define RVC_INSN_OPCODE_MASK    GENMASK(1, 0)
 112 #define RVC_ENCODE_FUNCT3(f_)   (RVC_FUNCT3_##f_ << RVC_INSN_FUNCT3_OPOFF)
 113 #define RVC_ENCODE_FUNCT4(f_)   (RVC_FUNCT4_##f_ << RVC_INSN_FUNCT4_OPOFF)
 114
 115 /* The register offset in RVC op=C0 instruction */
 116 #define RVC_C0_RS1_OPOFF        7
 117 #define RVC_C0_RS2_OPOFF        2
 118 #define RVC_C0_RD_OPOFF         2
 119
 120 /* The register offset in RVC op=C1 instruction */
 121 #define RVC_C1_RS1_OPOFF        7
 122 #define RVC_C1_RS2_OPOFF        2
 123 #define RVC_C1_RD_OPOFF         7
 124
 125 /* The register offset in RVC op=C2 instruction */
 126 #define RVC_C2_RS1_OPOFF        7
 127 #define RVC_C2_RS2_OPOFF        2
 128 #define RVC_C2_RD_OPOFF         7
 129
 130 /* parts of opcode for RVG*/
 131 #define RVG_OPCODE_FENCE        0x0f
 132 #define RVG_OPCODE_AUIPC        0x17
 133 #define RVG_OPCODE_BRANCH       0x63
 134 #define RVG_OPCODE_JALR         0x67
 135 #define RVG_OPCODE_JAL          0x6f
 136 #define RVG_OPCODE_SYSTEM       0x73
 137
 138 /* parts of opcode for RVC*/
 139 #define RVC_OPCODE_C0           0x0
 140 #define RVC_OPCODE_C1           0x1
 141 #define RVC_OPCODE_C2           0x2
 142
 143 /* parts of funct3 code for I, M, A extension*/
 144 #define RVG_FUNCT3_JALR         0x0
 145 #define RVG_FUNCT3_BEQ          0x0
 146 #define RVG_FUNCT3_BNE          0x1
 147 #define RVG_FUNCT3_BLT          0x4
 148 #define RVG_FUNCT3_BGE          0x5
 149 #define RVG_FUNCT3_BLTU         0x6
 150 #define RVG_FUNCT3_BGEU         0x7
 151
 152 /* parts of funct3 code for C extension*/
 153 #define RVC_FUNCT3_C_BEQZ       0x6
 154 #define RVC_FUNCT3_C_BNEZ       0x7
 155 #define RVC_FUNCT3_C_J          0x5
 156 #define RVC_FUNCT3_C_JAL        0x1
 157 #define RVC_FUNCT4_C_JR         0x8
 158 #define RVC_FUNCT4_C_JALR       0x9
 159 #define RVC_FUNCT4_C_EBREAK     0x9
 160
 161 #define RVG_FUNCT12_EBREAK      0x1
 162 #define RVG_FUNCT12_SRET        0x102
 163
 164 #define RVG_MATCH_AUIPC         (RVG_OPCODE_AUIPC)
 165 #define RVG_MATCH_JALR          (RV_ENCODE_FUNCT3(JALR) | RVG_OPCODE_JALR)
 166 #define RVG_MATCH_JAL           (RVG_OPCODE_JAL)
 167 #define RVG_MATCH_FENCE         (RVG_OPCODE_FENCE)
 168 #define RVG_MATCH_BEQ           (RV_ENCODE_FUNCT3(BEQ) | RVG_OPCODE_BRANCH)
 169 #define RVG_MATCH_BNE           (RV_ENCODE_FUNCT3(BNE) | RVG_OPCODE_BRANCH)
 170 #define RVG_MATCH_BLT           (RV_ENCODE_FUNCT3(BLT) | RVG_OPCODE_BRANCH)
 171 #define RVG_MATCH_BGE           (RV_ENCODE_FUNCT3(BGE) | RVG_OPCODE_BRANCH)
 172 #define RVG_MATCH_BLTU          (RV_ENCODE_FUNCT3(BLTU) | RVG_OPCODE_BRANCH)
 173 #define RVG_MATCH_BGEU          (RV_ENCODE_FUNCT3(BGEU) | RVG_OPCODE_BRANCH)
 174 #define RVG_MATCH_EBREAK        (RV_ENCODE_FUNCT12(EBREAK) | RVG_OPCODE_SYSTEM)
 175 #define RVG_MATCH_SRET          (RV_ENCODE_FUNCT12(SRET) | RVG_OPCODE_SYSTEM)
 176 #define RVC_MATCH_C_BEQZ        (RVC_ENCODE_FUNCT3(C_BEQZ) | RVC_OPCODE_C1)
 177 #define RVC_MATCH_C_BNEZ        (RVC_ENCODE_FUNCT3(C_BNEZ) | RVC_OPCODE_C1)
 178 #define RVC_MATCH_C_J           (RVC_ENCODE_FUNCT3(C_J) | RVC_OPCODE_C1)
 179 #define RVC_MATCH_C_JAL         (RVC_ENCODE_FUNCT3(C_JAL) | RVC_OPCODE_C1)
 180 #define RVC_MATCH_C_JR          (RVC_ENCODE_FUNCT4(C_JR) | RVC_OPCODE_C2)
 181 #define RVC_MATCH_C_JALR        (RVC_ENCODE_FUNCT4(C_JALR) | RVC_OPCODE_C2)
 182 #define RVC_MATCH_C_EBREAK      (RVC_ENCODE_FUNCT4(C_EBREAK) | RVC_OPCODE_C2)
 183
 184 #define RVG_MASK_AUIPC          (RV_INSN_OPCODE_MASK)
 185 #define RVG_MASK_JALR           (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)
 186 #define RVG_MASK_JAL            (RV_INSN_OPCODE_MASK)
 187 #define RVG_MASK_FENCE          (RV_INSN_OPCODE_MASK)
 188 #define RVC_MASK_C_JALR         (RVC_INSN_FUNCT4_MASK | RVC_INSN_J_RS2_MASK | RVC_INSN_OPCODE_MASK)
 189 #define RVC_MASK_C_JR           (RVC_INSN_FUNCT4_MASK | RVC_INSN_J_RS2_MASK | RVC_INSN_OPCODE_MASK)
 190 #define RVC_MASK_C_JAL          (RVC_INSN_FUNCT3_MASK | RVC_INSN_OPCODE_MASK)
 191 #define RVC_MASK_C_J            (RVC_INSN_FUNCT3_MASK | RVC_INSN_OPCODE_MASK)
 192 #define RVG_MASK_BEQ            (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)
 193 #define RVG_MASK_BNE            (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)
 194 #define RVG_MASK_BLT            (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)
 195 #define RVG_MASK_BGE            (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)
 196 #define RVG_MASK_BLTU           (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)
 197 #define RVG_MASK_BGEU           (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)
 198 #define RVC_MASK_C_BEQZ         (RVC_INSN_FUNCT3_MASK | RVC_INSN_OPCODE_MASK)
 199 #define RVC_MASK_C_BNEZ         (RVC_INSN_FUNCT3_MASK | RVC_INSN_OPCODE_MASK)
 200 #define RVC_MASK_C_EBREAK       0xffff
 201 #define RVG_MASK_EBREAK         0xffffffff
 202 #define RVG_MASK_SRET           0xffffffff
 203
 204 #define __INSN_LENGTH_MASK      _UL(0x3)
 205 #define __INSN_LENGTH_GE_32     _UL(0x3)
 206 #define __INSN_OPCODE_MASK      _UL(0x7F)
 207 #define __INSN_BRANCH_OPCODE    _UL(RVG_OPCODE_BRANCH)
 208
 209 #define __RISCV_INSN_FUNCS(name, mask, val)                             \
 210 static __always_inline bool riscv_insn_is_##name(u32 code)              \
 211 {                                                                       \
 212         BUILD_BUG_ON(~(mask) & (val));                                  \
 213         return (code & (mask)) == (val);                                \
 214 }                                                                       \
 215
 216 #if __riscv_xlen == 32
 217 /* C.JAL is an RV32C-only instruction */
 218 __RISCV_INSN_FUNCS(c_jal, RVC_MASK_C_JAL, RVC_MATCH_C_JAL)
 219 #else
 220 #define riscv_insn_is_c_jal(opcode) 0
 221 #endif
 222 __RISCV_INSN_FUNCS(auipc, RVG_MASK_AUIPC, RVG_MATCH_AUIPC)
 223 __RISCV_INSN_FUNCS(jalr, RVG_MASK_JALR, RVG_MATCH_JALR)
 224 __RISCV_INSN_FUNCS(jal, RVG_MASK_JAL, RVG_MATCH_JAL)
 225 __RISCV_INSN_FUNCS(c_jr, RVC_MASK_C_JR, RVC_MATCH_C_JR)
 226 __RISCV_INSN_FUNCS(c_jalr, RVC_MASK_C_JALR, RVC_MATCH_C_JALR)
 227 __RISCV_INSN_FUNCS(c_j, RVC_MASK_C_J, RVC_MATCH_C_J)
 228 __RISCV_INSN_FUNCS(beq, RVG_MASK_BEQ, RVG_MATCH_BEQ)
 229 __RISCV_INSN_FUNCS(bne, RVG_MASK_BNE, RVG_MATCH_BNE)
 230 __RISCV_INSN_FUNCS(blt, RVG_MASK_BLT, RVG_MATCH_BLT)
 231 __RISCV_INSN_FUNCS(bge, RVG_MASK_BGE, RVG_MATCH_BGE)
 232 __RISCV_INSN_FUNCS(bltu, RVG_MASK_BLTU, RVG_MATCH_BLTU)
 233 __RISCV_INSN_FUNCS(bgeu, RVG_MASK_BGEU, RVG_MATCH_BGEU)
 234 __RISCV_INSN_FUNCS(c_beqz, RVC_MASK_C_BEQZ, RVC_MATCH_C_BEQZ)
 235 __RISCV_INSN_FUNCS(c_bnez, RVC_MASK_C_BNEZ, RVC_MATCH_C_BNEZ)
 236 __RISCV_INSN_FUNCS(c_ebreak, RVC_MASK_C_EBREAK, RVC_MATCH_C_EBREAK)
 237 __RISCV_INSN_FUNCS(ebreak, RVG_MASK_EBREAK, RVG_MATCH_EBREAK)
 238 __RISCV_INSN_FUNCS(sret, RVG_MASK_SRET, RVG_MATCH_SRET)
 239 __RISCV_INSN_FUNCS(fence, RVG_MASK_FENCE, RVG_MATCH_FENCE);
 240
 241 /* special case to catch _any_ system instruction */
 242 static __always_inline bool riscv_insn_is_system(u32 code)
 243 {
 244         return (code & RV_INSN_OPCODE_MASK) == RVG_OPCODE_SYSTEM;
 245 }
 246
 247 /* special case to catch _any_ branch instruction */
 248 static __always_inline bool riscv_insn_is_branch(u32 code)
 249 {
 250         return (code & RV_INSN_OPCODE_MASK) == RVG_OPCODE_BRANCH;
 251 }
 252
 253 #define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
 254 #define RVC_IMM_SIGN(x) (-(((x) >> 12) & 1))
 255 #define RV_X(X, s, mask)  (((X) >> (s)) & (mask))
 256 #define RVC_X(X, s, mask) RV_X(X, s, mask)
 257
 258 #define RV_EXTRACT_RD_REG(x) \
 259         ({typeof(x) x_ = (x); \
 260         (RV_X(x_, RVG_RD_OPOFF, RVG_RD_MASK)); })
 261
 262 #define RV_EXTRACT_UTYPE_IMM(x) \
 263         ({typeof(x) x_ = (x); \
 264         (RV_X(x_, RV_U_IMM_31_12_OPOFF, RV_U_IMM_31_12_MASK)); })
 265
 266 #define RV_EXTRACT_JTYPE_IMM(x) \
 267         ({typeof(x) x_ = (x); \
 268         (RV_X(x_, RV_J_IMM_10_1_OPOFF, RV_J_IMM_10_1_MASK) << RV_J_IMM_10_1_OFF) | \
 269         (RV_X(x_, RV_J_IMM_11_OPOFF, RV_J_IMM_11_MASK) << RV_J_IMM_11_OFF) | \
 270         (RV_X(x_, RV_J_IMM_19_12_OPOFF, RV_J_IMM_19_12_MASK) << RV_J_IMM_19_12_OFF) | \
 271         (RV_IMM_SIGN(x_) << RV_J_IMM_SIGN_OFF); })
 272
 273 #define RV_EXTRACT_ITYPE_IMM(x) \
 274         ({typeof(x) x_ = (x); \
 275         (RV_X(x_, RV_I_IMM_11_0_OPOFF, RV_I_IMM_11_0_MASK)) | \
 276         (RV_IMM_SIGN(x_) << RV_I_IMM_SIGN_OFF); })
 277
 278 #define RV_EXTRACT_BTYPE_IMM(x) \
 279         ({typeof(x) x_ = (x); \
 280         (RV_X(x_, RV_B_IMM_4_1_OPOFF, RV_B_IMM_4_1_MASK) << RV_B_IMM_4_1_OFF) | \
 281         (RV_X(x_, RV_B_IMM_10_5_OPOFF, RV_B_IMM_10_5_MASK) << RV_B_IMM_10_5_OFF) | \
 282         (RV_X(x_, RV_B_IMM_11_OPOFF, RV_B_IMM_11_MASK) << RV_B_IMM_11_OFF) | \
 283         (RV_IMM_SIGN(x_) << RV_B_IMM_SIGN_OFF); })
 284
 285 #define RVC_EXTRACT_JTYPE_IMM(x) \
 286         ({typeof(x) x_ = (x); \
 287         (RVC_X(x_, RVC_J_IMM_3_1_OPOFF, RVC_J_IMM_3_1_MASK) << RVC_J_IMM_3_1_OFF) | \
 288         (RVC_X(x_, RVC_J_IMM_4_OPOFF, RVC_J_IMM_4_MASK) << RVC_J_IMM_4_OFF) | \
 289         (RVC_X(x_, RVC_J_IMM_5_OPOFF, RVC_J_IMM_5_MASK) << RVC_J_IMM_5_OFF) | \
 290         (RVC_X(x_, RVC_J_IMM_6_OPOFF, RVC_J_IMM_6_MASK) << RVC_J_IMM_6_OFF) | \
 291         (RVC_X(x_, RVC_J_IMM_7_OPOFF, RVC_J_IMM_7_MASK) << RVC_J_IMM_7_OFF) | \
 292         (RVC_X(x_, RVC_J_IMM_9_8_OPOFF, RVC_J_IMM_9_8_MASK) << RVC_J_IMM_9_8_OFF) | \
 293         (RVC_X(x_, RVC_J_IMM_10_OPOFF, RVC_J_IMM_10_MASK) << RVC_J_IMM_10_OFF) | \
 294         (RVC_IMM_SIGN(x_) << RVC_J_IMM_SIGN_OFF); })
 295
 296 #define RVC_EXTRACT_BTYPE_IMM(x) \
 297         ({typeof(x) x_ = (x); \
 298         (RVC_X(x_, RVC_B_IMM_2_1_OPOFF, RVC_B_IMM_2_1_MASK) << RVC_B_IMM_2_1_OFF) | \
 299         (RVC_X(x_, RVC_B_IMM_4_3_OPOFF, RVC_B_IMM_4_3_MASK) << RVC_B_IMM_4_3_OFF) | \
 300         (RVC_X(x_, RVC_B_IMM_5_OPOFF, RVC_B_IMM_5_MASK) << RVC_B_IMM_5_OFF) | \
 301         (RVC_X(x_, RVC_B_IMM_7_6_OPOFF, RVC_B_IMM_7_6_MASK) << RVC_B_IMM_7_6_OFF) | \
 302         (RVC_IMM_SIGN(x_) << RVC_B_IMM_SIGN_OFF); })
 303
 304 /*
 305  * Get the immediate from a J-type instruction.
 306  *
 307  * @insn: instruction to process
 308  * Return: immediate
 309  */
 310 static inline s32 riscv_insn_extract_jtype_imm(u32 insn)
 311 {
 312         return RV_EXTRACT_JTYPE_IMM(insn);
 313 }
 314
 315 /*
 316  * Update a J-type instruction with an immediate value.
 317  *
 318  * @insn: pointer to the jtype instruction
 319  * @imm: the immediate to insert into the instruction
 320  */
 321 static inline void riscv_insn_insert_jtype_imm(u32 *insn, s32 imm)
 322 {
 323         /* drop the old IMMs, all jal IMM bits sit at 31:12 */
 324         *insn &= ~GENMASK(31, 12);
 325         *insn |= (RV_X(imm, RV_J_IMM_10_1_OFF, RV_J_IMM_10_1_MASK) << RV_J_IMM_10_1_OPOFF) |
 326                  (RV_X(imm, RV_J_IMM_11_OFF, RV_J_IMM_11_MASK) << RV_J_IMM_11_OPOFF) |
 327                  (RV_X(imm, RV_J_IMM_19_12_OFF, RV_J_IMM_19_12_MASK) << RV_J_IMM_19_12_OPOFF) |
 328                  (RV_X(imm, RV_J_IMM_SIGN_OFF, 1) << RV_J_IMM_SIGN_OPOFF);
 329 }
 330
 331 /*
 332  * Put together one immediate from a U-type and I-type instruction pair.
 333  *
 334  * The U-type contains an upper immediate, meaning bits[31:12] with [11:0]
 335  * being zero, while the I-type contains a 12bit immediate.
 336  * Combined these can encode larger 32bit values and are used for example
 337  * in auipc + jalr pairs to allow larger jumps.
 338  *
 339  * @utype_insn: instruction containing the upper immediate
 340  * @itype_insn: instruction
 341  * Return: combined immediate
 342  */
 343 static inline s32 riscv_insn_extract_utype_itype_imm(u32 utype_insn, u32 itype_insn)
 344 {
 345         s32 imm;
 346
 347         imm = RV_EXTRACT_UTYPE_IMM(utype_insn);
 348         imm += RV_EXTRACT_ITYPE_IMM(itype_insn);
 349
 350         return imm;
 351 }
 352
 353 /*
 354  * Update a set of two instructions (U-type + I-type) with an immediate value.
 355  *
 356  * Used for example in auipc+jalrs pairs the U-type instructions contains
 357  * a 20bit upper immediate representing bits[31:12], while the I-type
 358  * instruction contains a 12bit immediate representing bits[11:0].
 359  *
 360  * This also takes into account that both separate immediates are
 361  * considered as signed values, so if the I-type immediate becomes
 362  * negative (BIT(11) set) the U-type part gets adjusted.
 363  *
 364  * @utype_insn: pointer to the utype instruction of the pair
 365  * @itype_insn: pointer to the itype instruction of the pair
 366  * @imm: the immediate to insert into the two instructions
 367  */
 368 static inline void riscv_insn_insert_utype_itype_imm(u32 *utype_insn, u32 *itype_insn, s32 imm)
 369 {
 370         /* drop possible old IMM values */
 371         *utype_insn &= ~(RV_U_IMM_31_12_MASK);
 372         *itype_insn &= ~(RV_I_IMM_11_0_MASK << RV_I_IMM_11_0_OPOFF);
 373
 374         /* add the adapted IMMs */
 375         *utype_insn |= (imm & RV_U_IMM_31_12_MASK) + ((imm & BIT(11)) << 1);
 376         *itype_insn |= ((imm & RV_I_IMM_11_0_MASK) << RV_I_IMM_11_0_OPOFF);
 377 }