1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copied from arch/arm64/include/asm/hwcap.h
5 * Copyright (C) 2012 ARM Ltd.
6 * Copyright (C) 2017 SiFive
8 #ifndef _ASM_RISCV_HWCAP_H
9 #define _ASM_RISCV_HWCAP_H
11 #include <asm/alternative-macros.h>
12 #include <asm/errno.h>
13 #include <linux/bits.h>
14 #include <uapi/asm/hwcap.h>
16 #define RISCV_ISA_EXT_a ('a' - 'a')
17 #define RISCV_ISA_EXT_c ('c' - 'a')
18 #define RISCV_ISA_EXT_d ('d' - 'a')
19 #define RISCV_ISA_EXT_f ('f' - 'a')
20 #define RISCV_ISA_EXT_h ('h' - 'a')
21 #define RISCV_ISA_EXT_i ('i' - 'a')
22 #define RISCV_ISA_EXT_m ('m' - 'a')
23 #define RISCV_ISA_EXT_s ('s' - 'a')
24 #define RISCV_ISA_EXT_u ('u' - 'a')
27 * These macros represent the logical IDs of each multi-letter RISC-V ISA
28 * extension and are used in the ISA bitmap. The logical IDs start from
29 * RISCV_ISA_EXT_BASE, which allows the 0-25 range to be reserved for single
30 * letter extensions. The maximum, RISCV_ISA_EXT_MAX, is defined in order
31 * to allocate the bitmap and may be increased when necessary.
33 * New extensions should just be added to the bottom, rather than added
34 * alphabetically, in order to avoid unnecessary shuffling.
36 #define RISCV_ISA_EXT_BASE 26
38 #define RISCV_ISA_EXT_SSCOFPMF 26
39 #define RISCV_ISA_EXT_SSTC 27
40 #define RISCV_ISA_EXT_SVINVAL 28
41 #define RISCV_ISA_EXT_SVPBMT 29
42 #define RISCV_ISA_EXT_ZBB 30
43 #define RISCV_ISA_EXT_ZICBOM 31
44 #define RISCV_ISA_EXT_ZIHINTPAUSE 32
45 #define RISCV_ISA_EXT_SVNAPOT 33
46 #define RISCV_ISA_EXT_ZICBOZ 34
47 #define RISCV_ISA_EXT_SMAIA 35
48 #define RISCV_ISA_EXT_SSAIA 36
50 #define RISCV_ISA_EXT_MAX 64
51 #define RISCV_ISA_EXT_NAME_LEN_MAX 32
53 #ifdef CONFIG_RISCV_M_MODE
54 #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA
56 #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SSAIA
61 #include <linux/jump_label.h>
63 struct riscv_isa_ext_data {
64 /* Name of the extension displayed to userspace via /proc/cpuinfo */
65 char uprop[RISCV_ISA_EXT_NAME_LEN_MAX];
66 /* The logical ISA extension ID */
67 unsigned int isa_ext_id;
70 unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);
72 #define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext)
74 bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit);
75 #define riscv_isa_extension_available(isa_bitmap, ext) \
76 __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext)
78 static __always_inline bool
79 riscv_has_extension_likely(const unsigned long ext)
81 compiletime_assert(ext < RISCV_ISA_EXT_MAX,
82 "ext must be < RISCV_ISA_EXT_MAX");
84 if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {
86 ALTERNATIVE("j %l[l_no]", "nop", 0, %[ext], 1)
92 if (!__riscv_isa_extension_available(NULL, ext))
101 static __always_inline bool
102 riscv_has_extension_unlikely(const unsigned long ext)
104 compiletime_assert(ext < RISCV_ISA_EXT_MAX,
105 "ext must be < RISCV_ISA_EXT_MAX");
107 if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {
109 ALTERNATIVE("nop", "j %l[l_yes]", 0, %[ext], 1)
115 if (__riscv_isa_extension_available(NULL, ext))
126 #endif /* _ASM_RISCV_HWCAP_H */