1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copied from arch/arm64/include/asm/hwcap.h
5 * Copyright (C) 2012 ARM Ltd.
6 * Copyright (C) 2017 SiFive
8 #ifndef _ASM_RISCV_HWCAP_H
9 #define _ASM_RISCV_HWCAP_H
11 #include <asm/alternative-macros.h>
12 #include <asm/errno.h>
13 #include <linux/bits.h>
14 #include <uapi/asm/hwcap.h>
16 #define RISCV_ISA_EXT_a ('a' - 'a')
17 #define RISCV_ISA_EXT_c ('c' - 'a')
18 #define RISCV_ISA_EXT_d ('d' - 'a')
19 #define RISCV_ISA_EXT_f ('f' - 'a')
20 #define RISCV_ISA_EXT_h ('h' - 'a')
21 #define RISCV_ISA_EXT_i ('i' - 'a')
22 #define RISCV_ISA_EXT_m ('m' - 'a')
23 #define RISCV_ISA_EXT_s ('s' - 'a')
24 #define RISCV_ISA_EXT_u ('u' - 'a')
27 * Increse this to higher value as kernel support more ISA extensions.
29 #define RISCV_ISA_EXT_MAX 64
30 #define RISCV_ISA_EXT_NAME_LEN_MAX 32
32 /* The base ID for multi-letter ISA extensions */
33 #define RISCV_ISA_EXT_BASE 26
36 * These macros represent the logical ID for each multi-letter RISC-V ISA extension.
37 * The logical ID should start from RISCV_ISA_EXT_BASE and must not exceed
38 * RISCV_ISA_EXT_MAX. 0-25 range is reserved for single letter
39 * extensions while all the multi-letter extensions should define the next
40 * available logical extension id.
41 * Entries are sorted alphabetically.
43 #define RISCV_ISA_EXT_SSCOFPMF 26
44 #define RISCV_ISA_EXT_SSTC 27
45 #define RISCV_ISA_EXT_SVINVAL 28
46 #define RISCV_ISA_EXT_SVNAPOT 29
47 #define RISCV_ISA_EXT_SVPBMT 30
48 #define RISCV_ISA_EXT_ZBB 31
49 #define RISCV_ISA_EXT_ZICBOM 32
50 #define RISCV_ISA_EXT_ZIHINTPAUSE 33
54 #include <linux/jump_label.h>
57 * This yields a mask that user programs can use to figure out what
58 * instruction set this cpu supports.
60 #define ELF_HWCAP (elf_hwcap)
66 extern unsigned long elf_hwcap;
68 struct riscv_isa_ext_data {
69 /* Name of the extension displayed to userspace via /proc/cpuinfo */
70 char uprop[RISCV_ISA_EXT_NAME_LEN_MAX];
71 /* The logical ISA extension ID */
72 unsigned int isa_ext_id;
75 static __always_inline bool
76 riscv_has_extension_likely(const unsigned long ext)
78 compiletime_assert(ext < RISCV_ISA_EXT_MAX,
79 "ext must be < RISCV_ISA_EXT_MAX");
82 ALTERNATIVE("j %l[l_no]", "nop", 0, %[ext], 1)
93 static __always_inline bool
94 riscv_has_extension_unlikely(const unsigned long ext)
96 compiletime_assert(ext < RISCV_ISA_EXT_MAX,
97 "ext must be < RISCV_ISA_EXT_MAX");
100 ALTERNATIVE("nop", "j %l[l_yes]", 0, %[ext], 1)
111 unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);
113 #define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext)
115 bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit);
116 #define riscv_isa_extension_available(isa_bitmap, ext) \
117 __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext)
121 #endif /* _ASM_RISCV_HWCAP_H */