1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2015 Regents of the University of California
5 * Taken from Linux arch/riscv/include/asm/csr.h
8 #ifndef _ASM_RISCV_CSR_H
9 #define _ASM_RISCV_CSR_H
11 #include <linux/const.h>
13 /* Status register flags */
14 #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */
15 #define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */
16 #define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */
17 #define SR_SUM _AC(0x00040000, UL) /* Supervisor access User Memory */
19 #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */
20 #define SR_FS_OFF _AC(0x00000000, UL)
21 #define SR_FS_INITIAL _AC(0x00002000, UL)
22 #define SR_FS_CLEAN _AC(0x00004000, UL)
23 #define SR_FS_DIRTY _AC(0x00006000, UL)
25 #define SR_XS _AC(0x00018000, UL) /* Extension Status */
26 #define SR_XS_OFF _AC(0x00000000, UL)
27 #define SR_XS_INITIAL _AC(0x00008000, UL)
28 #define SR_XS_CLEAN _AC(0x00010000, UL)
29 #define SR_XS_DIRTY _AC(0x00018000, UL)
32 #define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */
34 #define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */
38 #if __riscv_xlen == 32
39 #define SATP_PPN _AC(0x003FFFFF, UL)
40 #define SATP_MODE_32 _AC(0x80000000, UL)
41 #define SATP_MODE SATP_MODE_32
43 #define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL)
44 #define SATP_MODE_39 _AC(0x8000000000000000, UL)
45 #define SATP_MODE SATP_MODE_39
48 /* Interrupt Enable and Interrupt Pending flags */
49 #define SIE_SSIE _AC(0x00000002, UL) /* Software Interrupt Enable */
50 #define SIE_STIE _AC(0x00000020, UL) /* Timer Interrupt Enable */
52 #define EXC_INST_MISALIGNED 0
53 #define EXC_INST_ACCESS 1
54 #define EXC_BREAKPOINT 3
55 #define EXC_LOAD_ACCESS 5
56 #define EXC_STORE_ACCESS 7
58 #define EXC_INST_PAGE_FAULT 12
59 #define EXC_LOAD_PAGE_FAULT 13
60 #define EXC_STORE_PAGE_FAULT 15
64 #define xcsr(csr) #csr
66 #define csr_swap(csr, val) \
68 unsigned long __v = (unsigned long)(val); \
69 __asm__ __volatile__ ("csrrw %0, " xcsr(csr) ", %1" \
70 : "=r" (__v) : "rK" (__v) \
75 #define csr_read(csr) \
77 register unsigned long __v; \
78 __asm__ __volatile__ ("csrr %0, " xcsr(csr) \
84 #define csr_write(csr, val) \
86 unsigned long __v = (unsigned long)(val); \
87 __asm__ __volatile__ ("csrw " xcsr(csr) ", %0" \
92 #define csr_read_set(csr, val) \
94 unsigned long __v = (unsigned long)(val); \
95 __asm__ __volatile__ ("csrrs %0, " xcsr(csr) ", %1" \
96 : "=r" (__v) : "rK" (__v) \
101 #define csr_set(csr, val) \
103 unsigned long __v = (unsigned long)(val); \
104 __asm__ __volatile__ ("csrs " xcsr(csr) ", %0" \
109 #define csr_read_clear(csr, val) \
111 unsigned long __v = (unsigned long)(val); \
112 __asm__ __volatile__ ("csrrc %0, " xcsr(csr) ", %1" \
113 : "=r" (__v) : "rK" (__v) \
118 #define csr_clear(csr, val) \
120 unsigned long __v = (unsigned long)(val); \
121 __asm__ __volatile__ ("csrc " xcsr(csr) ", %0" \
126 #endif /* __ASSEMBLY__ */
128 #endif /* _ASM_RISCV_CSR_H */